1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|*Target Instruction Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ 11 12 13#ifdef GET_INSTRINFO_ENUM 14#undef GET_INSTRINFO_ENUM 15 16enum { 17 ARM_PHI = 0, 18 ARM_INLINEASM = 1, 19 ARM_CFI_INSTRUCTION = 2, 20 ARM_EH_LABEL = 3, 21 ARM_GC_LABEL = 4, 22 ARM_KILL = 5, 23 ARM_EXTRACT_SUBREG = 6, 24 ARM_INSERT_SUBREG = 7, 25 ARM_IMPLICIT_DEF = 8, 26 ARM_SUBREG_TO_REG = 9, 27 ARM_COPY_TO_REGCLASS = 10, 28 ARM_DBG_VALUE = 11, 29 ARM_REG_SEQUENCE = 12, 30 ARM_COPY = 13, 31 ARM_BUNDLE = 14, 32 ARM_LIFETIME_START = 15, 33 ARM_LIFETIME_END = 16, 34 ARM_STACKMAP = 17, 35 ARM_PATCHPOINT = 18, 36 ARM_LOAD_STACK_GUARD = 19, 37 ARM_ABS = 20, 38 ARM_ADCri = 21, 39 ARM_ADCrr = 22, 40 ARM_ADCrsi = 23, 41 ARM_ADCrsr = 24, 42 ARM_ADDSri = 25, 43 ARM_ADDSrr = 26, 44 ARM_ADDSrsi = 27, 45 ARM_ADDSrsr = 28, 46 ARM_ADDri = 29, 47 ARM_ADDrr = 30, 48 ARM_ADDrsi = 31, 49 ARM_ADDrsr = 32, 50 ARM_ADJCALLSTACKDOWN = 33, 51 ARM_ADJCALLSTACKUP = 34, 52 ARM_ADR = 35, 53 ARM_AESD = 36, 54 ARM_AESE = 37, 55 ARM_AESIMC = 38, 56 ARM_AESMC = 39, 57 ARM_ANDri = 40, 58 ARM_ANDrr = 41, 59 ARM_ANDrsi = 42, 60 ARM_ANDrsr = 43, 61 ARM_ASRi = 44, 62 ARM_ASRr = 45, 63 ARM_B = 46, 64 ARM_BCCZi64 = 47, 65 ARM_BCCi64 = 48, 66 ARM_BFC = 49, 67 ARM_BFI = 50, 68 ARM_BICri = 51, 69 ARM_BICrr = 52, 70 ARM_BICrsi = 53, 71 ARM_BICrsr = 54, 72 ARM_BKPT = 55, 73 ARM_BL = 56, 74 ARM_BLX = 57, 75 ARM_BLX_pred = 58, 76 ARM_BLXi = 59, 77 ARM_BL_pred = 60, 78 ARM_BMOVPCB_CALL = 61, 79 ARM_BMOVPCRX_CALL = 62, 80 ARM_BR_JTadd = 63, 81 ARM_BR_JTm = 64, 82 ARM_BR_JTr = 65, 83 ARM_BX = 66, 84 ARM_BXJ = 67, 85 ARM_BX_CALL = 68, 86 ARM_BX_RET = 69, 87 ARM_BX_pred = 70, 88 ARM_Bcc = 71, 89 ARM_CDP = 72, 90 ARM_CDP2 = 73, 91 ARM_CLREX = 74, 92 ARM_CLZ = 75, 93 ARM_CMNri = 76, 94 ARM_CMNzrr = 77, 95 ARM_CMNzrsi = 78, 96 ARM_CMNzrsr = 79, 97 ARM_CMPri = 80, 98 ARM_CMPrr = 81, 99 ARM_CMPrsi = 82, 100 ARM_CMPrsr = 83, 101 ARM_CONSTPOOL_ENTRY = 84, 102 ARM_COPY_STRUCT_BYVAL_I32 = 85, 103 ARM_CPS1p = 86, 104 ARM_CPS2p = 87, 105 ARM_CPS3p = 88, 106 ARM_CRC32B = 89, 107 ARM_CRC32CB = 90, 108 ARM_CRC32CH = 91, 109 ARM_CRC32CW = 92, 110 ARM_CRC32H = 93, 111 ARM_CRC32W = 94, 112 ARM_DBG = 95, 113 ARM_DMB = 96, 114 ARM_DSB = 97, 115 ARM_EORri = 98, 116 ARM_EORrr = 99, 117 ARM_EORrsi = 100, 118 ARM_EORrsr = 101, 119 ARM_FCONSTD = 102, 120 ARM_FCONSTS = 103, 121 ARM_FLDMXDB_UPD = 104, 122 ARM_FLDMXIA = 105, 123 ARM_FLDMXIA_UPD = 106, 124 ARM_FMSTAT = 107, 125 ARM_FSTMXDB_UPD = 108, 126 ARM_FSTMXIA = 109, 127 ARM_FSTMXIA_UPD = 110, 128 ARM_HINT = 111, 129 ARM_HLT = 112, 130 ARM_ISB = 113, 131 ARM_ITasm = 114, 132 ARM_Int_eh_sjlj_dispatchsetup = 115, 133 ARM_Int_eh_sjlj_longjmp = 116, 134 ARM_Int_eh_sjlj_setjmp = 117, 135 ARM_Int_eh_sjlj_setjmp_nofp = 118, 136 ARM_LDA = 119, 137 ARM_LDAB = 120, 138 ARM_LDAEX = 121, 139 ARM_LDAEXB = 122, 140 ARM_LDAEXD = 123, 141 ARM_LDAEXH = 124, 142 ARM_LDAH = 125, 143 ARM_LDC2L_OFFSET = 126, 144 ARM_LDC2L_OPTION = 127, 145 ARM_LDC2L_POST = 128, 146 ARM_LDC2L_PRE = 129, 147 ARM_LDC2_OFFSET = 130, 148 ARM_LDC2_OPTION = 131, 149 ARM_LDC2_POST = 132, 150 ARM_LDC2_PRE = 133, 151 ARM_LDCL_OFFSET = 134, 152 ARM_LDCL_OPTION = 135, 153 ARM_LDCL_POST = 136, 154 ARM_LDCL_PRE = 137, 155 ARM_LDC_OFFSET = 138, 156 ARM_LDC_OPTION = 139, 157 ARM_LDC_POST = 140, 158 ARM_LDC_PRE = 141, 159 ARM_LDMDA = 142, 160 ARM_LDMDA_UPD = 143, 161 ARM_LDMDB = 144, 162 ARM_LDMDB_UPD = 145, 163 ARM_LDMIA = 146, 164 ARM_LDMIA_RET = 147, 165 ARM_LDMIA_UPD = 148, 166 ARM_LDMIB = 149, 167 ARM_LDMIB_UPD = 150, 168 ARM_LDRBT_POST = 151, 169 ARM_LDRBT_POST_IMM = 152, 170 ARM_LDRBT_POST_REG = 153, 171 ARM_LDRB_POST_IMM = 154, 172 ARM_LDRB_POST_REG = 155, 173 ARM_LDRB_PRE_IMM = 156, 174 ARM_LDRB_PRE_REG = 157, 175 ARM_LDRBi12 = 158, 176 ARM_LDRBrs = 159, 177 ARM_LDRD = 160, 178 ARM_LDRD_POST = 161, 179 ARM_LDRD_PRE = 162, 180 ARM_LDREX = 163, 181 ARM_LDREXB = 164, 182 ARM_LDREXD = 165, 183 ARM_LDREXH = 166, 184 ARM_LDRH = 167, 185 ARM_LDRHTi = 168, 186 ARM_LDRHTr = 169, 187 ARM_LDRH_POST = 170, 188 ARM_LDRH_PRE = 171, 189 ARM_LDRLIT_ga_abs = 172, 190 ARM_LDRLIT_ga_pcrel = 173, 191 ARM_LDRLIT_ga_pcrel_ldr = 174, 192 ARM_LDRSB = 175, 193 ARM_LDRSBTi = 176, 194 ARM_LDRSBTr = 177, 195 ARM_LDRSB_POST = 178, 196 ARM_LDRSB_PRE = 179, 197 ARM_LDRSH = 180, 198 ARM_LDRSHTi = 181, 199 ARM_LDRSHTr = 182, 200 ARM_LDRSH_POST = 183, 201 ARM_LDRSH_PRE = 184, 202 ARM_LDRT_POST = 185, 203 ARM_LDRT_POST_IMM = 186, 204 ARM_LDRT_POST_REG = 187, 205 ARM_LDR_POST_IMM = 188, 206 ARM_LDR_POST_REG = 189, 207 ARM_LDR_PRE_IMM = 190, 208 ARM_LDR_PRE_REG = 191, 209 ARM_LDRcp = 192, 210 ARM_LDRi12 = 193, 211 ARM_LDRrs = 194, 212 ARM_LEApcrel = 195, 213 ARM_LEApcrelJT = 196, 214 ARM_LSLi = 197, 215 ARM_LSLr = 198, 216 ARM_LSRi = 199, 217 ARM_LSRr = 200, 218 ARM_MCR = 201, 219 ARM_MCR2 = 202, 220 ARM_MCRR = 203, 221 ARM_MCRR2 = 204, 222 ARM_MLA = 205, 223 ARM_MLAv5 = 206, 224 ARM_MLS = 207, 225 ARM_MOVCCi = 208, 226 ARM_MOVCCi16 = 209, 227 ARM_MOVCCi32imm = 210, 228 ARM_MOVCCr = 211, 229 ARM_MOVCCsi = 212, 230 ARM_MOVCCsr = 213, 231 ARM_MOVPCLR = 214, 232 ARM_MOVPCRX = 215, 233 ARM_MOVTi16 = 216, 234 ARM_MOVTi16_ga_pcrel = 217, 235 ARM_MOV_ga_pcrel = 218, 236 ARM_MOV_ga_pcrel_ldr = 219, 237 ARM_MOVi = 220, 238 ARM_MOVi16 = 221, 239 ARM_MOVi16_ga_pcrel = 222, 240 ARM_MOVi32imm = 223, 241 ARM_MOVr = 224, 242 ARM_MOVr_TC = 225, 243 ARM_MOVsi = 226, 244 ARM_MOVsr = 227, 245 ARM_MOVsra_flag = 228, 246 ARM_MOVsrl_flag = 229, 247 ARM_MRC = 230, 248 ARM_MRC2 = 231, 249 ARM_MRRC = 232, 250 ARM_MRRC2 = 233, 251 ARM_MRS = 234, 252 ARM_MRSsys = 235, 253 ARM_MSR = 236, 254 ARM_MSRi = 237, 255 ARM_MUL = 238, 256 ARM_MULv5 = 239, 257 ARM_MVNCCi = 240, 258 ARM_MVNi = 241, 259 ARM_MVNr = 242, 260 ARM_MVNsi = 243, 261 ARM_MVNsr = 244, 262 ARM_ORRri = 245, 263 ARM_ORRrr = 246, 264 ARM_ORRrsi = 247, 265 ARM_ORRrsr = 248, 266 ARM_PICADD = 249, 267 ARM_PICLDR = 250, 268 ARM_PICLDRB = 251, 269 ARM_PICLDRH = 252, 270 ARM_PICLDRSB = 253, 271 ARM_PICLDRSH = 254, 272 ARM_PICSTR = 255, 273 ARM_PICSTRB = 256, 274 ARM_PICSTRH = 257, 275 ARM_PKHBT = 258, 276 ARM_PKHTB = 259, 277 ARM_PLDWi12 = 260, 278 ARM_PLDWrs = 261, 279 ARM_PLDi12 = 262, 280 ARM_PLDrs = 263, 281 ARM_PLIi12 = 264, 282 ARM_PLIrs = 265, 283 ARM_QADD = 266, 284 ARM_QADD16 = 267, 285 ARM_QADD8 = 268, 286 ARM_QASX = 269, 287 ARM_QDADD = 270, 288 ARM_QDSUB = 271, 289 ARM_QSAX = 272, 290 ARM_QSUB = 273, 291 ARM_QSUB16 = 274, 292 ARM_QSUB8 = 275, 293 ARM_RBIT = 276, 294 ARM_REV = 277, 295 ARM_REV16 = 278, 296 ARM_REVSH = 279, 297 ARM_RFEDA = 280, 298 ARM_RFEDA_UPD = 281, 299 ARM_RFEDB = 282, 300 ARM_RFEDB_UPD = 283, 301 ARM_RFEIA = 284, 302 ARM_RFEIA_UPD = 285, 303 ARM_RFEIB = 286, 304 ARM_RFEIB_UPD = 287, 305 ARM_RORi = 288, 306 ARM_RORr = 289, 307 ARM_RRX = 290, 308 ARM_RRXi = 291, 309 ARM_RSBSri = 292, 310 ARM_RSBSrsi = 293, 311 ARM_RSBSrsr = 294, 312 ARM_RSBri = 295, 313 ARM_RSBrr = 296, 314 ARM_RSBrsi = 297, 315 ARM_RSBrsr = 298, 316 ARM_RSCri = 299, 317 ARM_RSCrr = 300, 318 ARM_RSCrsi = 301, 319 ARM_RSCrsr = 302, 320 ARM_SADD16 = 303, 321 ARM_SADD8 = 304, 322 ARM_SASX = 305, 323 ARM_SBCri = 306, 324 ARM_SBCrr = 307, 325 ARM_SBCrsi = 308, 326 ARM_SBCrsr = 309, 327 ARM_SBFX = 310, 328 ARM_SDIV = 311, 329 ARM_SEL = 312, 330 ARM_SETEND = 313, 331 ARM_SHA1C = 314, 332 ARM_SHA1H = 315, 333 ARM_SHA1M = 316, 334 ARM_SHA1P = 317, 335 ARM_SHA1SU0 = 318, 336 ARM_SHA1SU1 = 319, 337 ARM_SHA256H = 320, 338 ARM_SHA256H2 = 321, 339 ARM_SHA256SU0 = 322, 340 ARM_SHA256SU1 = 323, 341 ARM_SHADD16 = 324, 342 ARM_SHADD8 = 325, 343 ARM_SHASX = 326, 344 ARM_SHSAX = 327, 345 ARM_SHSUB16 = 328, 346 ARM_SHSUB8 = 329, 347 ARM_SMC = 330, 348 ARM_SMLABB = 331, 349 ARM_SMLABT = 332, 350 ARM_SMLAD = 333, 351 ARM_SMLADX = 334, 352 ARM_SMLAL = 335, 353 ARM_SMLALBB = 336, 354 ARM_SMLALBT = 337, 355 ARM_SMLALD = 338, 356 ARM_SMLALDX = 339, 357 ARM_SMLALTB = 340, 358 ARM_SMLALTT = 341, 359 ARM_SMLALv5 = 342, 360 ARM_SMLATB = 343, 361 ARM_SMLATT = 344, 362 ARM_SMLAWB = 345, 363 ARM_SMLAWT = 346, 364 ARM_SMLSD = 347, 365 ARM_SMLSDX = 348, 366 ARM_SMLSLD = 349, 367 ARM_SMLSLDX = 350, 368 ARM_SMMLA = 351, 369 ARM_SMMLAR = 352, 370 ARM_SMMLS = 353, 371 ARM_SMMLSR = 354, 372 ARM_SMMUL = 355, 373 ARM_SMMULR = 356, 374 ARM_SMUAD = 357, 375 ARM_SMUADX = 358, 376 ARM_SMULBB = 359, 377 ARM_SMULBT = 360, 378 ARM_SMULL = 361, 379 ARM_SMULLv5 = 362, 380 ARM_SMULTB = 363, 381 ARM_SMULTT = 364, 382 ARM_SMULWB = 365, 383 ARM_SMULWT = 366, 384 ARM_SMUSD = 367, 385 ARM_SMUSDX = 368, 386 ARM_SRSDA = 369, 387 ARM_SRSDA_UPD = 370, 388 ARM_SRSDB = 371, 389 ARM_SRSDB_UPD = 372, 390 ARM_SRSIA = 373, 391 ARM_SRSIA_UPD = 374, 392 ARM_SRSIB = 375, 393 ARM_SRSIB_UPD = 376, 394 ARM_SSAT = 377, 395 ARM_SSAT16 = 378, 396 ARM_SSAX = 379, 397 ARM_SSUB16 = 380, 398 ARM_SSUB8 = 381, 399 ARM_STC2L_OFFSET = 382, 400 ARM_STC2L_OPTION = 383, 401 ARM_STC2L_POST = 384, 402 ARM_STC2L_PRE = 385, 403 ARM_STC2_OFFSET = 386, 404 ARM_STC2_OPTION = 387, 405 ARM_STC2_POST = 388, 406 ARM_STC2_PRE = 389, 407 ARM_STCL_OFFSET = 390, 408 ARM_STCL_OPTION = 391, 409 ARM_STCL_POST = 392, 410 ARM_STCL_PRE = 393, 411 ARM_STC_OFFSET = 394, 412 ARM_STC_OPTION = 395, 413 ARM_STC_POST = 396, 414 ARM_STC_PRE = 397, 415 ARM_STL = 398, 416 ARM_STLB = 399, 417 ARM_STLEX = 400, 418 ARM_STLEXB = 401, 419 ARM_STLEXD = 402, 420 ARM_STLEXH = 403, 421 ARM_STLH = 404, 422 ARM_STMDA = 405, 423 ARM_STMDA_UPD = 406, 424 ARM_STMDB = 407, 425 ARM_STMDB_UPD = 408, 426 ARM_STMIA = 409, 427 ARM_STMIA_UPD = 410, 428 ARM_STMIB = 411, 429 ARM_STMIB_UPD = 412, 430 ARM_STRBT_POST = 413, 431 ARM_STRBT_POST_IMM = 414, 432 ARM_STRBT_POST_REG = 415, 433 ARM_STRB_POST_IMM = 416, 434 ARM_STRB_POST_REG = 417, 435 ARM_STRB_PRE_IMM = 418, 436 ARM_STRB_PRE_REG = 419, 437 ARM_STRBi12 = 420, 438 ARM_STRBi_preidx = 421, 439 ARM_STRBr_preidx = 422, 440 ARM_STRBrs = 423, 441 ARM_STRD = 424, 442 ARM_STRD_POST = 425, 443 ARM_STRD_PRE = 426, 444 ARM_STREX = 427, 445 ARM_STREXB = 428, 446 ARM_STREXD = 429, 447 ARM_STREXH = 430, 448 ARM_STRH = 431, 449 ARM_STRHTi = 432, 450 ARM_STRHTr = 433, 451 ARM_STRH_POST = 434, 452 ARM_STRH_PRE = 435, 453 ARM_STRH_preidx = 436, 454 ARM_STRT_POST = 437, 455 ARM_STRT_POST_IMM = 438, 456 ARM_STRT_POST_REG = 439, 457 ARM_STR_POST_IMM = 440, 458 ARM_STR_POST_REG = 441, 459 ARM_STR_PRE_IMM = 442, 460 ARM_STR_PRE_REG = 443, 461 ARM_STRi12 = 444, 462 ARM_STRi_preidx = 445, 463 ARM_STRr_preidx = 446, 464 ARM_STRrs = 447, 465 ARM_SUBS_PC_LR = 448, 466 ARM_SUBSri = 449, 467 ARM_SUBSrr = 450, 468 ARM_SUBSrsi = 451, 469 ARM_SUBSrsr = 452, 470 ARM_SUBri = 453, 471 ARM_SUBrr = 454, 472 ARM_SUBrsi = 455, 473 ARM_SUBrsr = 456, 474 ARM_SVC = 457, 475 ARM_SWP = 458, 476 ARM_SWPB = 459, 477 ARM_SXTAB = 460, 478 ARM_SXTAB16 = 461, 479 ARM_SXTAH = 462, 480 ARM_SXTB = 463, 481 ARM_SXTB16 = 464, 482 ARM_SXTH = 465, 483 ARM_TAILJMPd = 466, 484 ARM_TAILJMPr = 467, 485 ARM_TCRETURNdi = 468, 486 ARM_TCRETURNri = 469, 487 ARM_TEQri = 470, 488 ARM_TEQrr = 471, 489 ARM_TEQrsi = 472, 490 ARM_TEQrsr = 473, 491 ARM_TPsoft = 474, 492 ARM_TRAP = 475, 493 ARM_TRAPNaCl = 476, 494 ARM_TSTri = 477, 495 ARM_TSTrr = 478, 496 ARM_TSTrsi = 479, 497 ARM_TSTrsr = 480, 498 ARM_UADD16 = 481, 499 ARM_UADD8 = 482, 500 ARM_UASX = 483, 501 ARM_UBFX = 484, 502 ARM_UDF = 485, 503 ARM_UDIV = 486, 504 ARM_UHADD16 = 487, 505 ARM_UHADD8 = 488, 506 ARM_UHASX = 489, 507 ARM_UHSAX = 490, 508 ARM_UHSUB16 = 491, 509 ARM_UHSUB8 = 492, 510 ARM_UMAAL = 493, 511 ARM_UMLAL = 494, 512 ARM_UMLALv5 = 495, 513 ARM_UMULL = 496, 514 ARM_UMULLv5 = 497, 515 ARM_UQADD16 = 498, 516 ARM_UQADD8 = 499, 517 ARM_UQASX = 500, 518 ARM_UQSAX = 501, 519 ARM_UQSUB16 = 502, 520 ARM_UQSUB8 = 503, 521 ARM_USAD8 = 504, 522 ARM_USADA8 = 505, 523 ARM_USAT = 506, 524 ARM_USAT16 = 507, 525 ARM_USAX = 508, 526 ARM_USUB16 = 509, 527 ARM_USUB8 = 510, 528 ARM_UXTAB = 511, 529 ARM_UXTAB16 = 512, 530 ARM_UXTAH = 513, 531 ARM_UXTB = 514, 532 ARM_UXTB16 = 515, 533 ARM_UXTH = 516, 534 ARM_VABALsv2i64 = 517, 535 ARM_VABALsv4i32 = 518, 536 ARM_VABALsv8i16 = 519, 537 ARM_VABALuv2i64 = 520, 538 ARM_VABALuv4i32 = 521, 539 ARM_VABALuv8i16 = 522, 540 ARM_VABAsv16i8 = 523, 541 ARM_VABAsv2i32 = 524, 542 ARM_VABAsv4i16 = 525, 543 ARM_VABAsv4i32 = 526, 544 ARM_VABAsv8i16 = 527, 545 ARM_VABAsv8i8 = 528, 546 ARM_VABAuv16i8 = 529, 547 ARM_VABAuv2i32 = 530, 548 ARM_VABAuv4i16 = 531, 549 ARM_VABAuv4i32 = 532, 550 ARM_VABAuv8i16 = 533, 551 ARM_VABAuv8i8 = 534, 552 ARM_VABDLsv2i64 = 535, 553 ARM_VABDLsv4i32 = 536, 554 ARM_VABDLsv8i16 = 537, 555 ARM_VABDLuv2i64 = 538, 556 ARM_VABDLuv4i32 = 539, 557 ARM_VABDLuv8i16 = 540, 558 ARM_VABDfd = 541, 559 ARM_VABDfq = 542, 560 ARM_VABDsv16i8 = 543, 561 ARM_VABDsv2i32 = 544, 562 ARM_VABDsv4i16 = 545, 563 ARM_VABDsv4i32 = 546, 564 ARM_VABDsv8i16 = 547, 565 ARM_VABDsv8i8 = 548, 566 ARM_VABDuv16i8 = 549, 567 ARM_VABDuv2i32 = 550, 568 ARM_VABDuv4i16 = 551, 569 ARM_VABDuv4i32 = 552, 570 ARM_VABDuv8i16 = 553, 571 ARM_VABDuv8i8 = 554, 572 ARM_VABSD = 555, 573 ARM_VABSS = 556, 574 ARM_VABSfd = 557, 575 ARM_VABSfq = 558, 576 ARM_VABSv16i8 = 559, 577 ARM_VABSv2i32 = 560, 578 ARM_VABSv4i16 = 561, 579 ARM_VABSv4i32 = 562, 580 ARM_VABSv8i16 = 563, 581 ARM_VABSv8i8 = 564, 582 ARM_VACGEd = 565, 583 ARM_VACGEq = 566, 584 ARM_VACGTd = 567, 585 ARM_VACGTq = 568, 586 ARM_VADDD = 569, 587 ARM_VADDHNv2i32 = 570, 588 ARM_VADDHNv4i16 = 571, 589 ARM_VADDHNv8i8 = 572, 590 ARM_VADDLsv2i64 = 573, 591 ARM_VADDLsv4i32 = 574, 592 ARM_VADDLsv8i16 = 575, 593 ARM_VADDLuv2i64 = 576, 594 ARM_VADDLuv4i32 = 577, 595 ARM_VADDLuv8i16 = 578, 596 ARM_VADDS = 579, 597 ARM_VADDWsv2i64 = 580, 598 ARM_VADDWsv4i32 = 581, 599 ARM_VADDWsv8i16 = 582, 600 ARM_VADDWuv2i64 = 583, 601 ARM_VADDWuv4i32 = 584, 602 ARM_VADDWuv8i16 = 585, 603 ARM_VADDfd = 586, 604 ARM_VADDfq = 587, 605 ARM_VADDv16i8 = 588, 606 ARM_VADDv1i64 = 589, 607 ARM_VADDv2i32 = 590, 608 ARM_VADDv2i64 = 591, 609 ARM_VADDv4i16 = 592, 610 ARM_VADDv4i32 = 593, 611 ARM_VADDv8i16 = 594, 612 ARM_VADDv8i8 = 595, 613 ARM_VANDd = 596, 614 ARM_VANDq = 597, 615 ARM_VBICd = 598, 616 ARM_VBICiv2i32 = 599, 617 ARM_VBICiv4i16 = 600, 618 ARM_VBICiv4i32 = 601, 619 ARM_VBICiv8i16 = 602, 620 ARM_VBICq = 603, 621 ARM_VBIFd = 604, 622 ARM_VBIFq = 605, 623 ARM_VBITd = 606, 624 ARM_VBITq = 607, 625 ARM_VBSLd = 608, 626 ARM_VBSLq = 609, 627 ARM_VCEQfd = 610, 628 ARM_VCEQfq = 611, 629 ARM_VCEQv16i8 = 612, 630 ARM_VCEQv2i32 = 613, 631 ARM_VCEQv4i16 = 614, 632 ARM_VCEQv4i32 = 615, 633 ARM_VCEQv8i16 = 616, 634 ARM_VCEQv8i8 = 617, 635 ARM_VCEQzv16i8 = 618, 636 ARM_VCEQzv2f32 = 619, 637 ARM_VCEQzv2i32 = 620, 638 ARM_VCEQzv4f32 = 621, 639 ARM_VCEQzv4i16 = 622, 640 ARM_VCEQzv4i32 = 623, 641 ARM_VCEQzv8i16 = 624, 642 ARM_VCEQzv8i8 = 625, 643 ARM_VCGEfd = 626, 644 ARM_VCGEfq = 627, 645 ARM_VCGEsv16i8 = 628, 646 ARM_VCGEsv2i32 = 629, 647 ARM_VCGEsv4i16 = 630, 648 ARM_VCGEsv4i32 = 631, 649 ARM_VCGEsv8i16 = 632, 650 ARM_VCGEsv8i8 = 633, 651 ARM_VCGEuv16i8 = 634, 652 ARM_VCGEuv2i32 = 635, 653 ARM_VCGEuv4i16 = 636, 654 ARM_VCGEuv4i32 = 637, 655 ARM_VCGEuv8i16 = 638, 656 ARM_VCGEuv8i8 = 639, 657 ARM_VCGEzv16i8 = 640, 658 ARM_VCGEzv2f32 = 641, 659 ARM_VCGEzv2i32 = 642, 660 ARM_VCGEzv4f32 = 643, 661 ARM_VCGEzv4i16 = 644, 662 ARM_VCGEzv4i32 = 645, 663 ARM_VCGEzv8i16 = 646, 664 ARM_VCGEzv8i8 = 647, 665 ARM_VCGTfd = 648, 666 ARM_VCGTfq = 649, 667 ARM_VCGTsv16i8 = 650, 668 ARM_VCGTsv2i32 = 651, 669 ARM_VCGTsv4i16 = 652, 670 ARM_VCGTsv4i32 = 653, 671 ARM_VCGTsv8i16 = 654, 672 ARM_VCGTsv8i8 = 655, 673 ARM_VCGTuv16i8 = 656, 674 ARM_VCGTuv2i32 = 657, 675 ARM_VCGTuv4i16 = 658, 676 ARM_VCGTuv4i32 = 659, 677 ARM_VCGTuv8i16 = 660, 678 ARM_VCGTuv8i8 = 661, 679 ARM_VCGTzv16i8 = 662, 680 ARM_VCGTzv2f32 = 663, 681 ARM_VCGTzv2i32 = 664, 682 ARM_VCGTzv4f32 = 665, 683 ARM_VCGTzv4i16 = 666, 684 ARM_VCGTzv4i32 = 667, 685 ARM_VCGTzv8i16 = 668, 686 ARM_VCGTzv8i8 = 669, 687 ARM_VCLEzv16i8 = 670, 688 ARM_VCLEzv2f32 = 671, 689 ARM_VCLEzv2i32 = 672, 690 ARM_VCLEzv4f32 = 673, 691 ARM_VCLEzv4i16 = 674, 692 ARM_VCLEzv4i32 = 675, 693 ARM_VCLEzv8i16 = 676, 694 ARM_VCLEzv8i8 = 677, 695 ARM_VCLSv16i8 = 678, 696 ARM_VCLSv2i32 = 679, 697 ARM_VCLSv4i16 = 680, 698 ARM_VCLSv4i32 = 681, 699 ARM_VCLSv8i16 = 682, 700 ARM_VCLSv8i8 = 683, 701 ARM_VCLTzv16i8 = 684, 702 ARM_VCLTzv2f32 = 685, 703 ARM_VCLTzv2i32 = 686, 704 ARM_VCLTzv4f32 = 687, 705 ARM_VCLTzv4i16 = 688, 706 ARM_VCLTzv4i32 = 689, 707 ARM_VCLTzv8i16 = 690, 708 ARM_VCLTzv8i8 = 691, 709 ARM_VCLZv16i8 = 692, 710 ARM_VCLZv2i32 = 693, 711 ARM_VCLZv4i16 = 694, 712 ARM_VCLZv4i32 = 695, 713 ARM_VCLZv8i16 = 696, 714 ARM_VCLZv8i8 = 697, 715 ARM_VCMPD = 698, 716 ARM_VCMPED = 699, 717 ARM_VCMPES = 700, 718 ARM_VCMPEZD = 701, 719 ARM_VCMPEZS = 702, 720 ARM_VCMPS = 703, 721 ARM_VCMPZD = 704, 722 ARM_VCMPZS = 705, 723 ARM_VCNTd = 706, 724 ARM_VCNTq = 707, 725 ARM_VCVTANSD = 708, 726 ARM_VCVTANSQ = 709, 727 ARM_VCVTANUD = 710, 728 ARM_VCVTANUQ = 711, 729 ARM_VCVTASD = 712, 730 ARM_VCVTASS = 713, 731 ARM_VCVTAUD = 714, 732 ARM_VCVTAUS = 715, 733 ARM_VCVTBDH = 716, 734 ARM_VCVTBHD = 717, 735 ARM_VCVTBHS = 718, 736 ARM_VCVTBSH = 719, 737 ARM_VCVTDS = 720, 738 ARM_VCVTMNSD = 721, 739 ARM_VCVTMNSQ = 722, 740 ARM_VCVTMNUD = 723, 741 ARM_VCVTMNUQ = 724, 742 ARM_VCVTMSD = 725, 743 ARM_VCVTMSS = 726, 744 ARM_VCVTMUD = 727, 745 ARM_VCVTMUS = 728, 746 ARM_VCVTNNSD = 729, 747 ARM_VCVTNNSQ = 730, 748 ARM_VCVTNNUD = 731, 749 ARM_VCVTNNUQ = 732, 750 ARM_VCVTNSD = 733, 751 ARM_VCVTNSS = 734, 752 ARM_VCVTNUD = 735, 753 ARM_VCVTNUS = 736, 754 ARM_VCVTPNSD = 737, 755 ARM_VCVTPNSQ = 738, 756 ARM_VCVTPNUD = 739, 757 ARM_VCVTPNUQ = 740, 758 ARM_VCVTPSD = 741, 759 ARM_VCVTPSS = 742, 760 ARM_VCVTPUD = 743, 761 ARM_VCVTPUS = 744, 762 ARM_VCVTSD = 745, 763 ARM_VCVTTDH = 746, 764 ARM_VCVTTHD = 747, 765 ARM_VCVTTHS = 748, 766 ARM_VCVTTSH = 749, 767 ARM_VCVTf2h = 750, 768 ARM_VCVTf2sd = 751, 769 ARM_VCVTf2sq = 752, 770 ARM_VCVTf2ud = 753, 771 ARM_VCVTf2uq = 754, 772 ARM_VCVTf2xsd = 755, 773 ARM_VCVTf2xsq = 756, 774 ARM_VCVTf2xud = 757, 775 ARM_VCVTf2xuq = 758, 776 ARM_VCVTh2f = 759, 777 ARM_VCVTs2fd = 760, 778 ARM_VCVTs2fq = 761, 779 ARM_VCVTu2fd = 762, 780 ARM_VCVTu2fq = 763, 781 ARM_VCVTxs2fd = 764, 782 ARM_VCVTxs2fq = 765, 783 ARM_VCVTxu2fd = 766, 784 ARM_VCVTxu2fq = 767, 785 ARM_VDIVD = 768, 786 ARM_VDIVS = 769, 787 ARM_VDUP16d = 770, 788 ARM_VDUP16q = 771, 789 ARM_VDUP32d = 772, 790 ARM_VDUP32q = 773, 791 ARM_VDUP8d = 774, 792 ARM_VDUP8q = 775, 793 ARM_VDUPLN16d = 776, 794 ARM_VDUPLN16q = 777, 795 ARM_VDUPLN32d = 778, 796 ARM_VDUPLN32q = 779, 797 ARM_VDUPLN8d = 780, 798 ARM_VDUPLN8q = 781, 799 ARM_VEORd = 782, 800 ARM_VEORq = 783, 801 ARM_VEXTd16 = 784, 802 ARM_VEXTd32 = 785, 803 ARM_VEXTd8 = 786, 804 ARM_VEXTq16 = 787, 805 ARM_VEXTq32 = 788, 806 ARM_VEXTq64 = 789, 807 ARM_VEXTq8 = 790, 808 ARM_VFMAD = 791, 809 ARM_VFMAS = 792, 810 ARM_VFMAfd = 793, 811 ARM_VFMAfq = 794, 812 ARM_VFMSD = 795, 813 ARM_VFMSS = 796, 814 ARM_VFMSfd = 797, 815 ARM_VFMSfq = 798, 816 ARM_VFNMAD = 799, 817 ARM_VFNMAS = 800, 818 ARM_VFNMSD = 801, 819 ARM_VFNMSS = 802, 820 ARM_VGETLNi32 = 803, 821 ARM_VGETLNs16 = 804, 822 ARM_VGETLNs8 = 805, 823 ARM_VGETLNu16 = 806, 824 ARM_VGETLNu8 = 807, 825 ARM_VHADDsv16i8 = 808, 826 ARM_VHADDsv2i32 = 809, 827 ARM_VHADDsv4i16 = 810, 828 ARM_VHADDsv4i32 = 811, 829 ARM_VHADDsv8i16 = 812, 830 ARM_VHADDsv8i8 = 813, 831 ARM_VHADDuv16i8 = 814, 832 ARM_VHADDuv2i32 = 815, 833 ARM_VHADDuv4i16 = 816, 834 ARM_VHADDuv4i32 = 817, 835 ARM_VHADDuv8i16 = 818, 836 ARM_VHADDuv8i8 = 819, 837 ARM_VHSUBsv16i8 = 820, 838 ARM_VHSUBsv2i32 = 821, 839 ARM_VHSUBsv4i16 = 822, 840 ARM_VHSUBsv4i32 = 823, 841 ARM_VHSUBsv8i16 = 824, 842 ARM_VHSUBsv8i8 = 825, 843 ARM_VHSUBuv16i8 = 826, 844 ARM_VHSUBuv2i32 = 827, 845 ARM_VHSUBuv4i16 = 828, 846 ARM_VHSUBuv4i32 = 829, 847 ARM_VHSUBuv8i16 = 830, 848 ARM_VHSUBuv8i8 = 831, 849 ARM_VLD1DUPd16 = 832, 850 ARM_VLD1DUPd16wb_fixed = 833, 851 ARM_VLD1DUPd16wb_register = 834, 852 ARM_VLD1DUPd32 = 835, 853 ARM_VLD1DUPd32wb_fixed = 836, 854 ARM_VLD1DUPd32wb_register = 837, 855 ARM_VLD1DUPd8 = 838, 856 ARM_VLD1DUPd8wb_fixed = 839, 857 ARM_VLD1DUPd8wb_register = 840, 858 ARM_VLD1DUPq16 = 841, 859 ARM_VLD1DUPq16wb_fixed = 842, 860 ARM_VLD1DUPq16wb_register = 843, 861 ARM_VLD1DUPq32 = 844, 862 ARM_VLD1DUPq32wb_fixed = 845, 863 ARM_VLD1DUPq32wb_register = 846, 864 ARM_VLD1DUPq8 = 847, 865 ARM_VLD1DUPq8wb_fixed = 848, 866 ARM_VLD1DUPq8wb_register = 849, 867 ARM_VLD1LNd16 = 850, 868 ARM_VLD1LNd16_UPD = 851, 869 ARM_VLD1LNd32 = 852, 870 ARM_VLD1LNd32_UPD = 853, 871 ARM_VLD1LNd8 = 854, 872 ARM_VLD1LNd8_UPD = 855, 873 ARM_VLD1LNdAsm_16 = 856, 874 ARM_VLD1LNdAsm_32 = 857, 875 ARM_VLD1LNdAsm_8 = 858, 876 ARM_VLD1LNdWB_fixed_Asm_16 = 859, 877 ARM_VLD1LNdWB_fixed_Asm_32 = 860, 878 ARM_VLD1LNdWB_fixed_Asm_8 = 861, 879 ARM_VLD1LNdWB_register_Asm_16 = 862, 880 ARM_VLD1LNdWB_register_Asm_32 = 863, 881 ARM_VLD1LNdWB_register_Asm_8 = 864, 882 ARM_VLD1LNq16Pseudo = 865, 883 ARM_VLD1LNq16Pseudo_UPD = 866, 884 ARM_VLD1LNq32Pseudo = 867, 885 ARM_VLD1LNq32Pseudo_UPD = 868, 886 ARM_VLD1LNq8Pseudo = 869, 887 ARM_VLD1LNq8Pseudo_UPD = 870, 888 ARM_VLD1d16 = 871, 889 ARM_VLD1d16Q = 872, 890 ARM_VLD1d16Qwb_fixed = 873, 891 ARM_VLD1d16Qwb_register = 874, 892 ARM_VLD1d16T = 875, 893 ARM_VLD1d16Twb_fixed = 876, 894 ARM_VLD1d16Twb_register = 877, 895 ARM_VLD1d16wb_fixed = 878, 896 ARM_VLD1d16wb_register = 879, 897 ARM_VLD1d32 = 880, 898 ARM_VLD1d32Q = 881, 899 ARM_VLD1d32Qwb_fixed = 882, 900 ARM_VLD1d32Qwb_register = 883, 901 ARM_VLD1d32T = 884, 902 ARM_VLD1d32Twb_fixed = 885, 903 ARM_VLD1d32Twb_register = 886, 904 ARM_VLD1d32wb_fixed = 887, 905 ARM_VLD1d32wb_register = 888, 906 ARM_VLD1d64 = 889, 907 ARM_VLD1d64Q = 890, 908 ARM_VLD1d64QPseudo = 891, 909 ARM_VLD1d64QPseudoWB_fixed = 892, 910 ARM_VLD1d64QPseudoWB_register = 893, 911 ARM_VLD1d64Qwb_fixed = 894, 912 ARM_VLD1d64Qwb_register = 895, 913 ARM_VLD1d64T = 896, 914 ARM_VLD1d64TPseudo = 897, 915 ARM_VLD1d64TPseudoWB_fixed = 898, 916 ARM_VLD1d64TPseudoWB_register = 899, 917 ARM_VLD1d64Twb_fixed = 900, 918 ARM_VLD1d64Twb_register = 901, 919 ARM_VLD1d64wb_fixed = 902, 920 ARM_VLD1d64wb_register = 903, 921 ARM_VLD1d8 = 904, 922 ARM_VLD1d8Q = 905, 923 ARM_VLD1d8Qwb_fixed = 906, 924 ARM_VLD1d8Qwb_register = 907, 925 ARM_VLD1d8T = 908, 926 ARM_VLD1d8Twb_fixed = 909, 927 ARM_VLD1d8Twb_register = 910, 928 ARM_VLD1d8wb_fixed = 911, 929 ARM_VLD1d8wb_register = 912, 930 ARM_VLD1q16 = 913, 931 ARM_VLD1q16wb_fixed = 914, 932 ARM_VLD1q16wb_register = 915, 933 ARM_VLD1q32 = 916, 934 ARM_VLD1q32wb_fixed = 917, 935 ARM_VLD1q32wb_register = 918, 936 ARM_VLD1q64 = 919, 937 ARM_VLD1q64wb_fixed = 920, 938 ARM_VLD1q64wb_register = 921, 939 ARM_VLD1q8 = 922, 940 ARM_VLD1q8wb_fixed = 923, 941 ARM_VLD1q8wb_register = 924, 942 ARM_VLD2DUPd16 = 925, 943 ARM_VLD2DUPd16wb_fixed = 926, 944 ARM_VLD2DUPd16wb_register = 927, 945 ARM_VLD2DUPd16x2 = 928, 946 ARM_VLD2DUPd16x2wb_fixed = 929, 947 ARM_VLD2DUPd16x2wb_register = 930, 948 ARM_VLD2DUPd32 = 931, 949 ARM_VLD2DUPd32wb_fixed = 932, 950 ARM_VLD2DUPd32wb_register = 933, 951 ARM_VLD2DUPd32x2 = 934, 952 ARM_VLD2DUPd32x2wb_fixed = 935, 953 ARM_VLD2DUPd32x2wb_register = 936, 954 ARM_VLD2DUPd8 = 937, 955 ARM_VLD2DUPd8wb_fixed = 938, 956 ARM_VLD2DUPd8wb_register = 939, 957 ARM_VLD2DUPd8x2 = 940, 958 ARM_VLD2DUPd8x2wb_fixed = 941, 959 ARM_VLD2DUPd8x2wb_register = 942, 960 ARM_VLD2LNd16 = 943, 961 ARM_VLD2LNd16Pseudo = 944, 962 ARM_VLD2LNd16Pseudo_UPD = 945, 963 ARM_VLD2LNd16_UPD = 946, 964 ARM_VLD2LNd32 = 947, 965 ARM_VLD2LNd32Pseudo = 948, 966 ARM_VLD2LNd32Pseudo_UPD = 949, 967 ARM_VLD2LNd32_UPD = 950, 968 ARM_VLD2LNd8 = 951, 969 ARM_VLD2LNd8Pseudo = 952, 970 ARM_VLD2LNd8Pseudo_UPD = 953, 971 ARM_VLD2LNd8_UPD = 954, 972 ARM_VLD2LNdAsm_16 = 955, 973 ARM_VLD2LNdAsm_32 = 956, 974 ARM_VLD2LNdAsm_8 = 957, 975 ARM_VLD2LNdWB_fixed_Asm_16 = 958, 976 ARM_VLD2LNdWB_fixed_Asm_32 = 959, 977 ARM_VLD2LNdWB_fixed_Asm_8 = 960, 978 ARM_VLD2LNdWB_register_Asm_16 = 961, 979 ARM_VLD2LNdWB_register_Asm_32 = 962, 980 ARM_VLD2LNdWB_register_Asm_8 = 963, 981 ARM_VLD2LNq16 = 964, 982 ARM_VLD2LNq16Pseudo = 965, 983 ARM_VLD2LNq16Pseudo_UPD = 966, 984 ARM_VLD2LNq16_UPD = 967, 985 ARM_VLD2LNq32 = 968, 986 ARM_VLD2LNq32Pseudo = 969, 987 ARM_VLD2LNq32Pseudo_UPD = 970, 988 ARM_VLD2LNq32_UPD = 971, 989 ARM_VLD2LNqAsm_16 = 972, 990 ARM_VLD2LNqAsm_32 = 973, 991 ARM_VLD2LNqWB_fixed_Asm_16 = 974, 992 ARM_VLD2LNqWB_fixed_Asm_32 = 975, 993 ARM_VLD2LNqWB_register_Asm_16 = 976, 994 ARM_VLD2LNqWB_register_Asm_32 = 977, 995 ARM_VLD2b16 = 978, 996 ARM_VLD2b16wb_fixed = 979, 997 ARM_VLD2b16wb_register = 980, 998 ARM_VLD2b32 = 981, 999 ARM_VLD2b32wb_fixed = 982, 1000 ARM_VLD2b32wb_register = 983, 1001 ARM_VLD2b8 = 984, 1002 ARM_VLD2b8wb_fixed = 985, 1003 ARM_VLD2b8wb_register = 986, 1004 ARM_VLD2d16 = 987, 1005 ARM_VLD2d16wb_fixed = 988, 1006 ARM_VLD2d16wb_register = 989, 1007 ARM_VLD2d32 = 990, 1008 ARM_VLD2d32wb_fixed = 991, 1009 ARM_VLD2d32wb_register = 992, 1010 ARM_VLD2d8 = 993, 1011 ARM_VLD2d8wb_fixed = 994, 1012 ARM_VLD2d8wb_register = 995, 1013 ARM_VLD2q16 = 996, 1014 ARM_VLD2q16Pseudo = 997, 1015 ARM_VLD2q16PseudoWB_fixed = 998, 1016 ARM_VLD2q16PseudoWB_register = 999, 1017 ARM_VLD2q16wb_fixed = 1000, 1018 ARM_VLD2q16wb_register = 1001, 1019 ARM_VLD2q32 = 1002, 1020 ARM_VLD2q32Pseudo = 1003, 1021 ARM_VLD2q32PseudoWB_fixed = 1004, 1022 ARM_VLD2q32PseudoWB_register = 1005, 1023 ARM_VLD2q32wb_fixed = 1006, 1024 ARM_VLD2q32wb_register = 1007, 1025 ARM_VLD2q8 = 1008, 1026 ARM_VLD2q8Pseudo = 1009, 1027 ARM_VLD2q8PseudoWB_fixed = 1010, 1028 ARM_VLD2q8PseudoWB_register = 1011, 1029 ARM_VLD2q8wb_fixed = 1012, 1030 ARM_VLD2q8wb_register = 1013, 1031 ARM_VLD3DUPd16 = 1014, 1032 ARM_VLD3DUPd16Pseudo = 1015, 1033 ARM_VLD3DUPd16Pseudo_UPD = 1016, 1034 ARM_VLD3DUPd16_UPD = 1017, 1035 ARM_VLD3DUPd32 = 1018, 1036 ARM_VLD3DUPd32Pseudo = 1019, 1037 ARM_VLD3DUPd32Pseudo_UPD = 1020, 1038 ARM_VLD3DUPd32_UPD = 1021, 1039 ARM_VLD3DUPd8 = 1022, 1040 ARM_VLD3DUPd8Pseudo = 1023, 1041 ARM_VLD3DUPd8Pseudo_UPD = 1024, 1042 ARM_VLD3DUPd8_UPD = 1025, 1043 ARM_VLD3DUPdAsm_16 = 1026, 1044 ARM_VLD3DUPdAsm_32 = 1027, 1045 ARM_VLD3DUPdAsm_8 = 1028, 1046 ARM_VLD3DUPdWB_fixed_Asm_16 = 1029, 1047 ARM_VLD3DUPdWB_fixed_Asm_32 = 1030, 1048 ARM_VLD3DUPdWB_fixed_Asm_8 = 1031, 1049 ARM_VLD3DUPdWB_register_Asm_16 = 1032, 1050 ARM_VLD3DUPdWB_register_Asm_32 = 1033, 1051 ARM_VLD3DUPdWB_register_Asm_8 = 1034, 1052 ARM_VLD3DUPq16 = 1035, 1053 ARM_VLD3DUPq16_UPD = 1036, 1054 ARM_VLD3DUPq32 = 1037, 1055 ARM_VLD3DUPq32_UPD = 1038, 1056 ARM_VLD3DUPq8 = 1039, 1057 ARM_VLD3DUPq8_UPD = 1040, 1058 ARM_VLD3DUPqAsm_16 = 1041, 1059 ARM_VLD3DUPqAsm_32 = 1042, 1060 ARM_VLD3DUPqAsm_8 = 1043, 1061 ARM_VLD3DUPqWB_fixed_Asm_16 = 1044, 1062 ARM_VLD3DUPqWB_fixed_Asm_32 = 1045, 1063 ARM_VLD3DUPqWB_fixed_Asm_8 = 1046, 1064 ARM_VLD3DUPqWB_register_Asm_16 = 1047, 1065 ARM_VLD3DUPqWB_register_Asm_32 = 1048, 1066 ARM_VLD3DUPqWB_register_Asm_8 = 1049, 1067 ARM_VLD3LNd16 = 1050, 1068 ARM_VLD3LNd16Pseudo = 1051, 1069 ARM_VLD3LNd16Pseudo_UPD = 1052, 1070 ARM_VLD3LNd16_UPD = 1053, 1071 ARM_VLD3LNd32 = 1054, 1072 ARM_VLD3LNd32Pseudo = 1055, 1073 ARM_VLD3LNd32Pseudo_UPD = 1056, 1074 ARM_VLD3LNd32_UPD = 1057, 1075 ARM_VLD3LNd8 = 1058, 1076 ARM_VLD3LNd8Pseudo = 1059, 1077 ARM_VLD3LNd8Pseudo_UPD = 1060, 1078 ARM_VLD3LNd8_UPD = 1061, 1079 ARM_VLD3LNdAsm_16 = 1062, 1080 ARM_VLD3LNdAsm_32 = 1063, 1081 ARM_VLD3LNdAsm_8 = 1064, 1082 ARM_VLD3LNdWB_fixed_Asm_16 = 1065, 1083 ARM_VLD3LNdWB_fixed_Asm_32 = 1066, 1084 ARM_VLD3LNdWB_fixed_Asm_8 = 1067, 1085 ARM_VLD3LNdWB_register_Asm_16 = 1068, 1086 ARM_VLD3LNdWB_register_Asm_32 = 1069, 1087 ARM_VLD3LNdWB_register_Asm_8 = 1070, 1088 ARM_VLD3LNq16 = 1071, 1089 ARM_VLD3LNq16Pseudo = 1072, 1090 ARM_VLD3LNq16Pseudo_UPD = 1073, 1091 ARM_VLD3LNq16_UPD = 1074, 1092 ARM_VLD3LNq32 = 1075, 1093 ARM_VLD3LNq32Pseudo = 1076, 1094 ARM_VLD3LNq32Pseudo_UPD = 1077, 1095 ARM_VLD3LNq32_UPD = 1078, 1096 ARM_VLD3LNqAsm_16 = 1079, 1097 ARM_VLD3LNqAsm_32 = 1080, 1098 ARM_VLD3LNqWB_fixed_Asm_16 = 1081, 1099 ARM_VLD3LNqWB_fixed_Asm_32 = 1082, 1100 ARM_VLD3LNqWB_register_Asm_16 = 1083, 1101 ARM_VLD3LNqWB_register_Asm_32 = 1084, 1102 ARM_VLD3d16 = 1085, 1103 ARM_VLD3d16Pseudo = 1086, 1104 ARM_VLD3d16Pseudo_UPD = 1087, 1105 ARM_VLD3d16_UPD = 1088, 1106 ARM_VLD3d32 = 1089, 1107 ARM_VLD3d32Pseudo = 1090, 1108 ARM_VLD3d32Pseudo_UPD = 1091, 1109 ARM_VLD3d32_UPD = 1092, 1110 ARM_VLD3d8 = 1093, 1111 ARM_VLD3d8Pseudo = 1094, 1112 ARM_VLD3d8Pseudo_UPD = 1095, 1113 ARM_VLD3d8_UPD = 1096, 1114 ARM_VLD3dAsm_16 = 1097, 1115 ARM_VLD3dAsm_32 = 1098, 1116 ARM_VLD3dAsm_8 = 1099, 1117 ARM_VLD3dWB_fixed_Asm_16 = 1100, 1118 ARM_VLD3dWB_fixed_Asm_32 = 1101, 1119 ARM_VLD3dWB_fixed_Asm_8 = 1102, 1120 ARM_VLD3dWB_register_Asm_16 = 1103, 1121 ARM_VLD3dWB_register_Asm_32 = 1104, 1122 ARM_VLD3dWB_register_Asm_8 = 1105, 1123 ARM_VLD3q16 = 1106, 1124 ARM_VLD3q16Pseudo_UPD = 1107, 1125 ARM_VLD3q16_UPD = 1108, 1126 ARM_VLD3q16oddPseudo = 1109, 1127 ARM_VLD3q16oddPseudo_UPD = 1110, 1128 ARM_VLD3q32 = 1111, 1129 ARM_VLD3q32Pseudo_UPD = 1112, 1130 ARM_VLD3q32_UPD = 1113, 1131 ARM_VLD3q32oddPseudo = 1114, 1132 ARM_VLD3q32oddPseudo_UPD = 1115, 1133 ARM_VLD3q8 = 1116, 1134 ARM_VLD3q8Pseudo_UPD = 1117, 1135 ARM_VLD3q8_UPD = 1118, 1136 ARM_VLD3q8oddPseudo = 1119, 1137 ARM_VLD3q8oddPseudo_UPD = 1120, 1138 ARM_VLD3qAsm_16 = 1121, 1139 ARM_VLD3qAsm_32 = 1122, 1140 ARM_VLD3qAsm_8 = 1123, 1141 ARM_VLD3qWB_fixed_Asm_16 = 1124, 1142 ARM_VLD3qWB_fixed_Asm_32 = 1125, 1143 ARM_VLD3qWB_fixed_Asm_8 = 1126, 1144 ARM_VLD3qWB_register_Asm_16 = 1127, 1145 ARM_VLD3qWB_register_Asm_32 = 1128, 1146 ARM_VLD3qWB_register_Asm_8 = 1129, 1147 ARM_VLD4DUPd16 = 1130, 1148 ARM_VLD4DUPd16Pseudo = 1131, 1149 ARM_VLD4DUPd16Pseudo_UPD = 1132, 1150 ARM_VLD4DUPd16_UPD = 1133, 1151 ARM_VLD4DUPd32 = 1134, 1152 ARM_VLD4DUPd32Pseudo = 1135, 1153 ARM_VLD4DUPd32Pseudo_UPD = 1136, 1154 ARM_VLD4DUPd32_UPD = 1137, 1155 ARM_VLD4DUPd8 = 1138, 1156 ARM_VLD4DUPd8Pseudo = 1139, 1157 ARM_VLD4DUPd8Pseudo_UPD = 1140, 1158 ARM_VLD4DUPd8_UPD = 1141, 1159 ARM_VLD4DUPdAsm_16 = 1142, 1160 ARM_VLD4DUPdAsm_32 = 1143, 1161 ARM_VLD4DUPdAsm_8 = 1144, 1162 ARM_VLD4DUPdWB_fixed_Asm_16 = 1145, 1163 ARM_VLD4DUPdWB_fixed_Asm_32 = 1146, 1164 ARM_VLD4DUPdWB_fixed_Asm_8 = 1147, 1165 ARM_VLD4DUPdWB_register_Asm_16 = 1148, 1166 ARM_VLD4DUPdWB_register_Asm_32 = 1149, 1167 ARM_VLD4DUPdWB_register_Asm_8 = 1150, 1168 ARM_VLD4DUPq16 = 1151, 1169 ARM_VLD4DUPq16_UPD = 1152, 1170 ARM_VLD4DUPq32 = 1153, 1171 ARM_VLD4DUPq32_UPD = 1154, 1172 ARM_VLD4DUPq8 = 1155, 1173 ARM_VLD4DUPq8_UPD = 1156, 1174 ARM_VLD4DUPqAsm_16 = 1157, 1175 ARM_VLD4DUPqAsm_32 = 1158, 1176 ARM_VLD4DUPqAsm_8 = 1159, 1177 ARM_VLD4DUPqWB_fixed_Asm_16 = 1160, 1178 ARM_VLD4DUPqWB_fixed_Asm_32 = 1161, 1179 ARM_VLD4DUPqWB_fixed_Asm_8 = 1162, 1180 ARM_VLD4DUPqWB_register_Asm_16 = 1163, 1181 ARM_VLD4DUPqWB_register_Asm_32 = 1164, 1182 ARM_VLD4DUPqWB_register_Asm_8 = 1165, 1183 ARM_VLD4LNd16 = 1166, 1184 ARM_VLD4LNd16Pseudo = 1167, 1185 ARM_VLD4LNd16Pseudo_UPD = 1168, 1186 ARM_VLD4LNd16_UPD = 1169, 1187 ARM_VLD4LNd32 = 1170, 1188 ARM_VLD4LNd32Pseudo = 1171, 1189 ARM_VLD4LNd32Pseudo_UPD = 1172, 1190 ARM_VLD4LNd32_UPD = 1173, 1191 ARM_VLD4LNd8 = 1174, 1192 ARM_VLD4LNd8Pseudo = 1175, 1193 ARM_VLD4LNd8Pseudo_UPD = 1176, 1194 ARM_VLD4LNd8_UPD = 1177, 1195 ARM_VLD4LNdAsm_16 = 1178, 1196 ARM_VLD4LNdAsm_32 = 1179, 1197 ARM_VLD4LNdAsm_8 = 1180, 1198 ARM_VLD4LNdWB_fixed_Asm_16 = 1181, 1199 ARM_VLD4LNdWB_fixed_Asm_32 = 1182, 1200 ARM_VLD4LNdWB_fixed_Asm_8 = 1183, 1201 ARM_VLD4LNdWB_register_Asm_16 = 1184, 1202 ARM_VLD4LNdWB_register_Asm_32 = 1185, 1203 ARM_VLD4LNdWB_register_Asm_8 = 1186, 1204 ARM_VLD4LNq16 = 1187, 1205 ARM_VLD4LNq16Pseudo = 1188, 1206 ARM_VLD4LNq16Pseudo_UPD = 1189, 1207 ARM_VLD4LNq16_UPD = 1190, 1208 ARM_VLD4LNq32 = 1191, 1209 ARM_VLD4LNq32Pseudo = 1192, 1210 ARM_VLD4LNq32Pseudo_UPD = 1193, 1211 ARM_VLD4LNq32_UPD = 1194, 1212 ARM_VLD4LNqAsm_16 = 1195, 1213 ARM_VLD4LNqAsm_32 = 1196, 1214 ARM_VLD4LNqWB_fixed_Asm_16 = 1197, 1215 ARM_VLD4LNqWB_fixed_Asm_32 = 1198, 1216 ARM_VLD4LNqWB_register_Asm_16 = 1199, 1217 ARM_VLD4LNqWB_register_Asm_32 = 1200, 1218 ARM_VLD4d16 = 1201, 1219 ARM_VLD4d16Pseudo = 1202, 1220 ARM_VLD4d16Pseudo_UPD = 1203, 1221 ARM_VLD4d16_UPD = 1204, 1222 ARM_VLD4d32 = 1205, 1223 ARM_VLD4d32Pseudo = 1206, 1224 ARM_VLD4d32Pseudo_UPD = 1207, 1225 ARM_VLD4d32_UPD = 1208, 1226 ARM_VLD4d8 = 1209, 1227 ARM_VLD4d8Pseudo = 1210, 1228 ARM_VLD4d8Pseudo_UPD = 1211, 1229 ARM_VLD4d8_UPD = 1212, 1230 ARM_VLD4dAsm_16 = 1213, 1231 ARM_VLD4dAsm_32 = 1214, 1232 ARM_VLD4dAsm_8 = 1215, 1233 ARM_VLD4dWB_fixed_Asm_16 = 1216, 1234 ARM_VLD4dWB_fixed_Asm_32 = 1217, 1235 ARM_VLD4dWB_fixed_Asm_8 = 1218, 1236 ARM_VLD4dWB_register_Asm_16 = 1219, 1237 ARM_VLD4dWB_register_Asm_32 = 1220, 1238 ARM_VLD4dWB_register_Asm_8 = 1221, 1239 ARM_VLD4q16 = 1222, 1240 ARM_VLD4q16Pseudo_UPD = 1223, 1241 ARM_VLD4q16_UPD = 1224, 1242 ARM_VLD4q16oddPseudo = 1225, 1243 ARM_VLD4q16oddPseudo_UPD = 1226, 1244 ARM_VLD4q32 = 1227, 1245 ARM_VLD4q32Pseudo_UPD = 1228, 1246 ARM_VLD4q32_UPD = 1229, 1247 ARM_VLD4q32oddPseudo = 1230, 1248 ARM_VLD4q32oddPseudo_UPD = 1231, 1249 ARM_VLD4q8 = 1232, 1250 ARM_VLD4q8Pseudo_UPD = 1233, 1251 ARM_VLD4q8_UPD = 1234, 1252 ARM_VLD4q8oddPseudo = 1235, 1253 ARM_VLD4q8oddPseudo_UPD = 1236, 1254 ARM_VLD4qAsm_16 = 1237, 1255 ARM_VLD4qAsm_32 = 1238, 1256 ARM_VLD4qAsm_8 = 1239, 1257 ARM_VLD4qWB_fixed_Asm_16 = 1240, 1258 ARM_VLD4qWB_fixed_Asm_32 = 1241, 1259 ARM_VLD4qWB_fixed_Asm_8 = 1242, 1260 ARM_VLD4qWB_register_Asm_16 = 1243, 1261 ARM_VLD4qWB_register_Asm_32 = 1244, 1262 ARM_VLD4qWB_register_Asm_8 = 1245, 1263 ARM_VLDMDDB_UPD = 1246, 1264 ARM_VLDMDIA = 1247, 1265 ARM_VLDMDIA_UPD = 1248, 1266 ARM_VLDMQIA = 1249, 1267 ARM_VLDMSDB_UPD = 1250, 1268 ARM_VLDMSIA = 1251, 1269 ARM_VLDMSIA_UPD = 1252, 1270 ARM_VLDRD = 1253, 1271 ARM_VLDRS = 1254, 1272 ARM_VMAXNMD = 1255, 1273 ARM_VMAXNMND = 1256, 1274 ARM_VMAXNMNQ = 1257, 1275 ARM_VMAXNMS = 1258, 1276 ARM_VMAXfd = 1259, 1277 ARM_VMAXfq = 1260, 1278 ARM_VMAXsv16i8 = 1261, 1279 ARM_VMAXsv2i32 = 1262, 1280 ARM_VMAXsv4i16 = 1263, 1281 ARM_VMAXsv4i32 = 1264, 1282 ARM_VMAXsv8i16 = 1265, 1283 ARM_VMAXsv8i8 = 1266, 1284 ARM_VMAXuv16i8 = 1267, 1285 ARM_VMAXuv2i32 = 1268, 1286 ARM_VMAXuv4i16 = 1269, 1287 ARM_VMAXuv4i32 = 1270, 1288 ARM_VMAXuv8i16 = 1271, 1289 ARM_VMAXuv8i8 = 1272, 1290 ARM_VMINNMD = 1273, 1291 ARM_VMINNMND = 1274, 1292 ARM_VMINNMNQ = 1275, 1293 ARM_VMINNMS = 1276, 1294 ARM_VMINfd = 1277, 1295 ARM_VMINfq = 1278, 1296 ARM_VMINsv16i8 = 1279, 1297 ARM_VMINsv2i32 = 1280, 1298 ARM_VMINsv4i16 = 1281, 1299 ARM_VMINsv4i32 = 1282, 1300 ARM_VMINsv8i16 = 1283, 1301 ARM_VMINsv8i8 = 1284, 1302 ARM_VMINuv16i8 = 1285, 1303 ARM_VMINuv2i32 = 1286, 1304 ARM_VMINuv4i16 = 1287, 1305 ARM_VMINuv4i32 = 1288, 1306 ARM_VMINuv8i16 = 1289, 1307 ARM_VMINuv8i8 = 1290, 1308 ARM_VMLAD = 1291, 1309 ARM_VMLALslsv2i32 = 1292, 1310 ARM_VMLALslsv4i16 = 1293, 1311 ARM_VMLALsluv2i32 = 1294, 1312 ARM_VMLALsluv4i16 = 1295, 1313 ARM_VMLALsv2i64 = 1296, 1314 ARM_VMLALsv4i32 = 1297, 1315 ARM_VMLALsv8i16 = 1298, 1316 ARM_VMLALuv2i64 = 1299, 1317 ARM_VMLALuv4i32 = 1300, 1318 ARM_VMLALuv8i16 = 1301, 1319 ARM_VMLAS = 1302, 1320 ARM_VMLAfd = 1303, 1321 ARM_VMLAfq = 1304, 1322 ARM_VMLAslfd = 1305, 1323 ARM_VMLAslfq = 1306, 1324 ARM_VMLAslv2i32 = 1307, 1325 ARM_VMLAslv4i16 = 1308, 1326 ARM_VMLAslv4i32 = 1309, 1327 ARM_VMLAslv8i16 = 1310, 1328 ARM_VMLAv16i8 = 1311, 1329 ARM_VMLAv2i32 = 1312, 1330 ARM_VMLAv4i16 = 1313, 1331 ARM_VMLAv4i32 = 1314, 1332 ARM_VMLAv8i16 = 1315, 1333 ARM_VMLAv8i8 = 1316, 1334 ARM_VMLSD = 1317, 1335 ARM_VMLSLslsv2i32 = 1318, 1336 ARM_VMLSLslsv4i16 = 1319, 1337 ARM_VMLSLsluv2i32 = 1320, 1338 ARM_VMLSLsluv4i16 = 1321, 1339 ARM_VMLSLsv2i64 = 1322, 1340 ARM_VMLSLsv4i32 = 1323, 1341 ARM_VMLSLsv8i16 = 1324, 1342 ARM_VMLSLuv2i64 = 1325, 1343 ARM_VMLSLuv4i32 = 1326, 1344 ARM_VMLSLuv8i16 = 1327, 1345 ARM_VMLSS = 1328, 1346 ARM_VMLSfd = 1329, 1347 ARM_VMLSfq = 1330, 1348 ARM_VMLSslfd = 1331, 1349 ARM_VMLSslfq = 1332, 1350 ARM_VMLSslv2i32 = 1333, 1351 ARM_VMLSslv4i16 = 1334, 1352 ARM_VMLSslv4i32 = 1335, 1353 ARM_VMLSslv8i16 = 1336, 1354 ARM_VMLSv16i8 = 1337, 1355 ARM_VMLSv2i32 = 1338, 1356 ARM_VMLSv4i16 = 1339, 1357 ARM_VMLSv4i32 = 1340, 1358 ARM_VMLSv8i16 = 1341, 1359 ARM_VMLSv8i8 = 1342, 1360 ARM_VMOVD = 1343, 1361 ARM_VMOVD0 = 1344, 1362 ARM_VMOVDRR = 1345, 1363 ARM_VMOVDcc = 1346, 1364 ARM_VMOVLsv2i64 = 1347, 1365 ARM_VMOVLsv4i32 = 1348, 1366 ARM_VMOVLsv8i16 = 1349, 1367 ARM_VMOVLuv2i64 = 1350, 1368 ARM_VMOVLuv4i32 = 1351, 1369 ARM_VMOVLuv8i16 = 1352, 1370 ARM_VMOVNv2i32 = 1353, 1371 ARM_VMOVNv4i16 = 1354, 1372 ARM_VMOVNv8i8 = 1355, 1373 ARM_VMOVQ0 = 1356, 1374 ARM_VMOVRRD = 1357, 1375 ARM_VMOVRRS = 1358, 1376 ARM_VMOVRS = 1359, 1377 ARM_VMOVS = 1360, 1378 ARM_VMOVSR = 1361, 1379 ARM_VMOVSRR = 1362, 1380 ARM_VMOVScc = 1363, 1381 ARM_VMOVv16i8 = 1364, 1382 ARM_VMOVv1i64 = 1365, 1383 ARM_VMOVv2f32 = 1366, 1384 ARM_VMOVv2i32 = 1367, 1385 ARM_VMOVv2i64 = 1368, 1386 ARM_VMOVv4f32 = 1369, 1387 ARM_VMOVv4i16 = 1370, 1388 ARM_VMOVv4i32 = 1371, 1389 ARM_VMOVv8i16 = 1372, 1390 ARM_VMOVv8i8 = 1373, 1391 ARM_VMRS = 1374, 1392 ARM_VMRS_FPEXC = 1375, 1393 ARM_VMRS_FPINST = 1376, 1394 ARM_VMRS_FPINST2 = 1377, 1395 ARM_VMRS_FPSID = 1378, 1396 ARM_VMRS_MVFR0 = 1379, 1397 ARM_VMRS_MVFR1 = 1380, 1398 ARM_VMRS_MVFR2 = 1381, 1399 ARM_VMSR = 1382, 1400 ARM_VMSR_FPEXC = 1383, 1401 ARM_VMSR_FPINST = 1384, 1402 ARM_VMSR_FPINST2 = 1385, 1403 ARM_VMSR_FPSID = 1386, 1404 ARM_VMULD = 1387, 1405 ARM_VMULLp64 = 1388, 1406 ARM_VMULLp8 = 1389, 1407 ARM_VMULLslsv2i32 = 1390, 1408 ARM_VMULLslsv4i16 = 1391, 1409 ARM_VMULLsluv2i32 = 1392, 1410 ARM_VMULLsluv4i16 = 1393, 1411 ARM_VMULLsv2i64 = 1394, 1412 ARM_VMULLsv4i32 = 1395, 1413 ARM_VMULLsv8i16 = 1396, 1414 ARM_VMULLuv2i64 = 1397, 1415 ARM_VMULLuv4i32 = 1398, 1416 ARM_VMULLuv8i16 = 1399, 1417 ARM_VMULS = 1400, 1418 ARM_VMULfd = 1401, 1419 ARM_VMULfq = 1402, 1420 ARM_VMULpd = 1403, 1421 ARM_VMULpq = 1404, 1422 ARM_VMULslfd = 1405, 1423 ARM_VMULslfq = 1406, 1424 ARM_VMULslv2i32 = 1407, 1425 ARM_VMULslv4i16 = 1408, 1426 ARM_VMULslv4i32 = 1409, 1427 ARM_VMULslv8i16 = 1410, 1428 ARM_VMULv16i8 = 1411, 1429 ARM_VMULv2i32 = 1412, 1430 ARM_VMULv4i16 = 1413, 1431 ARM_VMULv4i32 = 1414, 1432 ARM_VMULv8i16 = 1415, 1433 ARM_VMULv8i8 = 1416, 1434 ARM_VMVNd = 1417, 1435 ARM_VMVNq = 1418, 1436 ARM_VMVNv2i32 = 1419, 1437 ARM_VMVNv4i16 = 1420, 1438 ARM_VMVNv4i32 = 1421, 1439 ARM_VMVNv8i16 = 1422, 1440 ARM_VNEGD = 1423, 1441 ARM_VNEGS = 1424, 1442 ARM_VNEGf32q = 1425, 1443 ARM_VNEGfd = 1426, 1444 ARM_VNEGs16d = 1427, 1445 ARM_VNEGs16q = 1428, 1446 ARM_VNEGs32d = 1429, 1447 ARM_VNEGs32q = 1430, 1448 ARM_VNEGs8d = 1431, 1449 ARM_VNEGs8q = 1432, 1450 ARM_VNMLAD = 1433, 1451 ARM_VNMLAS = 1434, 1452 ARM_VNMLSD = 1435, 1453 ARM_VNMLSS = 1436, 1454 ARM_VNMULD = 1437, 1455 ARM_VNMULS = 1438, 1456 ARM_VORNd = 1439, 1457 ARM_VORNq = 1440, 1458 ARM_VORRd = 1441, 1459 ARM_VORRiv2i32 = 1442, 1460 ARM_VORRiv4i16 = 1443, 1461 ARM_VORRiv4i32 = 1444, 1462 ARM_VORRiv8i16 = 1445, 1463 ARM_VORRq = 1446, 1464 ARM_VPADALsv16i8 = 1447, 1465 ARM_VPADALsv2i32 = 1448, 1466 ARM_VPADALsv4i16 = 1449, 1467 ARM_VPADALsv4i32 = 1450, 1468 ARM_VPADALsv8i16 = 1451, 1469 ARM_VPADALsv8i8 = 1452, 1470 ARM_VPADALuv16i8 = 1453, 1471 ARM_VPADALuv2i32 = 1454, 1472 ARM_VPADALuv4i16 = 1455, 1473 ARM_VPADALuv4i32 = 1456, 1474 ARM_VPADALuv8i16 = 1457, 1475 ARM_VPADALuv8i8 = 1458, 1476 ARM_VPADDLsv16i8 = 1459, 1477 ARM_VPADDLsv2i32 = 1460, 1478 ARM_VPADDLsv4i16 = 1461, 1479 ARM_VPADDLsv4i32 = 1462, 1480 ARM_VPADDLsv8i16 = 1463, 1481 ARM_VPADDLsv8i8 = 1464, 1482 ARM_VPADDLuv16i8 = 1465, 1483 ARM_VPADDLuv2i32 = 1466, 1484 ARM_VPADDLuv4i16 = 1467, 1485 ARM_VPADDLuv4i32 = 1468, 1486 ARM_VPADDLuv8i16 = 1469, 1487 ARM_VPADDLuv8i8 = 1470, 1488 ARM_VPADDf = 1471, 1489 ARM_VPADDi16 = 1472, 1490 ARM_VPADDi32 = 1473, 1491 ARM_VPADDi8 = 1474, 1492 ARM_VPMAXf = 1475, 1493 ARM_VPMAXs16 = 1476, 1494 ARM_VPMAXs32 = 1477, 1495 ARM_VPMAXs8 = 1478, 1496 ARM_VPMAXu16 = 1479, 1497 ARM_VPMAXu32 = 1480, 1498 ARM_VPMAXu8 = 1481, 1499 ARM_VPMINf = 1482, 1500 ARM_VPMINs16 = 1483, 1501 ARM_VPMINs32 = 1484, 1502 ARM_VPMINs8 = 1485, 1503 ARM_VPMINu16 = 1486, 1504 ARM_VPMINu32 = 1487, 1505 ARM_VPMINu8 = 1488, 1506 ARM_VQABSv16i8 = 1489, 1507 ARM_VQABSv2i32 = 1490, 1508 ARM_VQABSv4i16 = 1491, 1509 ARM_VQABSv4i32 = 1492, 1510 ARM_VQABSv8i16 = 1493, 1511 ARM_VQABSv8i8 = 1494, 1512 ARM_VQADDsv16i8 = 1495, 1513 ARM_VQADDsv1i64 = 1496, 1514 ARM_VQADDsv2i32 = 1497, 1515 ARM_VQADDsv2i64 = 1498, 1516 ARM_VQADDsv4i16 = 1499, 1517 ARM_VQADDsv4i32 = 1500, 1518 ARM_VQADDsv8i16 = 1501, 1519 ARM_VQADDsv8i8 = 1502, 1520 ARM_VQADDuv16i8 = 1503, 1521 ARM_VQADDuv1i64 = 1504, 1522 ARM_VQADDuv2i32 = 1505, 1523 ARM_VQADDuv2i64 = 1506, 1524 ARM_VQADDuv4i16 = 1507, 1525 ARM_VQADDuv4i32 = 1508, 1526 ARM_VQADDuv8i16 = 1509, 1527 ARM_VQADDuv8i8 = 1510, 1528 ARM_VQDMLALslv2i32 = 1511, 1529 ARM_VQDMLALslv4i16 = 1512, 1530 ARM_VQDMLALv2i64 = 1513, 1531 ARM_VQDMLALv4i32 = 1514, 1532 ARM_VQDMLSLslv2i32 = 1515, 1533 ARM_VQDMLSLslv4i16 = 1516, 1534 ARM_VQDMLSLv2i64 = 1517, 1535 ARM_VQDMLSLv4i32 = 1518, 1536 ARM_VQDMULHslv2i32 = 1519, 1537 ARM_VQDMULHslv4i16 = 1520, 1538 ARM_VQDMULHslv4i32 = 1521, 1539 ARM_VQDMULHslv8i16 = 1522, 1540 ARM_VQDMULHv2i32 = 1523, 1541 ARM_VQDMULHv4i16 = 1524, 1542 ARM_VQDMULHv4i32 = 1525, 1543 ARM_VQDMULHv8i16 = 1526, 1544 ARM_VQDMULLslv2i32 = 1527, 1545 ARM_VQDMULLslv4i16 = 1528, 1546 ARM_VQDMULLv2i64 = 1529, 1547 ARM_VQDMULLv4i32 = 1530, 1548 ARM_VQMOVNsuv2i32 = 1531, 1549 ARM_VQMOVNsuv4i16 = 1532, 1550 ARM_VQMOVNsuv8i8 = 1533, 1551 ARM_VQMOVNsv2i32 = 1534, 1552 ARM_VQMOVNsv4i16 = 1535, 1553 ARM_VQMOVNsv8i8 = 1536, 1554 ARM_VQMOVNuv2i32 = 1537, 1555 ARM_VQMOVNuv4i16 = 1538, 1556 ARM_VQMOVNuv8i8 = 1539, 1557 ARM_VQNEGv16i8 = 1540, 1558 ARM_VQNEGv2i32 = 1541, 1559 ARM_VQNEGv4i16 = 1542, 1560 ARM_VQNEGv4i32 = 1543, 1561 ARM_VQNEGv8i16 = 1544, 1562 ARM_VQNEGv8i8 = 1545, 1563 ARM_VQRDMULHslv2i32 = 1546, 1564 ARM_VQRDMULHslv4i16 = 1547, 1565 ARM_VQRDMULHslv4i32 = 1548, 1566 ARM_VQRDMULHslv8i16 = 1549, 1567 ARM_VQRDMULHv2i32 = 1550, 1568 ARM_VQRDMULHv4i16 = 1551, 1569 ARM_VQRDMULHv4i32 = 1552, 1570 ARM_VQRDMULHv8i16 = 1553, 1571 ARM_VQRSHLsv16i8 = 1554, 1572 ARM_VQRSHLsv1i64 = 1555, 1573 ARM_VQRSHLsv2i32 = 1556, 1574 ARM_VQRSHLsv2i64 = 1557, 1575 ARM_VQRSHLsv4i16 = 1558, 1576 ARM_VQRSHLsv4i32 = 1559, 1577 ARM_VQRSHLsv8i16 = 1560, 1578 ARM_VQRSHLsv8i8 = 1561, 1579 ARM_VQRSHLuv16i8 = 1562, 1580 ARM_VQRSHLuv1i64 = 1563, 1581 ARM_VQRSHLuv2i32 = 1564, 1582 ARM_VQRSHLuv2i64 = 1565, 1583 ARM_VQRSHLuv4i16 = 1566, 1584 ARM_VQRSHLuv4i32 = 1567, 1585 ARM_VQRSHLuv8i16 = 1568, 1586 ARM_VQRSHLuv8i8 = 1569, 1587 ARM_VQRSHRNsv2i32 = 1570, 1588 ARM_VQRSHRNsv4i16 = 1571, 1589 ARM_VQRSHRNsv8i8 = 1572, 1590 ARM_VQRSHRNuv2i32 = 1573, 1591 ARM_VQRSHRNuv4i16 = 1574, 1592 ARM_VQRSHRNuv8i8 = 1575, 1593 ARM_VQRSHRUNv2i32 = 1576, 1594 ARM_VQRSHRUNv4i16 = 1577, 1595 ARM_VQRSHRUNv8i8 = 1578, 1596 ARM_VQSHLsiv16i8 = 1579, 1597 ARM_VQSHLsiv1i64 = 1580, 1598 ARM_VQSHLsiv2i32 = 1581, 1599 ARM_VQSHLsiv2i64 = 1582, 1600 ARM_VQSHLsiv4i16 = 1583, 1601 ARM_VQSHLsiv4i32 = 1584, 1602 ARM_VQSHLsiv8i16 = 1585, 1603 ARM_VQSHLsiv8i8 = 1586, 1604 ARM_VQSHLsuv16i8 = 1587, 1605 ARM_VQSHLsuv1i64 = 1588, 1606 ARM_VQSHLsuv2i32 = 1589, 1607 ARM_VQSHLsuv2i64 = 1590, 1608 ARM_VQSHLsuv4i16 = 1591, 1609 ARM_VQSHLsuv4i32 = 1592, 1610 ARM_VQSHLsuv8i16 = 1593, 1611 ARM_VQSHLsuv8i8 = 1594, 1612 ARM_VQSHLsv16i8 = 1595, 1613 ARM_VQSHLsv1i64 = 1596, 1614 ARM_VQSHLsv2i32 = 1597, 1615 ARM_VQSHLsv2i64 = 1598, 1616 ARM_VQSHLsv4i16 = 1599, 1617 ARM_VQSHLsv4i32 = 1600, 1618 ARM_VQSHLsv8i16 = 1601, 1619 ARM_VQSHLsv8i8 = 1602, 1620 ARM_VQSHLuiv16i8 = 1603, 1621 ARM_VQSHLuiv1i64 = 1604, 1622 ARM_VQSHLuiv2i32 = 1605, 1623 ARM_VQSHLuiv2i64 = 1606, 1624 ARM_VQSHLuiv4i16 = 1607, 1625 ARM_VQSHLuiv4i32 = 1608, 1626 ARM_VQSHLuiv8i16 = 1609, 1627 ARM_VQSHLuiv8i8 = 1610, 1628 ARM_VQSHLuv16i8 = 1611, 1629 ARM_VQSHLuv1i64 = 1612, 1630 ARM_VQSHLuv2i32 = 1613, 1631 ARM_VQSHLuv2i64 = 1614, 1632 ARM_VQSHLuv4i16 = 1615, 1633 ARM_VQSHLuv4i32 = 1616, 1634 ARM_VQSHLuv8i16 = 1617, 1635 ARM_VQSHLuv8i8 = 1618, 1636 ARM_VQSHRNsv2i32 = 1619, 1637 ARM_VQSHRNsv4i16 = 1620, 1638 ARM_VQSHRNsv8i8 = 1621, 1639 ARM_VQSHRNuv2i32 = 1622, 1640 ARM_VQSHRNuv4i16 = 1623, 1641 ARM_VQSHRNuv8i8 = 1624, 1642 ARM_VQSHRUNv2i32 = 1625, 1643 ARM_VQSHRUNv4i16 = 1626, 1644 ARM_VQSHRUNv8i8 = 1627, 1645 ARM_VQSUBsv16i8 = 1628, 1646 ARM_VQSUBsv1i64 = 1629, 1647 ARM_VQSUBsv2i32 = 1630, 1648 ARM_VQSUBsv2i64 = 1631, 1649 ARM_VQSUBsv4i16 = 1632, 1650 ARM_VQSUBsv4i32 = 1633, 1651 ARM_VQSUBsv8i16 = 1634, 1652 ARM_VQSUBsv8i8 = 1635, 1653 ARM_VQSUBuv16i8 = 1636, 1654 ARM_VQSUBuv1i64 = 1637, 1655 ARM_VQSUBuv2i32 = 1638, 1656 ARM_VQSUBuv2i64 = 1639, 1657 ARM_VQSUBuv4i16 = 1640, 1658 ARM_VQSUBuv4i32 = 1641, 1659 ARM_VQSUBuv8i16 = 1642, 1660 ARM_VQSUBuv8i8 = 1643, 1661 ARM_VRADDHNv2i32 = 1644, 1662 ARM_VRADDHNv4i16 = 1645, 1663 ARM_VRADDHNv8i8 = 1646, 1664 ARM_VRECPEd = 1647, 1665 ARM_VRECPEfd = 1648, 1666 ARM_VRECPEfq = 1649, 1667 ARM_VRECPEq = 1650, 1668 ARM_VRECPSfd = 1651, 1669 ARM_VRECPSfq = 1652, 1670 ARM_VREV16d8 = 1653, 1671 ARM_VREV16q8 = 1654, 1672 ARM_VREV32d16 = 1655, 1673 ARM_VREV32d8 = 1656, 1674 ARM_VREV32q16 = 1657, 1675 ARM_VREV32q8 = 1658, 1676 ARM_VREV64d16 = 1659, 1677 ARM_VREV64d32 = 1660, 1678 ARM_VREV64d8 = 1661, 1679 ARM_VREV64q16 = 1662, 1680 ARM_VREV64q32 = 1663, 1681 ARM_VREV64q8 = 1664, 1682 ARM_VRHADDsv16i8 = 1665, 1683 ARM_VRHADDsv2i32 = 1666, 1684 ARM_VRHADDsv4i16 = 1667, 1685 ARM_VRHADDsv4i32 = 1668, 1686 ARM_VRHADDsv8i16 = 1669, 1687 ARM_VRHADDsv8i8 = 1670, 1688 ARM_VRHADDuv16i8 = 1671, 1689 ARM_VRHADDuv2i32 = 1672, 1690 ARM_VRHADDuv4i16 = 1673, 1691 ARM_VRHADDuv4i32 = 1674, 1692 ARM_VRHADDuv8i16 = 1675, 1693 ARM_VRHADDuv8i8 = 1676, 1694 ARM_VRINTAD = 1677, 1695 ARM_VRINTAND = 1678, 1696 ARM_VRINTANQ = 1679, 1697 ARM_VRINTAS = 1680, 1698 ARM_VRINTMD = 1681, 1699 ARM_VRINTMND = 1682, 1700 ARM_VRINTMNQ = 1683, 1701 ARM_VRINTMS = 1684, 1702 ARM_VRINTND = 1685, 1703 ARM_VRINTNND = 1686, 1704 ARM_VRINTNNQ = 1687, 1705 ARM_VRINTNS = 1688, 1706 ARM_VRINTPD = 1689, 1707 ARM_VRINTPND = 1690, 1708 ARM_VRINTPNQ = 1691, 1709 ARM_VRINTPS = 1692, 1710 ARM_VRINTRD = 1693, 1711 ARM_VRINTRS = 1694, 1712 ARM_VRINTXD = 1695, 1713 ARM_VRINTXND = 1696, 1714 ARM_VRINTXNQ = 1697, 1715 ARM_VRINTXS = 1698, 1716 ARM_VRINTZD = 1699, 1717 ARM_VRINTZND = 1700, 1718 ARM_VRINTZNQ = 1701, 1719 ARM_VRINTZS = 1702, 1720 ARM_VRSHLsv16i8 = 1703, 1721 ARM_VRSHLsv1i64 = 1704, 1722 ARM_VRSHLsv2i32 = 1705, 1723 ARM_VRSHLsv2i64 = 1706, 1724 ARM_VRSHLsv4i16 = 1707, 1725 ARM_VRSHLsv4i32 = 1708, 1726 ARM_VRSHLsv8i16 = 1709, 1727 ARM_VRSHLsv8i8 = 1710, 1728 ARM_VRSHLuv16i8 = 1711, 1729 ARM_VRSHLuv1i64 = 1712, 1730 ARM_VRSHLuv2i32 = 1713, 1731 ARM_VRSHLuv2i64 = 1714, 1732 ARM_VRSHLuv4i16 = 1715, 1733 ARM_VRSHLuv4i32 = 1716, 1734 ARM_VRSHLuv8i16 = 1717, 1735 ARM_VRSHLuv8i8 = 1718, 1736 ARM_VRSHRNv2i32 = 1719, 1737 ARM_VRSHRNv4i16 = 1720, 1738 ARM_VRSHRNv8i8 = 1721, 1739 ARM_VRSHRsv16i8 = 1722, 1740 ARM_VRSHRsv1i64 = 1723, 1741 ARM_VRSHRsv2i32 = 1724, 1742 ARM_VRSHRsv2i64 = 1725, 1743 ARM_VRSHRsv4i16 = 1726, 1744 ARM_VRSHRsv4i32 = 1727, 1745 ARM_VRSHRsv8i16 = 1728, 1746 ARM_VRSHRsv8i8 = 1729, 1747 ARM_VRSHRuv16i8 = 1730, 1748 ARM_VRSHRuv1i64 = 1731, 1749 ARM_VRSHRuv2i32 = 1732, 1750 ARM_VRSHRuv2i64 = 1733, 1751 ARM_VRSHRuv4i16 = 1734, 1752 ARM_VRSHRuv4i32 = 1735, 1753 ARM_VRSHRuv8i16 = 1736, 1754 ARM_VRSHRuv8i8 = 1737, 1755 ARM_VRSQRTEd = 1738, 1756 ARM_VRSQRTEfd = 1739, 1757 ARM_VRSQRTEfq = 1740, 1758 ARM_VRSQRTEq = 1741, 1759 ARM_VRSQRTSfd = 1742, 1760 ARM_VRSQRTSfq = 1743, 1761 ARM_VRSRAsv16i8 = 1744, 1762 ARM_VRSRAsv1i64 = 1745, 1763 ARM_VRSRAsv2i32 = 1746, 1764 ARM_VRSRAsv2i64 = 1747, 1765 ARM_VRSRAsv4i16 = 1748, 1766 ARM_VRSRAsv4i32 = 1749, 1767 ARM_VRSRAsv8i16 = 1750, 1768 ARM_VRSRAsv8i8 = 1751, 1769 ARM_VRSRAuv16i8 = 1752, 1770 ARM_VRSRAuv1i64 = 1753, 1771 ARM_VRSRAuv2i32 = 1754, 1772 ARM_VRSRAuv2i64 = 1755, 1773 ARM_VRSRAuv4i16 = 1756, 1774 ARM_VRSRAuv4i32 = 1757, 1775 ARM_VRSRAuv8i16 = 1758, 1776 ARM_VRSRAuv8i8 = 1759, 1777 ARM_VRSUBHNv2i32 = 1760, 1778 ARM_VRSUBHNv4i16 = 1761, 1779 ARM_VRSUBHNv8i8 = 1762, 1780 ARM_VSELEQD = 1763, 1781 ARM_VSELEQS = 1764, 1782 ARM_VSELGED = 1765, 1783 ARM_VSELGES = 1766, 1784 ARM_VSELGTD = 1767, 1785 ARM_VSELGTS = 1768, 1786 ARM_VSELVSD = 1769, 1787 ARM_VSELVSS = 1770, 1788 ARM_VSETLNi16 = 1771, 1789 ARM_VSETLNi32 = 1772, 1790 ARM_VSETLNi8 = 1773, 1791 ARM_VSHLLi16 = 1774, 1792 ARM_VSHLLi32 = 1775, 1793 ARM_VSHLLi8 = 1776, 1794 ARM_VSHLLsv2i64 = 1777, 1795 ARM_VSHLLsv4i32 = 1778, 1796 ARM_VSHLLsv8i16 = 1779, 1797 ARM_VSHLLuv2i64 = 1780, 1798 ARM_VSHLLuv4i32 = 1781, 1799 ARM_VSHLLuv8i16 = 1782, 1800 ARM_VSHLiv16i8 = 1783, 1801 ARM_VSHLiv1i64 = 1784, 1802 ARM_VSHLiv2i32 = 1785, 1803 ARM_VSHLiv2i64 = 1786, 1804 ARM_VSHLiv4i16 = 1787, 1805 ARM_VSHLiv4i32 = 1788, 1806 ARM_VSHLiv8i16 = 1789, 1807 ARM_VSHLiv8i8 = 1790, 1808 ARM_VSHLsv16i8 = 1791, 1809 ARM_VSHLsv1i64 = 1792, 1810 ARM_VSHLsv2i32 = 1793, 1811 ARM_VSHLsv2i64 = 1794, 1812 ARM_VSHLsv4i16 = 1795, 1813 ARM_VSHLsv4i32 = 1796, 1814 ARM_VSHLsv8i16 = 1797, 1815 ARM_VSHLsv8i8 = 1798, 1816 ARM_VSHLuv16i8 = 1799, 1817 ARM_VSHLuv1i64 = 1800, 1818 ARM_VSHLuv2i32 = 1801, 1819 ARM_VSHLuv2i64 = 1802, 1820 ARM_VSHLuv4i16 = 1803, 1821 ARM_VSHLuv4i32 = 1804, 1822 ARM_VSHLuv8i16 = 1805, 1823 ARM_VSHLuv8i8 = 1806, 1824 ARM_VSHRNv2i32 = 1807, 1825 ARM_VSHRNv4i16 = 1808, 1826 ARM_VSHRNv8i8 = 1809, 1827 ARM_VSHRsv16i8 = 1810, 1828 ARM_VSHRsv1i64 = 1811, 1829 ARM_VSHRsv2i32 = 1812, 1830 ARM_VSHRsv2i64 = 1813, 1831 ARM_VSHRsv4i16 = 1814, 1832 ARM_VSHRsv4i32 = 1815, 1833 ARM_VSHRsv8i16 = 1816, 1834 ARM_VSHRsv8i8 = 1817, 1835 ARM_VSHRuv16i8 = 1818, 1836 ARM_VSHRuv1i64 = 1819, 1837 ARM_VSHRuv2i32 = 1820, 1838 ARM_VSHRuv2i64 = 1821, 1839 ARM_VSHRuv4i16 = 1822, 1840 ARM_VSHRuv4i32 = 1823, 1841 ARM_VSHRuv8i16 = 1824, 1842 ARM_VSHRuv8i8 = 1825, 1843 ARM_VSHTOD = 1826, 1844 ARM_VSHTOS = 1827, 1845 ARM_VSITOD = 1828, 1846 ARM_VSITOS = 1829, 1847 ARM_VSLIv16i8 = 1830, 1848 ARM_VSLIv1i64 = 1831, 1849 ARM_VSLIv2i32 = 1832, 1850 ARM_VSLIv2i64 = 1833, 1851 ARM_VSLIv4i16 = 1834, 1852 ARM_VSLIv4i32 = 1835, 1853 ARM_VSLIv8i16 = 1836, 1854 ARM_VSLIv8i8 = 1837, 1855 ARM_VSLTOD = 1838, 1856 ARM_VSLTOS = 1839, 1857 ARM_VSQRTD = 1840, 1858 ARM_VSQRTS = 1841, 1859 ARM_VSRAsv16i8 = 1842, 1860 ARM_VSRAsv1i64 = 1843, 1861 ARM_VSRAsv2i32 = 1844, 1862 ARM_VSRAsv2i64 = 1845, 1863 ARM_VSRAsv4i16 = 1846, 1864 ARM_VSRAsv4i32 = 1847, 1865 ARM_VSRAsv8i16 = 1848, 1866 ARM_VSRAsv8i8 = 1849, 1867 ARM_VSRAuv16i8 = 1850, 1868 ARM_VSRAuv1i64 = 1851, 1869 ARM_VSRAuv2i32 = 1852, 1870 ARM_VSRAuv2i64 = 1853, 1871 ARM_VSRAuv4i16 = 1854, 1872 ARM_VSRAuv4i32 = 1855, 1873 ARM_VSRAuv8i16 = 1856, 1874 ARM_VSRAuv8i8 = 1857, 1875 ARM_VSRIv16i8 = 1858, 1876 ARM_VSRIv1i64 = 1859, 1877 ARM_VSRIv2i32 = 1860, 1878 ARM_VSRIv2i64 = 1861, 1879 ARM_VSRIv4i16 = 1862, 1880 ARM_VSRIv4i32 = 1863, 1881 ARM_VSRIv8i16 = 1864, 1882 ARM_VSRIv8i8 = 1865, 1883 ARM_VST1LNd16 = 1866, 1884 ARM_VST1LNd16_UPD = 1867, 1885 ARM_VST1LNd32 = 1868, 1886 ARM_VST1LNd32_UPD = 1869, 1887 ARM_VST1LNd8 = 1870, 1888 ARM_VST1LNd8_UPD = 1871, 1889 ARM_VST1LNdAsm_16 = 1872, 1890 ARM_VST1LNdAsm_32 = 1873, 1891 ARM_VST1LNdAsm_8 = 1874, 1892 ARM_VST1LNdWB_fixed_Asm_16 = 1875, 1893 ARM_VST1LNdWB_fixed_Asm_32 = 1876, 1894 ARM_VST1LNdWB_fixed_Asm_8 = 1877, 1895 ARM_VST1LNdWB_register_Asm_16 = 1878, 1896 ARM_VST1LNdWB_register_Asm_32 = 1879, 1897 ARM_VST1LNdWB_register_Asm_8 = 1880, 1898 ARM_VST1LNq16Pseudo = 1881, 1899 ARM_VST1LNq16Pseudo_UPD = 1882, 1900 ARM_VST1LNq32Pseudo = 1883, 1901 ARM_VST1LNq32Pseudo_UPD = 1884, 1902 ARM_VST1LNq8Pseudo = 1885, 1903 ARM_VST1LNq8Pseudo_UPD = 1886, 1904 ARM_VST1d16 = 1887, 1905 ARM_VST1d16Q = 1888, 1906 ARM_VST1d16Qwb_fixed = 1889, 1907 ARM_VST1d16Qwb_register = 1890, 1908 ARM_VST1d16T = 1891, 1909 ARM_VST1d16Twb_fixed = 1892, 1910 ARM_VST1d16Twb_register = 1893, 1911 ARM_VST1d16wb_fixed = 1894, 1912 ARM_VST1d16wb_register = 1895, 1913 ARM_VST1d32 = 1896, 1914 ARM_VST1d32Q = 1897, 1915 ARM_VST1d32Qwb_fixed = 1898, 1916 ARM_VST1d32Qwb_register = 1899, 1917 ARM_VST1d32T = 1900, 1918 ARM_VST1d32Twb_fixed = 1901, 1919 ARM_VST1d32Twb_register = 1902, 1920 ARM_VST1d32wb_fixed = 1903, 1921 ARM_VST1d32wb_register = 1904, 1922 ARM_VST1d64 = 1905, 1923 ARM_VST1d64Q = 1906, 1924 ARM_VST1d64QPseudo = 1907, 1925 ARM_VST1d64QPseudoWB_fixed = 1908, 1926 ARM_VST1d64QPseudoWB_register = 1909, 1927 ARM_VST1d64Qwb_fixed = 1910, 1928 ARM_VST1d64Qwb_register = 1911, 1929 ARM_VST1d64T = 1912, 1930 ARM_VST1d64TPseudo = 1913, 1931 ARM_VST1d64TPseudoWB_fixed = 1914, 1932 ARM_VST1d64TPseudoWB_register = 1915, 1933 ARM_VST1d64Twb_fixed = 1916, 1934 ARM_VST1d64Twb_register = 1917, 1935 ARM_VST1d64wb_fixed = 1918, 1936 ARM_VST1d64wb_register = 1919, 1937 ARM_VST1d8 = 1920, 1938 ARM_VST1d8Q = 1921, 1939 ARM_VST1d8Qwb_fixed = 1922, 1940 ARM_VST1d8Qwb_register = 1923, 1941 ARM_VST1d8T = 1924, 1942 ARM_VST1d8Twb_fixed = 1925, 1943 ARM_VST1d8Twb_register = 1926, 1944 ARM_VST1d8wb_fixed = 1927, 1945 ARM_VST1d8wb_register = 1928, 1946 ARM_VST1q16 = 1929, 1947 ARM_VST1q16wb_fixed = 1930, 1948 ARM_VST1q16wb_register = 1931, 1949 ARM_VST1q32 = 1932, 1950 ARM_VST1q32wb_fixed = 1933, 1951 ARM_VST1q32wb_register = 1934, 1952 ARM_VST1q64 = 1935, 1953 ARM_VST1q64wb_fixed = 1936, 1954 ARM_VST1q64wb_register = 1937, 1955 ARM_VST1q8 = 1938, 1956 ARM_VST1q8wb_fixed = 1939, 1957 ARM_VST1q8wb_register = 1940, 1958 ARM_VST2LNd16 = 1941, 1959 ARM_VST2LNd16Pseudo = 1942, 1960 ARM_VST2LNd16Pseudo_UPD = 1943, 1961 ARM_VST2LNd16_UPD = 1944, 1962 ARM_VST2LNd32 = 1945, 1963 ARM_VST2LNd32Pseudo = 1946, 1964 ARM_VST2LNd32Pseudo_UPD = 1947, 1965 ARM_VST2LNd32_UPD = 1948, 1966 ARM_VST2LNd8 = 1949, 1967 ARM_VST2LNd8Pseudo = 1950, 1968 ARM_VST2LNd8Pseudo_UPD = 1951, 1969 ARM_VST2LNd8_UPD = 1952, 1970 ARM_VST2LNdAsm_16 = 1953, 1971 ARM_VST2LNdAsm_32 = 1954, 1972 ARM_VST2LNdAsm_8 = 1955, 1973 ARM_VST2LNdWB_fixed_Asm_16 = 1956, 1974 ARM_VST2LNdWB_fixed_Asm_32 = 1957, 1975 ARM_VST2LNdWB_fixed_Asm_8 = 1958, 1976 ARM_VST2LNdWB_register_Asm_16 = 1959, 1977 ARM_VST2LNdWB_register_Asm_32 = 1960, 1978 ARM_VST2LNdWB_register_Asm_8 = 1961, 1979 ARM_VST2LNq16 = 1962, 1980 ARM_VST2LNq16Pseudo = 1963, 1981 ARM_VST2LNq16Pseudo_UPD = 1964, 1982 ARM_VST2LNq16_UPD = 1965, 1983 ARM_VST2LNq32 = 1966, 1984 ARM_VST2LNq32Pseudo = 1967, 1985 ARM_VST2LNq32Pseudo_UPD = 1968, 1986 ARM_VST2LNq32_UPD = 1969, 1987 ARM_VST2LNqAsm_16 = 1970, 1988 ARM_VST2LNqAsm_32 = 1971, 1989 ARM_VST2LNqWB_fixed_Asm_16 = 1972, 1990 ARM_VST2LNqWB_fixed_Asm_32 = 1973, 1991 ARM_VST2LNqWB_register_Asm_16 = 1974, 1992 ARM_VST2LNqWB_register_Asm_32 = 1975, 1993 ARM_VST2b16 = 1976, 1994 ARM_VST2b16wb_fixed = 1977, 1995 ARM_VST2b16wb_register = 1978, 1996 ARM_VST2b32 = 1979, 1997 ARM_VST2b32wb_fixed = 1980, 1998 ARM_VST2b32wb_register = 1981, 1999 ARM_VST2b8 = 1982, 2000 ARM_VST2b8wb_fixed = 1983, 2001 ARM_VST2b8wb_register = 1984, 2002 ARM_VST2d16 = 1985, 2003 ARM_VST2d16wb_fixed = 1986, 2004 ARM_VST2d16wb_register = 1987, 2005 ARM_VST2d32 = 1988, 2006 ARM_VST2d32wb_fixed = 1989, 2007 ARM_VST2d32wb_register = 1990, 2008 ARM_VST2d8 = 1991, 2009 ARM_VST2d8wb_fixed = 1992, 2010 ARM_VST2d8wb_register = 1993, 2011 ARM_VST2q16 = 1994, 2012 ARM_VST2q16Pseudo = 1995, 2013 ARM_VST2q16PseudoWB_fixed = 1996, 2014 ARM_VST2q16PseudoWB_register = 1997, 2015 ARM_VST2q16wb_fixed = 1998, 2016 ARM_VST2q16wb_register = 1999, 2017 ARM_VST2q32 = 2000, 2018 ARM_VST2q32Pseudo = 2001, 2019 ARM_VST2q32PseudoWB_fixed = 2002, 2020 ARM_VST2q32PseudoWB_register = 2003, 2021 ARM_VST2q32wb_fixed = 2004, 2022 ARM_VST2q32wb_register = 2005, 2023 ARM_VST2q8 = 2006, 2024 ARM_VST2q8Pseudo = 2007, 2025 ARM_VST2q8PseudoWB_fixed = 2008, 2026 ARM_VST2q8PseudoWB_register = 2009, 2027 ARM_VST2q8wb_fixed = 2010, 2028 ARM_VST2q8wb_register = 2011, 2029 ARM_VST3LNd16 = 2012, 2030 ARM_VST3LNd16Pseudo = 2013, 2031 ARM_VST3LNd16Pseudo_UPD = 2014, 2032 ARM_VST3LNd16_UPD = 2015, 2033 ARM_VST3LNd32 = 2016, 2034 ARM_VST3LNd32Pseudo = 2017, 2035 ARM_VST3LNd32Pseudo_UPD = 2018, 2036 ARM_VST3LNd32_UPD = 2019, 2037 ARM_VST3LNd8 = 2020, 2038 ARM_VST3LNd8Pseudo = 2021, 2039 ARM_VST3LNd8Pseudo_UPD = 2022, 2040 ARM_VST3LNd8_UPD = 2023, 2041 ARM_VST3LNdAsm_16 = 2024, 2042 ARM_VST3LNdAsm_32 = 2025, 2043 ARM_VST3LNdAsm_8 = 2026, 2044 ARM_VST3LNdWB_fixed_Asm_16 = 2027, 2045 ARM_VST3LNdWB_fixed_Asm_32 = 2028, 2046 ARM_VST3LNdWB_fixed_Asm_8 = 2029, 2047 ARM_VST3LNdWB_register_Asm_16 = 2030, 2048 ARM_VST3LNdWB_register_Asm_32 = 2031, 2049 ARM_VST3LNdWB_register_Asm_8 = 2032, 2050 ARM_VST3LNq16 = 2033, 2051 ARM_VST3LNq16Pseudo = 2034, 2052 ARM_VST3LNq16Pseudo_UPD = 2035, 2053 ARM_VST3LNq16_UPD = 2036, 2054 ARM_VST3LNq32 = 2037, 2055 ARM_VST3LNq32Pseudo = 2038, 2056 ARM_VST3LNq32Pseudo_UPD = 2039, 2057 ARM_VST3LNq32_UPD = 2040, 2058 ARM_VST3LNqAsm_16 = 2041, 2059 ARM_VST3LNqAsm_32 = 2042, 2060 ARM_VST3LNqWB_fixed_Asm_16 = 2043, 2061 ARM_VST3LNqWB_fixed_Asm_32 = 2044, 2062 ARM_VST3LNqWB_register_Asm_16 = 2045, 2063 ARM_VST3LNqWB_register_Asm_32 = 2046, 2064 ARM_VST3d16 = 2047, 2065 ARM_VST3d16Pseudo = 2048, 2066 ARM_VST3d16Pseudo_UPD = 2049, 2067 ARM_VST3d16_UPD = 2050, 2068 ARM_VST3d32 = 2051, 2069 ARM_VST3d32Pseudo = 2052, 2070 ARM_VST3d32Pseudo_UPD = 2053, 2071 ARM_VST3d32_UPD = 2054, 2072 ARM_VST3d8 = 2055, 2073 ARM_VST3d8Pseudo = 2056, 2074 ARM_VST3d8Pseudo_UPD = 2057, 2075 ARM_VST3d8_UPD = 2058, 2076 ARM_VST3dAsm_16 = 2059, 2077 ARM_VST3dAsm_32 = 2060, 2078 ARM_VST3dAsm_8 = 2061, 2079 ARM_VST3dWB_fixed_Asm_16 = 2062, 2080 ARM_VST3dWB_fixed_Asm_32 = 2063, 2081 ARM_VST3dWB_fixed_Asm_8 = 2064, 2082 ARM_VST3dWB_register_Asm_16 = 2065, 2083 ARM_VST3dWB_register_Asm_32 = 2066, 2084 ARM_VST3dWB_register_Asm_8 = 2067, 2085 ARM_VST3q16 = 2068, 2086 ARM_VST3q16Pseudo_UPD = 2069, 2087 ARM_VST3q16_UPD = 2070, 2088 ARM_VST3q16oddPseudo = 2071, 2089 ARM_VST3q16oddPseudo_UPD = 2072, 2090 ARM_VST3q32 = 2073, 2091 ARM_VST3q32Pseudo_UPD = 2074, 2092 ARM_VST3q32_UPD = 2075, 2093 ARM_VST3q32oddPseudo = 2076, 2094 ARM_VST3q32oddPseudo_UPD = 2077, 2095 ARM_VST3q8 = 2078, 2096 ARM_VST3q8Pseudo_UPD = 2079, 2097 ARM_VST3q8_UPD = 2080, 2098 ARM_VST3q8oddPseudo = 2081, 2099 ARM_VST3q8oddPseudo_UPD = 2082, 2100 ARM_VST3qAsm_16 = 2083, 2101 ARM_VST3qAsm_32 = 2084, 2102 ARM_VST3qAsm_8 = 2085, 2103 ARM_VST3qWB_fixed_Asm_16 = 2086, 2104 ARM_VST3qWB_fixed_Asm_32 = 2087, 2105 ARM_VST3qWB_fixed_Asm_8 = 2088, 2106 ARM_VST3qWB_register_Asm_16 = 2089, 2107 ARM_VST3qWB_register_Asm_32 = 2090, 2108 ARM_VST3qWB_register_Asm_8 = 2091, 2109 ARM_VST4LNd16 = 2092, 2110 ARM_VST4LNd16Pseudo = 2093, 2111 ARM_VST4LNd16Pseudo_UPD = 2094, 2112 ARM_VST4LNd16_UPD = 2095, 2113 ARM_VST4LNd32 = 2096, 2114 ARM_VST4LNd32Pseudo = 2097, 2115 ARM_VST4LNd32Pseudo_UPD = 2098, 2116 ARM_VST4LNd32_UPD = 2099, 2117 ARM_VST4LNd8 = 2100, 2118 ARM_VST4LNd8Pseudo = 2101, 2119 ARM_VST4LNd8Pseudo_UPD = 2102, 2120 ARM_VST4LNd8_UPD = 2103, 2121 ARM_VST4LNdAsm_16 = 2104, 2122 ARM_VST4LNdAsm_32 = 2105, 2123 ARM_VST4LNdAsm_8 = 2106, 2124 ARM_VST4LNdWB_fixed_Asm_16 = 2107, 2125 ARM_VST4LNdWB_fixed_Asm_32 = 2108, 2126 ARM_VST4LNdWB_fixed_Asm_8 = 2109, 2127 ARM_VST4LNdWB_register_Asm_16 = 2110, 2128 ARM_VST4LNdWB_register_Asm_32 = 2111, 2129 ARM_VST4LNdWB_register_Asm_8 = 2112, 2130 ARM_VST4LNq16 = 2113, 2131 ARM_VST4LNq16Pseudo = 2114, 2132 ARM_VST4LNq16Pseudo_UPD = 2115, 2133 ARM_VST4LNq16_UPD = 2116, 2134 ARM_VST4LNq32 = 2117, 2135 ARM_VST4LNq32Pseudo = 2118, 2136 ARM_VST4LNq32Pseudo_UPD = 2119, 2137 ARM_VST4LNq32_UPD = 2120, 2138 ARM_VST4LNqAsm_16 = 2121, 2139 ARM_VST4LNqAsm_32 = 2122, 2140 ARM_VST4LNqWB_fixed_Asm_16 = 2123, 2141 ARM_VST4LNqWB_fixed_Asm_32 = 2124, 2142 ARM_VST4LNqWB_register_Asm_16 = 2125, 2143 ARM_VST4LNqWB_register_Asm_32 = 2126, 2144 ARM_VST4d16 = 2127, 2145 ARM_VST4d16Pseudo = 2128, 2146 ARM_VST4d16Pseudo_UPD = 2129, 2147 ARM_VST4d16_UPD = 2130, 2148 ARM_VST4d32 = 2131, 2149 ARM_VST4d32Pseudo = 2132, 2150 ARM_VST4d32Pseudo_UPD = 2133, 2151 ARM_VST4d32_UPD = 2134, 2152 ARM_VST4d8 = 2135, 2153 ARM_VST4d8Pseudo = 2136, 2154 ARM_VST4d8Pseudo_UPD = 2137, 2155 ARM_VST4d8_UPD = 2138, 2156 ARM_VST4dAsm_16 = 2139, 2157 ARM_VST4dAsm_32 = 2140, 2158 ARM_VST4dAsm_8 = 2141, 2159 ARM_VST4dWB_fixed_Asm_16 = 2142, 2160 ARM_VST4dWB_fixed_Asm_32 = 2143, 2161 ARM_VST4dWB_fixed_Asm_8 = 2144, 2162 ARM_VST4dWB_register_Asm_16 = 2145, 2163 ARM_VST4dWB_register_Asm_32 = 2146, 2164 ARM_VST4dWB_register_Asm_8 = 2147, 2165 ARM_VST4q16 = 2148, 2166 ARM_VST4q16Pseudo_UPD = 2149, 2167 ARM_VST4q16_UPD = 2150, 2168 ARM_VST4q16oddPseudo = 2151, 2169 ARM_VST4q16oddPseudo_UPD = 2152, 2170 ARM_VST4q32 = 2153, 2171 ARM_VST4q32Pseudo_UPD = 2154, 2172 ARM_VST4q32_UPD = 2155, 2173 ARM_VST4q32oddPseudo = 2156, 2174 ARM_VST4q32oddPseudo_UPD = 2157, 2175 ARM_VST4q8 = 2158, 2176 ARM_VST4q8Pseudo_UPD = 2159, 2177 ARM_VST4q8_UPD = 2160, 2178 ARM_VST4q8oddPseudo = 2161, 2179 ARM_VST4q8oddPseudo_UPD = 2162, 2180 ARM_VST4qAsm_16 = 2163, 2181 ARM_VST4qAsm_32 = 2164, 2182 ARM_VST4qAsm_8 = 2165, 2183 ARM_VST4qWB_fixed_Asm_16 = 2166, 2184 ARM_VST4qWB_fixed_Asm_32 = 2167, 2185 ARM_VST4qWB_fixed_Asm_8 = 2168, 2186 ARM_VST4qWB_register_Asm_16 = 2169, 2187 ARM_VST4qWB_register_Asm_32 = 2170, 2188 ARM_VST4qWB_register_Asm_8 = 2171, 2189 ARM_VSTMDDB_UPD = 2172, 2190 ARM_VSTMDIA = 2173, 2191 ARM_VSTMDIA_UPD = 2174, 2192 ARM_VSTMQIA = 2175, 2193 ARM_VSTMSDB_UPD = 2176, 2194 ARM_VSTMSIA = 2177, 2195 ARM_VSTMSIA_UPD = 2178, 2196 ARM_VSTRD = 2179, 2197 ARM_VSTRS = 2180, 2198 ARM_VSUBD = 2181, 2199 ARM_VSUBHNv2i32 = 2182, 2200 ARM_VSUBHNv4i16 = 2183, 2201 ARM_VSUBHNv8i8 = 2184, 2202 ARM_VSUBLsv2i64 = 2185, 2203 ARM_VSUBLsv4i32 = 2186, 2204 ARM_VSUBLsv8i16 = 2187, 2205 ARM_VSUBLuv2i64 = 2188, 2206 ARM_VSUBLuv4i32 = 2189, 2207 ARM_VSUBLuv8i16 = 2190, 2208 ARM_VSUBS = 2191, 2209 ARM_VSUBWsv2i64 = 2192, 2210 ARM_VSUBWsv4i32 = 2193, 2211 ARM_VSUBWsv8i16 = 2194, 2212 ARM_VSUBWuv2i64 = 2195, 2213 ARM_VSUBWuv4i32 = 2196, 2214 ARM_VSUBWuv8i16 = 2197, 2215 ARM_VSUBfd = 2198, 2216 ARM_VSUBfq = 2199, 2217 ARM_VSUBv16i8 = 2200, 2218 ARM_VSUBv1i64 = 2201, 2219 ARM_VSUBv2i32 = 2202, 2220 ARM_VSUBv2i64 = 2203, 2221 ARM_VSUBv4i16 = 2204, 2222 ARM_VSUBv4i32 = 2205, 2223 ARM_VSUBv8i16 = 2206, 2224 ARM_VSUBv8i8 = 2207, 2225 ARM_VSWPd = 2208, 2226 ARM_VSWPq = 2209, 2227 ARM_VTBL1 = 2210, 2228 ARM_VTBL2 = 2211, 2229 ARM_VTBL3 = 2212, 2230 ARM_VTBL3Pseudo = 2213, 2231 ARM_VTBL4 = 2214, 2232 ARM_VTBL4Pseudo = 2215, 2233 ARM_VTBX1 = 2216, 2234 ARM_VTBX2 = 2217, 2235 ARM_VTBX3 = 2218, 2236 ARM_VTBX3Pseudo = 2219, 2237 ARM_VTBX4 = 2220, 2238 ARM_VTBX4Pseudo = 2221, 2239 ARM_VTOSHD = 2222, 2240 ARM_VTOSHS = 2223, 2241 ARM_VTOSIRD = 2224, 2242 ARM_VTOSIRS = 2225, 2243 ARM_VTOSIZD = 2226, 2244 ARM_VTOSIZS = 2227, 2245 ARM_VTOSLD = 2228, 2246 ARM_VTOSLS = 2229, 2247 ARM_VTOUHD = 2230, 2248 ARM_VTOUHS = 2231, 2249 ARM_VTOUIRD = 2232, 2250 ARM_VTOUIRS = 2233, 2251 ARM_VTOUIZD = 2234, 2252 ARM_VTOUIZS = 2235, 2253 ARM_VTOULD = 2236, 2254 ARM_VTOULS = 2237, 2255 ARM_VTRNd16 = 2238, 2256 ARM_VTRNd32 = 2239, 2257 ARM_VTRNd8 = 2240, 2258 ARM_VTRNq16 = 2241, 2259 ARM_VTRNq32 = 2242, 2260 ARM_VTRNq8 = 2243, 2261 ARM_VTSTv16i8 = 2244, 2262 ARM_VTSTv2i32 = 2245, 2263 ARM_VTSTv4i16 = 2246, 2264 ARM_VTSTv4i32 = 2247, 2265 ARM_VTSTv8i16 = 2248, 2266 ARM_VTSTv8i8 = 2249, 2267 ARM_VUHTOD = 2250, 2268 ARM_VUHTOS = 2251, 2269 ARM_VUITOD = 2252, 2270 ARM_VUITOS = 2253, 2271 ARM_VULTOD = 2254, 2272 ARM_VULTOS = 2255, 2273 ARM_VUZPd16 = 2256, 2274 ARM_VUZPd8 = 2257, 2275 ARM_VUZPq16 = 2258, 2276 ARM_VUZPq32 = 2259, 2277 ARM_VUZPq8 = 2260, 2278 ARM_VZIPd16 = 2261, 2279 ARM_VZIPd8 = 2262, 2280 ARM_VZIPq16 = 2263, 2281 ARM_VZIPq32 = 2264, 2282 ARM_VZIPq8 = 2265, 2283 ARM_WIN__CHKSTK = 2266, 2284 ARM_sysLDMDA = 2267, 2285 ARM_sysLDMDA_UPD = 2268, 2286 ARM_sysLDMDB = 2269, 2287 ARM_sysLDMDB_UPD = 2270, 2288 ARM_sysLDMIA = 2271, 2289 ARM_sysLDMIA_UPD = 2272, 2290 ARM_sysLDMIB = 2273, 2291 ARM_sysLDMIB_UPD = 2274, 2292 ARM_sysSTMDA = 2275, 2293 ARM_sysSTMDA_UPD = 2276, 2294 ARM_sysSTMDB = 2277, 2295 ARM_sysSTMDB_UPD = 2278, 2296 ARM_sysSTMIA = 2279, 2297 ARM_sysSTMIA_UPD = 2280, 2298 ARM_sysSTMIB = 2281, 2299 ARM_sysSTMIB_UPD = 2282, 2300 ARM_t2ABS = 2283, 2301 ARM_t2ADCri = 2284, 2302 ARM_t2ADCrr = 2285, 2303 ARM_t2ADCrs = 2286, 2304 ARM_t2ADDSri = 2287, 2305 ARM_t2ADDSrr = 2288, 2306 ARM_t2ADDSrs = 2289, 2307 ARM_t2ADDri = 2290, 2308 ARM_t2ADDri12 = 2291, 2309 ARM_t2ADDrr = 2292, 2310 ARM_t2ADDrs = 2293, 2311 ARM_t2ADR = 2294, 2312 ARM_t2ANDri = 2295, 2313 ARM_t2ANDrr = 2296, 2314 ARM_t2ANDrs = 2297, 2315 ARM_t2ASRri = 2298, 2316 ARM_t2ASRrr = 2299, 2317 ARM_t2B = 2300, 2318 ARM_t2BFC = 2301, 2319 ARM_t2BFI = 2302, 2320 ARM_t2BICri = 2303, 2321 ARM_t2BICrr = 2304, 2322 ARM_t2BICrs = 2305, 2323 ARM_t2BR_JT = 2306, 2324 ARM_t2BXJ = 2307, 2325 ARM_t2Bcc = 2308, 2326 ARM_t2CDP = 2309, 2327 ARM_t2CDP2 = 2310, 2328 ARM_t2CLREX = 2311, 2329 ARM_t2CLZ = 2312, 2330 ARM_t2CMNri = 2313, 2331 ARM_t2CMNzrr = 2314, 2332 ARM_t2CMNzrs = 2315, 2333 ARM_t2CMPri = 2316, 2334 ARM_t2CMPrr = 2317, 2335 ARM_t2CMPrs = 2318, 2336 ARM_t2CPS1p = 2319, 2337 ARM_t2CPS2p = 2320, 2338 ARM_t2CPS3p = 2321, 2339 ARM_t2CRC32B = 2322, 2340 ARM_t2CRC32CB = 2323, 2341 ARM_t2CRC32CH = 2324, 2342 ARM_t2CRC32CW = 2325, 2343 ARM_t2CRC32H = 2326, 2344 ARM_t2CRC32W = 2327, 2345 ARM_t2DBG = 2328, 2346 ARM_t2DCPS1 = 2329, 2347 ARM_t2DCPS2 = 2330, 2348 ARM_t2DCPS3 = 2331, 2349 ARM_t2DMB = 2332, 2350 ARM_t2DSB = 2333, 2351 ARM_t2EORri = 2334, 2352 ARM_t2EORrr = 2335, 2353 ARM_t2EORrs = 2336, 2354 ARM_t2HINT = 2337, 2355 ARM_t2ISB = 2338, 2356 ARM_t2IT = 2339, 2357 ARM_t2Int_eh_sjlj_setjmp = 2340, 2358 ARM_t2Int_eh_sjlj_setjmp_nofp = 2341, 2359 ARM_t2LDA = 2342, 2360 ARM_t2LDAB = 2343, 2361 ARM_t2LDAEX = 2344, 2362 ARM_t2LDAEXB = 2345, 2363 ARM_t2LDAEXD = 2346, 2364 ARM_t2LDAEXH = 2347, 2365 ARM_t2LDAH = 2348, 2366 ARM_t2LDC2L_OFFSET = 2349, 2367 ARM_t2LDC2L_OPTION = 2350, 2368 ARM_t2LDC2L_POST = 2351, 2369 ARM_t2LDC2L_PRE = 2352, 2370 ARM_t2LDC2_OFFSET = 2353, 2371 ARM_t2LDC2_OPTION = 2354, 2372 ARM_t2LDC2_POST = 2355, 2373 ARM_t2LDC2_PRE = 2356, 2374 ARM_t2LDCL_OFFSET = 2357, 2375 ARM_t2LDCL_OPTION = 2358, 2376 ARM_t2LDCL_POST = 2359, 2377 ARM_t2LDCL_PRE = 2360, 2378 ARM_t2LDC_OFFSET = 2361, 2379 ARM_t2LDC_OPTION = 2362, 2380 ARM_t2LDC_POST = 2363, 2381 ARM_t2LDC_PRE = 2364, 2382 ARM_t2LDMDB = 2365, 2383 ARM_t2LDMDB_UPD = 2366, 2384 ARM_t2LDMIA = 2367, 2385 ARM_t2LDMIA_RET = 2368, 2386 ARM_t2LDMIA_UPD = 2369, 2387 ARM_t2LDRBT = 2370, 2388 ARM_t2LDRB_POST = 2371, 2389 ARM_t2LDRB_PRE = 2372, 2390 ARM_t2LDRBi12 = 2373, 2391 ARM_t2LDRBi8 = 2374, 2392 ARM_t2LDRBpci = 2375, 2393 ARM_t2LDRBpcrel = 2376, 2394 ARM_t2LDRBs = 2377, 2395 ARM_t2LDRD_POST = 2378, 2396 ARM_t2LDRD_PRE = 2379, 2397 ARM_t2LDRDi8 = 2380, 2398 ARM_t2LDREX = 2381, 2399 ARM_t2LDREXB = 2382, 2400 ARM_t2LDREXD = 2383, 2401 ARM_t2LDREXH = 2384, 2402 ARM_t2LDRHT = 2385, 2403 ARM_t2LDRH_POST = 2386, 2404 ARM_t2LDRH_PRE = 2387, 2405 ARM_t2LDRHi12 = 2388, 2406 ARM_t2LDRHi8 = 2389, 2407 ARM_t2LDRHpci = 2390, 2408 ARM_t2LDRHpcrel = 2391, 2409 ARM_t2LDRHs = 2392, 2410 ARM_t2LDRSBT = 2393, 2411 ARM_t2LDRSB_POST = 2394, 2412 ARM_t2LDRSB_PRE = 2395, 2413 ARM_t2LDRSBi12 = 2396, 2414 ARM_t2LDRSBi8 = 2397, 2415 ARM_t2LDRSBpci = 2398, 2416 ARM_t2LDRSBpcrel = 2399, 2417 ARM_t2LDRSBs = 2400, 2418 ARM_t2LDRSHT = 2401, 2419 ARM_t2LDRSH_POST = 2402, 2420 ARM_t2LDRSH_PRE = 2403, 2421 ARM_t2LDRSHi12 = 2404, 2422 ARM_t2LDRSHi8 = 2405, 2423 ARM_t2LDRSHpci = 2406, 2424 ARM_t2LDRSHpcrel = 2407, 2425 ARM_t2LDRSHs = 2408, 2426 ARM_t2LDRT = 2409, 2427 ARM_t2LDR_POST = 2410, 2428 ARM_t2LDR_PRE = 2411, 2429 ARM_t2LDRi12 = 2412, 2430 ARM_t2LDRi8 = 2413, 2431 ARM_t2LDRpci = 2414, 2432 ARM_t2LDRpci_pic = 2415, 2433 ARM_t2LDRpcrel = 2416, 2434 ARM_t2LDRs = 2417, 2435 ARM_t2LEApcrel = 2418, 2436 ARM_t2LEApcrelJT = 2419, 2437 ARM_t2LSLri = 2420, 2438 ARM_t2LSLrr = 2421, 2439 ARM_t2LSRri = 2422, 2440 ARM_t2LSRrr = 2423, 2441 ARM_t2MCR = 2424, 2442 ARM_t2MCR2 = 2425, 2443 ARM_t2MCRR = 2426, 2444 ARM_t2MCRR2 = 2427, 2445 ARM_t2MLA = 2428, 2446 ARM_t2MLS = 2429, 2447 ARM_t2MOVCCasr = 2430, 2448 ARM_t2MOVCCi = 2431, 2449 ARM_t2MOVCCi16 = 2432, 2450 ARM_t2MOVCCi32imm = 2433, 2451 ARM_t2MOVCClsl = 2434, 2452 ARM_t2MOVCClsr = 2435, 2453 ARM_t2MOVCCr = 2436, 2454 ARM_t2MOVCCror = 2437, 2455 ARM_t2MOVSsi = 2438, 2456 ARM_t2MOVSsr = 2439, 2457 ARM_t2MOVTi16 = 2440, 2458 ARM_t2MOVTi16_ga_pcrel = 2441, 2459 ARM_t2MOV_ga_pcrel = 2442, 2460 ARM_t2MOVi = 2443, 2461 ARM_t2MOVi16 = 2444, 2462 ARM_t2MOVi16_ga_pcrel = 2445, 2463 ARM_t2MOVi32imm = 2446, 2464 ARM_t2MOVr = 2447, 2465 ARM_t2MOVsi = 2448, 2466 ARM_t2MOVsr = 2449, 2467 ARM_t2MOVsra_flag = 2450, 2468 ARM_t2MOVsrl_flag = 2451, 2469 ARM_t2MRC = 2452, 2470 ARM_t2MRC2 = 2453, 2471 ARM_t2MRRC = 2454, 2472 ARM_t2MRRC2 = 2455, 2473 ARM_t2MRS_AR = 2456, 2474 ARM_t2MRS_M = 2457, 2475 ARM_t2MRSsys_AR = 2458, 2476 ARM_t2MSR_AR = 2459, 2477 ARM_t2MSR_M = 2460, 2478 ARM_t2MUL = 2461, 2479 ARM_t2MVNCCi = 2462, 2480 ARM_t2MVNi = 2463, 2481 ARM_t2MVNr = 2464, 2482 ARM_t2MVNs = 2465, 2483 ARM_t2ORNri = 2466, 2484 ARM_t2ORNrr = 2467, 2485 ARM_t2ORNrs = 2468, 2486 ARM_t2ORRri = 2469, 2487 ARM_t2ORRrr = 2470, 2488 ARM_t2ORRrs = 2471, 2489 ARM_t2PKHBT = 2472, 2490 ARM_t2PKHTB = 2473, 2491 ARM_t2PLDWi12 = 2474, 2492 ARM_t2PLDWi8 = 2475, 2493 ARM_t2PLDWs = 2476, 2494 ARM_t2PLDi12 = 2477, 2495 ARM_t2PLDi8 = 2478, 2496 ARM_t2PLDpci = 2479, 2497 ARM_t2PLDs = 2480, 2498 ARM_t2PLIi12 = 2481, 2499 ARM_t2PLIi8 = 2482, 2500 ARM_t2PLIpci = 2483, 2501 ARM_t2PLIs = 2484, 2502 ARM_t2QADD = 2485, 2503 ARM_t2QADD16 = 2486, 2504 ARM_t2QADD8 = 2487, 2505 ARM_t2QASX = 2488, 2506 ARM_t2QDADD = 2489, 2507 ARM_t2QDSUB = 2490, 2508 ARM_t2QSAX = 2491, 2509 ARM_t2QSUB = 2492, 2510 ARM_t2QSUB16 = 2493, 2511 ARM_t2QSUB8 = 2494, 2512 ARM_t2RBIT = 2495, 2513 ARM_t2REV = 2496, 2514 ARM_t2REV16 = 2497, 2515 ARM_t2REVSH = 2498, 2516 ARM_t2RFEDB = 2499, 2517 ARM_t2RFEDBW = 2500, 2518 ARM_t2RFEIA = 2501, 2519 ARM_t2RFEIAW = 2502, 2520 ARM_t2RORri = 2503, 2521 ARM_t2RORrr = 2504, 2522 ARM_t2RRX = 2505, 2523 ARM_t2RSBSri = 2506, 2524 ARM_t2RSBSrs = 2507, 2525 ARM_t2RSBri = 2508, 2526 ARM_t2RSBrr = 2509, 2527 ARM_t2RSBrs = 2510, 2528 ARM_t2SADD16 = 2511, 2529 ARM_t2SADD8 = 2512, 2530 ARM_t2SASX = 2513, 2531 ARM_t2SBCri = 2514, 2532 ARM_t2SBCrr = 2515, 2533 ARM_t2SBCrs = 2516, 2534 ARM_t2SBFX = 2517, 2535 ARM_t2SDIV = 2518, 2536 ARM_t2SEL = 2519, 2537 ARM_t2SHADD16 = 2520, 2538 ARM_t2SHADD8 = 2521, 2539 ARM_t2SHASX = 2522, 2540 ARM_t2SHSAX = 2523, 2541 ARM_t2SHSUB16 = 2524, 2542 ARM_t2SHSUB8 = 2525, 2543 ARM_t2SMC = 2526, 2544 ARM_t2SMLABB = 2527, 2545 ARM_t2SMLABT = 2528, 2546 ARM_t2SMLAD = 2529, 2547 ARM_t2SMLADX = 2530, 2548 ARM_t2SMLAL = 2531, 2549 ARM_t2SMLALBB = 2532, 2550 ARM_t2SMLALBT = 2533, 2551 ARM_t2SMLALD = 2534, 2552 ARM_t2SMLALDX = 2535, 2553 ARM_t2SMLALTB = 2536, 2554 ARM_t2SMLALTT = 2537, 2555 ARM_t2SMLATB = 2538, 2556 ARM_t2SMLATT = 2539, 2557 ARM_t2SMLAWB = 2540, 2558 ARM_t2SMLAWT = 2541, 2559 ARM_t2SMLSD = 2542, 2560 ARM_t2SMLSDX = 2543, 2561 ARM_t2SMLSLD = 2544, 2562 ARM_t2SMLSLDX = 2545, 2563 ARM_t2SMMLA = 2546, 2564 ARM_t2SMMLAR = 2547, 2565 ARM_t2SMMLS = 2548, 2566 ARM_t2SMMLSR = 2549, 2567 ARM_t2SMMUL = 2550, 2568 ARM_t2SMMULR = 2551, 2569 ARM_t2SMUAD = 2552, 2570 ARM_t2SMUADX = 2553, 2571 ARM_t2SMULBB = 2554, 2572 ARM_t2SMULBT = 2555, 2573 ARM_t2SMULL = 2556, 2574 ARM_t2SMULTB = 2557, 2575 ARM_t2SMULTT = 2558, 2576 ARM_t2SMULWB = 2559, 2577 ARM_t2SMULWT = 2560, 2578 ARM_t2SMUSD = 2561, 2579 ARM_t2SMUSDX = 2562, 2580 ARM_t2SRSDB = 2563, 2581 ARM_t2SRSDB_UPD = 2564, 2582 ARM_t2SRSIA = 2565, 2583 ARM_t2SRSIA_UPD = 2566, 2584 ARM_t2SSAT = 2567, 2585 ARM_t2SSAT16 = 2568, 2586 ARM_t2SSAX = 2569, 2587 ARM_t2SSUB16 = 2570, 2588 ARM_t2SSUB8 = 2571, 2589 ARM_t2STC2L_OFFSET = 2572, 2590 ARM_t2STC2L_OPTION = 2573, 2591 ARM_t2STC2L_POST = 2574, 2592 ARM_t2STC2L_PRE = 2575, 2593 ARM_t2STC2_OFFSET = 2576, 2594 ARM_t2STC2_OPTION = 2577, 2595 ARM_t2STC2_POST = 2578, 2596 ARM_t2STC2_PRE = 2579, 2597 ARM_t2STCL_OFFSET = 2580, 2598 ARM_t2STCL_OPTION = 2581, 2599 ARM_t2STCL_POST = 2582, 2600 ARM_t2STCL_PRE = 2583, 2601 ARM_t2STC_OFFSET = 2584, 2602 ARM_t2STC_OPTION = 2585, 2603 ARM_t2STC_POST = 2586, 2604 ARM_t2STC_PRE = 2587, 2605 ARM_t2STL = 2588, 2606 ARM_t2STLB = 2589, 2607 ARM_t2STLEX = 2590, 2608 ARM_t2STLEXB = 2591, 2609 ARM_t2STLEXD = 2592, 2610 ARM_t2STLEXH = 2593, 2611 ARM_t2STLH = 2594, 2612 ARM_t2STMDB = 2595, 2613 ARM_t2STMDB_UPD = 2596, 2614 ARM_t2STMIA = 2597, 2615 ARM_t2STMIA_UPD = 2598, 2616 ARM_t2STRBT = 2599, 2617 ARM_t2STRB_POST = 2600, 2618 ARM_t2STRB_PRE = 2601, 2619 ARM_t2STRB_preidx = 2602, 2620 ARM_t2STRBi12 = 2603, 2621 ARM_t2STRBi8 = 2604, 2622 ARM_t2STRBs = 2605, 2623 ARM_t2STRD_POST = 2606, 2624 ARM_t2STRD_PRE = 2607, 2625 ARM_t2STRDi8 = 2608, 2626 ARM_t2STREX = 2609, 2627 ARM_t2STREXB = 2610, 2628 ARM_t2STREXD = 2611, 2629 ARM_t2STREXH = 2612, 2630 ARM_t2STRHT = 2613, 2631 ARM_t2STRH_POST = 2614, 2632 ARM_t2STRH_PRE = 2615, 2633 ARM_t2STRH_preidx = 2616, 2634 ARM_t2STRHi12 = 2617, 2635 ARM_t2STRHi8 = 2618, 2636 ARM_t2STRHs = 2619, 2637 ARM_t2STRT = 2620, 2638 ARM_t2STR_POST = 2621, 2639 ARM_t2STR_PRE = 2622, 2640 ARM_t2STR_preidx = 2623, 2641 ARM_t2STRi12 = 2624, 2642 ARM_t2STRi8 = 2625, 2643 ARM_t2STRs = 2626, 2644 ARM_t2SUBS_PC_LR = 2627, 2645 ARM_t2SUBSri = 2628, 2646 ARM_t2SUBSrr = 2629, 2647 ARM_t2SUBSrs = 2630, 2648 ARM_t2SUBri = 2631, 2649 ARM_t2SUBri12 = 2632, 2650 ARM_t2SUBrr = 2633, 2651 ARM_t2SUBrs = 2634, 2652 ARM_t2SXTAB = 2635, 2653 ARM_t2SXTAB16 = 2636, 2654 ARM_t2SXTAH = 2637, 2655 ARM_t2SXTB = 2638, 2656 ARM_t2SXTB16 = 2639, 2657 ARM_t2SXTH = 2640, 2658 ARM_t2TBB = 2641, 2659 ARM_t2TBB_JT = 2642, 2660 ARM_t2TBH = 2643, 2661 ARM_t2TBH_JT = 2644, 2662 ARM_t2TEQri = 2645, 2663 ARM_t2TEQrr = 2646, 2664 ARM_t2TEQrs = 2647, 2665 ARM_t2TSTri = 2648, 2666 ARM_t2TSTrr = 2649, 2667 ARM_t2TSTrs = 2650, 2668 ARM_t2UADD16 = 2651, 2669 ARM_t2UADD8 = 2652, 2670 ARM_t2UASX = 2653, 2671 ARM_t2UBFX = 2654, 2672 ARM_t2UDF = 2655, 2673 ARM_t2UDIV = 2656, 2674 ARM_t2UHADD16 = 2657, 2675 ARM_t2UHADD8 = 2658, 2676 ARM_t2UHASX = 2659, 2677 ARM_t2UHSAX = 2660, 2678 ARM_t2UHSUB16 = 2661, 2679 ARM_t2UHSUB8 = 2662, 2680 ARM_t2UMAAL = 2663, 2681 ARM_t2UMLAL = 2664, 2682 ARM_t2UMULL = 2665, 2683 ARM_t2UQADD16 = 2666, 2684 ARM_t2UQADD8 = 2667, 2685 ARM_t2UQASX = 2668, 2686 ARM_t2UQSAX = 2669, 2687 ARM_t2UQSUB16 = 2670, 2688 ARM_t2UQSUB8 = 2671, 2689 ARM_t2USAD8 = 2672, 2690 ARM_t2USADA8 = 2673, 2691 ARM_t2USAT = 2674, 2692 ARM_t2USAT16 = 2675, 2693 ARM_t2USAX = 2676, 2694 ARM_t2USUB16 = 2677, 2695 ARM_t2USUB8 = 2678, 2696 ARM_t2UXTAB = 2679, 2697 ARM_t2UXTAB16 = 2680, 2698 ARM_t2UXTAH = 2681, 2699 ARM_t2UXTB = 2682, 2700 ARM_t2UXTB16 = 2683, 2701 ARM_t2UXTH = 2684, 2702 ARM_tADC = 2685, 2703 ARM_tADDhirr = 2686, 2704 ARM_tADDi3 = 2687, 2705 ARM_tADDi8 = 2688, 2706 ARM_tADDrSP = 2689, 2707 ARM_tADDrSPi = 2690, 2708 ARM_tADDrr = 2691, 2709 ARM_tADDspi = 2692, 2710 ARM_tADDspr = 2693, 2711 ARM_tADJCALLSTACKDOWN = 2694, 2712 ARM_tADJCALLSTACKUP = 2695, 2713 ARM_tADR = 2696, 2714 ARM_tAND = 2697, 2715 ARM_tASRri = 2698, 2716 ARM_tASRrr = 2699, 2717 ARM_tB = 2700, 2718 ARM_tBIC = 2701, 2719 ARM_tBKPT = 2702, 2720 ARM_tBL = 2703, 2721 ARM_tBLXi = 2704, 2722 ARM_tBLXr = 2705, 2723 ARM_tBRIND = 2706, 2724 ARM_tBR_JTr = 2707, 2725 ARM_tBX = 2708, 2726 ARM_tBX_CALL = 2709, 2727 ARM_tBX_RET = 2710, 2728 ARM_tBX_RET_vararg = 2711, 2729 ARM_tBcc = 2712, 2730 ARM_tBfar = 2713, 2731 ARM_tCBNZ = 2714, 2732 ARM_tCBZ = 2715, 2733 ARM_tCMNz = 2716, 2734 ARM_tCMPhir = 2717, 2735 ARM_tCMPi8 = 2718, 2736 ARM_tCMPr = 2719, 2737 ARM_tCPS = 2720, 2738 ARM_tEOR = 2721, 2739 ARM_tHINT = 2722, 2740 ARM_tHLT = 2723, 2741 ARM_tInt_eh_sjlj_longjmp = 2724, 2742 ARM_tInt_eh_sjlj_setjmp = 2725, 2743 ARM_tLDMIA = 2726, 2744 ARM_tLDMIA_UPD = 2727, 2745 ARM_tLDRBi = 2728, 2746 ARM_tLDRBr = 2729, 2747 ARM_tLDRHi = 2730, 2748 ARM_tLDRHr = 2731, 2749 ARM_tLDRLIT_ga_abs = 2732, 2750 ARM_tLDRLIT_ga_pcrel = 2733, 2751 ARM_tLDRSB = 2734, 2752 ARM_tLDRSH = 2735, 2753 ARM_tLDRi = 2736, 2754 ARM_tLDRpci = 2737, 2755 ARM_tLDRpci_pic = 2738, 2756 ARM_tLDRr = 2739, 2757 ARM_tLDRspi = 2740, 2758 ARM_tLEApcrel = 2741, 2759 ARM_tLEApcrelJT = 2742, 2760 ARM_tLSLri = 2743, 2761 ARM_tLSLrr = 2744, 2762 ARM_tLSRri = 2745, 2763 ARM_tLSRrr = 2746, 2764 ARM_tMOVCCr_pseudo = 2747, 2765 ARM_tMOVSr = 2748, 2766 ARM_tMOVi8 = 2749, 2767 ARM_tMOVr = 2750, 2768 ARM_tMUL = 2751, 2769 ARM_tMVN = 2752, 2770 ARM_tORR = 2753, 2771 ARM_tPICADD = 2754, 2772 ARM_tPOP = 2755, 2773 ARM_tPOP_RET = 2756, 2774 ARM_tPUSH = 2757, 2775 ARM_tREV = 2758, 2776 ARM_tREV16 = 2759, 2777 ARM_tREVSH = 2760, 2778 ARM_tROR = 2761, 2779 ARM_tRSB = 2762, 2780 ARM_tSBC = 2763, 2781 ARM_tSETEND = 2764, 2782 ARM_tSTMIA_UPD = 2765, 2783 ARM_tSTRBi = 2766, 2784 ARM_tSTRBr = 2767, 2785 ARM_tSTRHi = 2768, 2786 ARM_tSTRHr = 2769, 2787 ARM_tSTRi = 2770, 2788 ARM_tSTRr = 2771, 2789 ARM_tSTRspi = 2772, 2790 ARM_tSUBi3 = 2773, 2791 ARM_tSUBi8 = 2774, 2792 ARM_tSUBrr = 2775, 2793 ARM_tSUBspi = 2776, 2794 ARM_tSVC = 2777, 2795 ARM_tSXTB = 2778, 2796 ARM_tSXTH = 2779, 2797 ARM_tTAILJMPd = 2780, 2798 ARM_tTAILJMPdND = 2781, 2799 ARM_tTAILJMPr = 2782, 2800 ARM_tTPsoft = 2783, 2801 ARM_tTRAP = 2784, 2802 ARM_tTST = 2785, 2803 ARM_tUDF = 2786, 2804 ARM_tUXTB = 2787, 2805 ARM_tUXTH = 2788, 2806 ARM_INSTRUCTION_LIST_END = 2789 2807}; 2808 2809#endif // GET_INSTRINFO_ENUM 2810 2811 2812#ifdef GET_INSTRINFO_MC_DESC 2813#undef GET_INSTRINFO_MC_DESC 2814 2815#define nullptr 0 2816 2817#define ImplicitList1 0 2818#define ImplicitList2 0 2819#define ImplicitList3 0 2820#define ImplicitList4 0 2821#define ImplicitList5 0 2822#define ImplicitList6 0 2823#define ImplicitList7 0 2824#define ImplicitList8 0 2825#define ImplicitList9 0 2826#define ImplicitList10 0 2827#define ImplicitList11 0 2828#define ImplicitList12 0 2829#define ImplicitList13 0 2830#define ImplicitList14 0 2831#define ImplicitList15 0 2832 2833static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2834static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2835static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2836static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2837static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2838static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2839static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2840static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2841static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, }; 2842static MCOperandInfo OperandInfo11[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2843static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2844static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2845static MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2846static MCOperandInfo OperandInfo15[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2847static MCOperandInfo OperandInfo16[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2848static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2849static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2850static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2851static MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2852static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2853static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2854static MCOperandInfo OperandInfo23[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2855static MCOperandInfo OperandInfo24[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2856static MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2857static MCOperandInfo OperandInfo26[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2858static MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; 2859static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; 2860static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; 2861static MCOperandInfo OperandInfo30[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2862static MCOperandInfo OperandInfo31[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2863static MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2864static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2865static MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2866static MCOperandInfo OperandInfo35[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2867static MCOperandInfo OperandInfo36[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2868static MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2869static MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2870static MCOperandInfo OperandInfo39[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2871static MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2872static MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2873static MCOperandInfo OperandInfo42[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2874static MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2875static MCOperandInfo OperandInfo44[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2876static MCOperandInfo OperandInfo45[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2877static MCOperandInfo OperandInfo46[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2878static MCOperandInfo OperandInfo47[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2879static MCOperandInfo OperandInfo48[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2880static MCOperandInfo OperandInfo49[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2881static MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2882static MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2883static MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2884static MCOperandInfo OperandInfo53[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2885static MCOperandInfo OperandInfo54[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2886static MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2887static MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2888static MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2889static MCOperandInfo OperandInfo58[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2890static MCOperandInfo OperandInfo59[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2891static MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2892static MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2893static MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2894static MCOperandInfo OperandInfo63[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2895static MCOperandInfo OperandInfo64[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2896static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 2897static MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2898static MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2899static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2900static MCOperandInfo OperandInfo69[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2901static MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2902static MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2903static MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2904static MCOperandInfo OperandInfo73[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2905static MCOperandInfo OperandInfo74[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2906static MCOperandInfo OperandInfo75[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2907static MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2908static MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2909static MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2910static MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2911static MCOperandInfo OperandInfo80[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2912static MCOperandInfo OperandInfo81[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2913static MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2914static MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2915static MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2916static MCOperandInfo OperandInfo85[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2917static MCOperandInfo OperandInfo86[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2918static MCOperandInfo OperandInfo87[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2919static MCOperandInfo OperandInfo88[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2920static MCOperandInfo OperandInfo89[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2921static MCOperandInfo OperandInfo90[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2922static MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2923static MCOperandInfo OperandInfo92[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2924static MCOperandInfo OperandInfo93[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2925static MCOperandInfo OperandInfo94[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2926static MCOperandInfo OperandInfo95[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2927static MCOperandInfo OperandInfo96[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2928static MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 2929static MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2930static MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2931static MCOperandInfo OperandInfo100[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2932static MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2933static MCOperandInfo OperandInfo102[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2934static MCOperandInfo OperandInfo103[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2935static MCOperandInfo OperandInfo104[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2936static MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2937static MCOperandInfo OperandInfo106[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 2938static MCOperandInfo OperandInfo107[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2939static MCOperandInfo OperandInfo108[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2940static MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2941static MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2942static MCOperandInfo OperandInfo111[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2943static MCOperandInfo OperandInfo112[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2944static MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2945static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2946static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2947static MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2948static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2949static MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2950static MCOperandInfo OperandInfo119[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2951static MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2952static MCOperandInfo OperandInfo121[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2953static MCOperandInfo OperandInfo122[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2954static MCOperandInfo OperandInfo123[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2955static MCOperandInfo OperandInfo124[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2956static MCOperandInfo OperandInfo125[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2957static MCOperandInfo OperandInfo126[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2958static MCOperandInfo OperandInfo127[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2959static MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2960static MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2961static MCOperandInfo OperandInfo130[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2962static MCOperandInfo OperandInfo131[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2963static MCOperandInfo OperandInfo132[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2964static MCOperandInfo OperandInfo133[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2965static MCOperandInfo OperandInfo134[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2966static MCOperandInfo OperandInfo135[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2967static MCOperandInfo OperandInfo136[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2968static MCOperandInfo OperandInfo137[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2969static MCOperandInfo OperandInfo138[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2970static MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2971static MCOperandInfo OperandInfo140[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2972static MCOperandInfo OperandInfo141[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 2973static MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2974static MCOperandInfo OperandInfo143[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2975static MCOperandInfo OperandInfo144[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2976static MCOperandInfo OperandInfo145[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2977static MCOperandInfo OperandInfo146[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2978static MCOperandInfo OperandInfo147[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2979static MCOperandInfo OperandInfo148[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2980static MCOperandInfo OperandInfo149[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2981static MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2982static MCOperandInfo OperandInfo151[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2983static MCOperandInfo OperandInfo152[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2984static MCOperandInfo OperandInfo153[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2985static MCOperandInfo OperandInfo154[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2986static MCOperandInfo OperandInfo155[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2987static MCOperandInfo OperandInfo156[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2988static MCOperandInfo OperandInfo157[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2989static MCOperandInfo OperandInfo158[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2990static MCOperandInfo OperandInfo159[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2991static MCOperandInfo OperandInfo160[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2992static MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2993static MCOperandInfo OperandInfo162[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2994static MCOperandInfo OperandInfo163[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2995static MCOperandInfo OperandInfo164[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2996static MCOperandInfo OperandInfo165[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2997static MCOperandInfo OperandInfo166[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2998static MCOperandInfo OperandInfo167[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 2999static MCOperandInfo OperandInfo168[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3000static MCOperandInfo OperandInfo169[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3001static MCOperandInfo OperandInfo170[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3002static MCOperandInfo OperandInfo171[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3003static MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3004static MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3005static MCOperandInfo OperandInfo174[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3006static MCOperandInfo OperandInfo175[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3007static MCOperandInfo OperandInfo176[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3008static MCOperandInfo OperandInfo177[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3009static MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3010static MCOperandInfo OperandInfo179[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3011static MCOperandInfo OperandInfo180[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3012static MCOperandInfo OperandInfo181[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3013static MCOperandInfo OperandInfo182[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3014static MCOperandInfo OperandInfo183[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3015static MCOperandInfo OperandInfo184[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3016static MCOperandInfo OperandInfo185[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3017static MCOperandInfo OperandInfo186[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3018static MCOperandInfo OperandInfo187[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3019static MCOperandInfo OperandInfo188[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3020static MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3021static MCOperandInfo OperandInfo190[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3022static MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3023static MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3024static MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3025static MCOperandInfo OperandInfo194[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3026static MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3027static MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3028static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3029static MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3030static MCOperandInfo OperandInfo199[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3031static MCOperandInfo OperandInfo200[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3032static MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3033static MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3034static MCOperandInfo OperandInfo203[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3035static MCOperandInfo OperandInfo204[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3036static MCOperandInfo OperandInfo205[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3037static MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3038static MCOperandInfo OperandInfo207[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3039static MCOperandInfo OperandInfo208[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3040static MCOperandInfo OperandInfo209[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3041static MCOperandInfo OperandInfo210[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3042static MCOperandInfo OperandInfo211[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3043static MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3044static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3045static MCOperandInfo OperandInfo214[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3046static MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3047static MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3048static MCOperandInfo OperandInfo217[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3049static MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3050static MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3051static MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3052static MCOperandInfo OperandInfo221[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3053static MCOperandInfo OperandInfo222[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3054static MCOperandInfo OperandInfo223[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3055static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3056static MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3057static MCOperandInfo OperandInfo226[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3058static MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3059static MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3060static MCOperandInfo OperandInfo229[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3061static MCOperandInfo OperandInfo230[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3062static MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3063static MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3064static MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3065static MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3066static MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3067static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3068static MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3069static MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3070static MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3071static MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3072static MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3073static MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3074static MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3075static MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3076static MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3077static MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3078static MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3079static MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3080static MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3081static MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3082static MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3083static MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3084static MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3085static MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3086static MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3087static MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3088static MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3089static MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3090static MCOperandInfo OperandInfo259[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3091static MCOperandInfo OperandInfo260[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3092static MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3093static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3094static MCOperandInfo OperandInfo263[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3095static MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3096static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3097static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3098static MCOperandInfo OperandInfo267[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3099static MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3100static MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3101static MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3102static MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3103static MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3104static MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3105static MCOperandInfo OperandInfo274[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3106static MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3107static MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3108static MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3109static MCOperandInfo OperandInfo278[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3110static MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3111static MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3112static MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3113static MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3114static MCOperandInfo OperandInfo283[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3115static MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3116static MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3117static MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3118static MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3119static MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3120static MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3121static MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3122static MCOperandInfo OperandInfo291[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3123static MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3124static MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3125static MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3126static MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 3127static MCOperandInfo OperandInfo296[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3128static MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3129static MCOperandInfo OperandInfo298[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3130static MCOperandInfo OperandInfo299[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3131static MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3132static MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3133static MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3134static MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3135static MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3136static MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 3137static MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 3138static MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3139static MCOperandInfo OperandInfo308[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3140static MCOperandInfo OperandInfo309[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3141static MCOperandInfo OperandInfo310[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3142static MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3143static MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; 3144static MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3145static MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3146static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3147static MCOperandInfo OperandInfo316[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3148static MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3149static MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3150static MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3151static MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3152static MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3153static MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3154static MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3155static MCOperandInfo OperandInfo324[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3156static MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3157static MCOperandInfo OperandInfo326[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3158static MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3159static MCOperandInfo OperandInfo328[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3160static MCOperandInfo OperandInfo329[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3161static MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3162static MCOperandInfo OperandInfo331[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3163static MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3164static MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3165static MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3166static MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3167static MCOperandInfo OperandInfo336[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3168static MCOperandInfo OperandInfo337[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3169static MCOperandInfo OperandInfo338[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3170static MCOperandInfo OperandInfo339[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3171static MCOperandInfo OperandInfo340[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; 3172static MCOperandInfo OperandInfo341[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; 3173static MCOperandInfo OperandInfo342[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 3174static MCOperandInfo OperandInfo343[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3175static MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; 3176static MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3177static MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3178static MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 3179static MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3180static MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3181static MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; 3182static MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3183static MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3184static MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3185static MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3186static MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3187static MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3188static MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; 3189static MCOperandInfo OperandInfo358[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 3190static MCOperandInfo OperandInfo359[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 3191static MCOperandInfo OperandInfo360[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; 3192 3193static MCInstrDesc ARMInsts[] = { 3194 { 0, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #0 = PHI 3195 { 1, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #1 = INLINEASM 3196 { 2, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #2 = CFI_INSTRUCTION 3197 { 3, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #3 = EH_LABEL 3198 { 4, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #4 = GC_LABEL 3199 { 5, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #5 = KILL 3200 { 6, 3, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #6 = EXTRACT_SUBREG 3201 { 7, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4,0,nullptr }, // Inst #7 = INSERT_SUBREG 3202 { 8, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #8 = IMPLICIT_DEF 3203 { 9, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6,0,nullptr }, // Inst #9 = SUBREG_TO_REG 3204 { 10, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #10 = COPY_TO_REGCLASS 3205 { 11, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #11 = DBG_VALUE 3206 { 12, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #12 = REG_SEQUENCE 3207 { 13, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #13 = COPY 3208 { 14, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #14 = BUNDLE 3209 { 15, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #15 = LIFETIME_START 3210 { 16, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #16 = LIFETIME_END 3211 { 17, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8,0,nullptr }, // Inst #17 = STACKMAP 3212 { 18, 6, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9,0,nullptr }, // Inst #18 = PATCHPOINT 3213 { 19, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10,0,nullptr }, // Inst #19 = LOAD_STACK_GUARD 3214 { 20, 2, 1, 590, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo11,0,nullptr }, // Inst #20 = ABS 3215 { 21, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #21 = ADCri 3216 { 22, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #22 = ADCrr 3217 { 23, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #23 = ADCrsi 3218 { 24, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #24 = ADCrsr 3219 { 25, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #25 = ADDSri 3220 { 26, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #26 = ADDSrr 3221 { 27, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #27 = ADDSrsi 3222 { 28, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #28 = ADDSrsr 3223 { 29, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #29 = ADDri 3224 { 30, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #30 = ADDrr 3225 { 31, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #31 = ADDrsi 3226 { 32, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #32 = ADDrsr 3227 { 33, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo21,0,nullptr }, // Inst #33 = ADJCALLSTACKDOWN 3228 { 34, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo22,0,nullptr }, // Inst #34 = ADJCALLSTACKUP 3229 { 35, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #35 = ADR 3230 { 36, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #36 = AESD 3231 { 37, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #37 = AESE 3232 { 38, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #38 = AESIMC 3233 { 39, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #39 = AESMC 3234 { 40, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #40 = ANDri 3235 { 41, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #41 = ANDrr 3236 { 42, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #42 = ANDrsi 3237 { 43, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #43 = ANDrsr 3238 { 44, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #44 = ASRi 3239 { 45, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #45 = ASRr 3240 { 46, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #46 = B 3241 { 47, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28,0,nullptr }, // Inst #47 = BCCZi64 3242 { 48, 6, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo29,0,nullptr }, // Inst #48 = BCCi64 3243 { 49, 5, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #49 = BFC 3244 { 50, 6, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #50 = BFI 3245 { 51, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #51 = BICri 3246 { 52, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #52 = BICrr 3247 { 53, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #53 = BICrsi 3248 { 54, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #54 = BICrsr 3249 { 55, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #55 = BKPT 3250 { 56, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo27,0,nullptr }, // Inst #56 = BL 3251 { 57, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo32,0,nullptr }, // Inst #57 = BLX 3252 { 58, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo33,0,nullptr }, // Inst #58 = BLX_pred 3253 { 59, 1, 0, 13, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #59 = BLXi 3254 { 60, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo34,0,nullptr }, // Inst #60 = BL_pred 3255 { 61, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo27,0,nullptr }, // Inst #61 = BMOVPCB_CALL 3256 { 62, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #62 = BMOVPCRX_CALL 3257 { 63, 4, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo36,0,nullptr }, // Inst #63 = BR_JTadd 3258 { 64, 5, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #64 = BR_JTm 3259 { 65, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #65 = BR_JTr 3260 { 66, 1, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #66 = BX 3261 { 67, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #67 = BXJ 3262 { 68, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #68 = BX_CALL 3263 { 69, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #69 = BX_RET 3264 { 70, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #70 = BX_pred 3265 { 71, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #71 = Bcc 3266 { 72, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #72 = CDP 3267 { 73, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #73 = CDP2 3268 { 74, 0, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #74 = CLREX 3269 { 75, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #75 = CLZ 3270 { 76, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #76 = CMNri 3271 { 77, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #77 = CMNzrr 3272 { 78, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #78 = CMNzrsi 3273 { 79, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #79 = CMNzrsr 3274 { 80, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #80 = CMPri 3275 { 81, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #81 = CMPrr 3276 { 82, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #82 = CMPrsi 3277 { 83, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #83 = CMPrsr 3278 { 84, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #84 = CONSTPOOL_ENTRY 3279 { 85, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36,0,nullptr }, // Inst #85 = COPY_STRUCT_BYVAL_I32 3280 { 86, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #86 = CPS1p 3281 { 87, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #87 = CPS2p 3282 { 88, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo45,0,nullptr }, // Inst #88 = CPS3p 3283 { 89, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #89 = CRC32B 3284 { 90, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #90 = CRC32CB 3285 { 91, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #91 = CRC32CH 3286 { 92, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #92 = CRC32CW 3287 { 93, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #93 = CRC32H 3288 { 94, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #94 = CRC32W 3289 { 95, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #95 = DBG 3290 { 96, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #96 = DMB 3291 { 97, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #97 = DSB 3292 { 98, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #98 = EORri 3293 { 99, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #99 = EORrr 3294 { 100, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #100 = EORrsi 3295 { 101, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #101 = EORrsr 3296 { 102, 4, 1, 487, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #102 = FCONSTD 3297 { 103, 4, 1, 488, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #103 = FCONSTS 3298 { 104, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #104 = FLDMXDB_UPD 3299 { 105, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #105 = FLDMXIA 3300 { 106, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #106 = FLDMXIA_UPD 3301 { 107, 2, 0, 507, 4, 0|(1<<MCID_Predicable), 0x8c00ULL, ImplicitList4, ImplicitList1, OperandInfo39,0,nullptr }, // Inst #107 = FMSTAT 3302 { 108, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #108 = FSTMXDB_UPD 3303 { 109, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #109 = FSTMXIA 3304 { 110, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #110 = FSTMXIA_UPD 3305 { 111, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #111 = HINT 3306 { 112, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #112 = HLT 3307 { 113, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #113 = ISB 3308 { 114, 2, 0, 377, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7,0,0 }, // Inst #114 = ITasm 3309 { 115, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #115 = Int_eh_sjlj_dispatchsetup 3310 { 116, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo11,0,nullptr }, // Inst #116 = Int_eh_sjlj_longjmp 3311 { 117, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo11,0,nullptr }, // Inst #117 = Int_eh_sjlj_setjmp 3312 { 118, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo11,0,nullptr }, // Inst #118 = Int_eh_sjlj_setjmp_nofp 3313 { 119, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #119 = LDA 3314 { 120, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #120 = LDAB 3315 { 121, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #121 = LDAEX 3316 { 122, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #122 = LDAEXB 3317 { 123, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #123 = LDAEXD 3318 { 124, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #124 = LDAEXH 3319 { 125, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #125 = LDAH 3320 { 126, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #126 = LDC2L_OFFSET 3321 { 127, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #127 = LDC2L_OPTION 3322 { 128, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #128 = LDC2L_POST 3323 { 129, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #129 = LDC2L_PRE 3324 { 130, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #130 = LDC2_OFFSET 3325 { 131, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #131 = LDC2_OPTION 3326 { 132, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #132 = LDC2_POST 3327 { 133, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #133 = LDC2_PRE 3328 { 134, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #134 = LDCL_OFFSET 3329 { 135, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #135 = LDCL_OPTION 3330 { 136, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #136 = LDCL_POST 3331 { 137, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #137 = LDCL_PRE 3332 { 138, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #138 = LDC_OFFSET 3333 { 139, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #139 = LDC_OPTION 3334 { 140, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #140 = LDC_POST 3335 { 141, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #141 = LDC_PRE 3336 { 142, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #142 = LDMDA 3337 { 143, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #143 = LDMDA_UPD 3338 { 144, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #144 = LDMDB 3339 { 145, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #145 = LDMDB_UPD 3340 { 146, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #146 = LDMIA 3341 { 147, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #147 = LDMIA_RET 3342 { 148, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #148 = LDMIA_UPD 3343 { 149, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #149 = LDMIB 3344 { 150, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #150 = LDMIB_UPD 3345 { 151, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #151 = LDRBT_POST 3346 { 152, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #152 = LDRBT_POST_IMM 3347 { 153, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #153 = LDRBT_POST_REG 3348 { 154, 7, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #154 = LDRB_POST_IMM 3349 { 155, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #155 = LDRB_POST_REG 3350 { 156, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #156 = LDRB_PRE_IMM 3351 { 157, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #157 = LDRB_PRE_REG 3352 { 158, 5, 1, 325, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #158 = LDRBi12 3353 { 159, 6, 1, 326, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #159 = LDRBrs 3354 { 160, 7, 2, 350, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #160 = LDRD 3355 { 161, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x443ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #161 = LDRD_POST 3356 { 162, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x423ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #162 = LDRD_PRE 3357 { 163, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #163 = LDREX 3358 { 164, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #164 = LDREXB 3359 { 165, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #165 = LDREXD 3360 { 166, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #166 = LDREXH 3361 { 167, 6, 1, 335, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #167 = LDRH 3362 { 168, 6, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #168 = LDRHTi 3363 { 169, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #169 = LDRHTr 3364 { 170, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #170 = LDRH_POST 3365 { 171, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #171 = LDRH_PRE 3366 { 172, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #172 = LDRLIT_ga_abs 3367 { 173, 2, 1, 34, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #173 = LDRLIT_ga_pcrel 3368 { 174, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #174 = LDRLIT_ga_pcrel_ldr 3369 { 175, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #175 = LDRSB 3370 { 176, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #176 = LDRSBTi 3371 { 177, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #177 = LDRSBTr 3372 { 178, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #178 = LDRSB_POST 3373 { 179, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #179 = LDRSB_PRE 3374 { 180, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #180 = LDRSH 3375 { 181, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #181 = LDRSHTi 3376 { 182, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #182 = LDRSHTr 3377 { 183, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #183 = LDRSH_POST 3378 { 184, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #184 = LDRSH_PRE 3379 { 185, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #185 = LDRT_POST 3380 { 186, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #186 = LDRT_POST_IMM 3381 { 187, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #187 = LDRT_POST_REG 3382 { 188, 7, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #188 = LDR_POST_IMM 3383 { 189, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #189 = LDR_POST_REG 3384 { 190, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #190 = LDR_PRE_IMM 3385 { 191, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #191 = LDR_PRE_REG 3386 { 192, 5, 1, 336, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #192 = LDRcp 3387 { 193, 5, 1, 328, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #193 = LDRi12 3388 { 194, 6, 1, 287, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #194 = LDRrs 3389 { 195, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo67,0,nullptr }, // Inst #195 = LEApcrel 3390 { 196, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68,0,nullptr }, // Inst #196 = LEApcrelJT 3391 { 197, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #197 = LSLi 3392 { 198, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #198 = LSLr 3393 { 199, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #199 = LSRi 3394 { 200, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #200 = LSRr 3395 { 201, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo69,0,0 }, // Inst #201 = MCR 3396 { 202, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo70,0,nullptr }, // Inst #202 = MCR2 3397 { 203, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo71,0,nullptr }, // Inst #203 = MCRR 3398 { 204, 5, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #204 = MCRR2 3399 { 205, 7, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #205 = MLA 3400 { 206, 7, 1, 279, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74,0,nullptr }, // Inst #206 = MLAv5 3401 { 207, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #207 = MLS 3402 { 208, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #208 = MOVCCi 3403 { 209, 5, 1, 41, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #209 = MOVCCi16 3404 { 210, 5, 1, 273, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #210 = MOVCCi32imm 3405 { 211, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #211 = MOVCCr 3406 { 212, 6, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo78,0,nullptr }, // Inst #212 = MOVCCsi 3407 { 213, 7, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo79,0,nullptr }, // Inst #213 = MOVCCsr 3408 { 214, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #214 = MOVPCLR 3409 { 215, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #215 = MOVPCRX 3410 { 216, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0x2201ULL, nullptr, nullptr, OperandInfo80,0,nullptr }, // Inst #216 = MOVTi16 3411 { 217, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81,0,nullptr }, // Inst #217 = MOVTi16_ga_pcrel 3412 { 218, 2, 1, 275, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #218 = MOV_ga_pcrel 3413 { 219, 2, 1, 276, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #219 = MOV_ga_pcrel_ldr 3414 { 220, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #220 = MOVi 3415 { 221, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #221 = MOVi16 3416 { 222, 3, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #222 = MOVi16_ga_pcrel 3417 { 223, 2, 1, 274, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #223 = MOVi32imm 3418 { 224, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #224 = MOVr 3419 { 225, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #225 = MOVr_TC 3420 { 226, 6, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #226 = MOVsi 3421 { 227, 7, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #227 = MOVsr 3422 { 228, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo11,0,nullptr }, // Inst #228 = MOVsra_flag 3423 { 229, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo11,0,nullptr }, // Inst #229 = MOVsrl_flag 3424 { 230, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #230 = MRC 3425 { 231, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #231 = MRC2 3426 { 232, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo71,0,nullptr }, // Inst #232 = MRRC 3427 { 233, 5, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #233 = MRRC2 3428 { 234, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo90,0,nullptr }, // Inst #234 = MRS 3429 { 235, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo90,0,nullptr }, // Inst #235 = MRSsys 3430 { 236, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo91,0,nullptr }, // Inst #236 = MSR 3431 { 237, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #237 = MSRi 3432 { 238, 6, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #238 = MUL 3433 { 239, 6, 1, 280, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo93,0,nullptr }, // Inst #239 = MULv5 3434 { 240, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #240 = MVNCCi 3435 { 241, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #241 = MVNi 3436 { 242, 5, 1, 272, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #242 = MVNr 3437 { 243, 6, 1, 54, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #243 = MVNsi 3438 { 244, 7, 1, 271, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo94,0,nullptr }, // Inst #244 = MVNsr 3439 { 245, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #245 = ORRri 3440 { 246, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #246 = ORRrr 3441 { 247, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #247 = ORRrsi 3442 { 248, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #248 = ORRrsr 3443 { 249, 5, 1, 55, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo16,0,nullptr }, // Inst #249 = PICADD 3444 { 250, 5, 1, 286, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #250 = PICLDR 3445 { 251, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #251 = PICLDRB 3446 { 252, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #252 = PICLDRH 3447 { 253, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #253 = PICLDRSB 3448 { 254, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #254 = PICLDRSH 3449 { 255, 5, 0, 358, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #255 = PICSTR 3450 { 256, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #256 = PICSTRB 3451 { 257, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #257 = PICSTRH 3452 { 258, 6, 1, 58, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo95,0,nullptr }, // Inst #258 = PKHBT 3453 { 259, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo95,0,nullptr }, // Inst #259 = PKHTB 3454 { 260, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #260 = PLDWi12 3455 { 261, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #261 = PLDWrs 3456 { 262, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #262 = PLDi12 3457 { 263, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #263 = PLDrs 3458 { 264, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #264 = PLIi12 3459 { 265, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #265 = PLIrs 3460 { 266, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #266 = QADD 3461 { 267, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #267 = QADD16 3462 { 268, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #268 = QADD8 3463 { 269, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #269 = QASX 3464 { 270, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #270 = QDADD 3465 { 271, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #271 = QDSUB 3466 { 272, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #272 = QSAX 3467 { 273, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #273 = QSUB 3468 { 274, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #274 = QSUB16 3469 { 275, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #275 = QSUB8 3470 { 276, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #276 = RBIT 3471 { 277, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #277 = REV 3472 { 278, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #278 = REV16 3473 { 279, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #279 = REVSH 3474 { 280, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #280 = RFEDA 3475 { 281, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #281 = RFEDA_UPD 3476 { 282, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #282 = RFEDB 3477 { 283, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #283 = RFEDB_UPD 3478 { 284, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #284 = RFEIA 3479 { 285, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #285 = RFEIA_UPD 3480 { 286, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #286 = RFEIB 3481 { 287, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #287 = RFEIB_UPD 3482 { 288, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #288 = RORi 3483 { 289, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #289 = RORr 3484 { 290, 2, 1, 50, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo11,0,nullptr }, // Inst #290 = RRX 3485 { 291, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #291 = RRXi 3486 { 292, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #292 = RSBSri 3487 { 293, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #293 = RSBSrsi 3488 { 294, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #294 = RSBSrsr 3489 { 295, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #295 = RSBri 3490 { 296, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #296 = RSBrr 3491 { 297, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #297 = RSBrsi 3492 { 298, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #298 = RSBrsr 3493 { 299, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #299 = RSCri 3494 { 300, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #300 = RSCrr 3495 { 301, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #301 = RSCrsi 3496 { 302, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #302 = RSCrsr 3497 { 303, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #303 = SADD16 3498 { 304, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #304 = SADD8 3499 { 305, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #305 = SASX 3500 { 306, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #306 = SBCri 3501 { 307, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #307 = SBCrr 3502 { 308, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #308 = SBCrsi 3503 { 309, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #309 = SBCrsr 3504 { 310, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #310 = SBFX 3505 { 311, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #311 = SDIV 3506 { 312, 5, 1, 277, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #312 = SEL 3507 { 313, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #313 = SETEND 3508 { 314, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #314 = SHA1C 3509 { 315, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #315 = SHA1H 3510 { 316, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #316 = SHA1M 3511 { 317, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #317 = SHA1P 3512 { 318, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #318 = SHA1SU0 3513 { 319, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #319 = SHA1SU1 3514 { 320, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #320 = SHA256H 3515 { 321, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #321 = SHA256H2 3516 { 322, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #322 = SHA256SU0 3517 { 323, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #323 = SHA256SU1 3518 { 324, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #324 = SHADD16 3519 { 325, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #325 = SHADD8 3520 { 326, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #326 = SHASX 3521 { 327, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #327 = SHSAX 3522 { 328, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #328 = SHSUB16 3523 { 329, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #329 = SHSUB8 3524 { 330, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #330 = SMC 3525 { 331, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #331 = SMLABB 3526 { 332, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #332 = SMLABT 3527 { 333, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #333 = SMLAD 3528 { 334, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #334 = SMLADX 3529 { 335, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #335 = SMLAL 3530 { 336, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #336 = SMLALBB 3531 { 337, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #337 = SMLALBT 3532 { 338, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #338 = SMLALD 3533 { 339, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #339 = SMLALDX 3534 { 340, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #340 = SMLALTB 3535 { 341, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #341 = SMLALTT 3536 { 342, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #342 = SMLALv5 3537 { 343, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #343 = SMLATB 3538 { 344, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #344 = SMLATT 3539 { 345, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #345 = SMLAWB 3540 { 346, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #346 = SMLAWT 3541 { 347, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #347 = SMLSD 3542 { 348, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #348 = SMLSDX 3543 { 349, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #349 = SMLSLD 3544 { 350, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #350 = SMLSLDX 3545 { 351, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #351 = SMMLA 3546 { 352, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #352 = SMMLAR 3547 { 353, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #353 = SMMLS 3548 { 354, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #354 = SMMLSR 3549 { 355, 5, 1, 280, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #355 = SMMUL 3550 { 356, 5, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #356 = SMMULR 3551 { 357, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #357 = SMUAD 3552 { 358, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #358 = SMUADX 3553 { 359, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #359 = SMULBB 3554 { 360, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #360 = SMULBT 3555 { 361, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #361 = SMULL 3556 { 362, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #362 = SMULLv5 3557 { 363, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #363 = SMULTB 3558 { 364, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #364 = SMULTT 3559 { 365, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #365 = SMULWB 3560 { 366, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #366 = SMULWT 3561 { 367, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #367 = SMUSD 3562 { 368, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #368 = SMUSDX 3563 { 369, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #369 = SRSDA 3564 { 370, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #370 = SRSDA_UPD 3565 { 371, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #371 = SRSDB 3566 { 372, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #372 = SRSDB_UPD 3567 { 373, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #373 = SRSIA 3568 { 374, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #374 = SRSIA_UPD 3569 { 375, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #375 = SRSIB 3570 { 376, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #376 = SRSIB_UPD 3571 { 377, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #377 = SSAT 3572 { 378, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #378 = SSAT16 3573 { 379, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #379 = SSAX 3574 { 380, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #380 = SSUB16 3575 { 381, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #381 = SSUB8 3576 { 382, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #382 = STC2L_OFFSET 3577 { 383, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #383 = STC2L_OPTION 3578 { 384, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #384 = STC2L_POST 3579 { 385, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #385 = STC2L_PRE 3580 { 386, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #386 = STC2_OFFSET 3581 { 387, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #387 = STC2_OPTION 3582 { 388, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #388 = STC2_POST 3583 { 389, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #389 = STC2_PRE 3584 { 390, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #390 = STCL_OFFSET 3585 { 391, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #391 = STCL_OPTION 3586 { 392, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #392 = STCL_POST 3587 { 393, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #393 = STCL_PRE 3588 { 394, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #394 = STC_OFFSET 3589 { 395, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #395 = STC_OPTION 3590 { 396, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #396 = STC_POST 3591 { 397, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #397 = STC_PRE 3592 { 398, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #398 = STL 3593 { 399, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #399 = STLB 3594 { 400, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #400 = STLEX 3595 { 401, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #401 = STLEXB 3596 { 402, 5, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo110,0,nullptr }, // Inst #402 = STLEXD 3597 { 403, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #403 = STLEXH 3598 { 404, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #404 = STLH 3599 { 405, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #405 = STMDA 3600 { 406, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #406 = STMDA_UPD 3601 { 407, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #407 = STMDB 3602 { 408, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #408 = STMDB_UPD 3603 { 409, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #409 = STMIA 3604 { 410, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #410 = STMIA_UPD 3605 { 411, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #411 = STMIB 3606 { 412, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #412 = STMIB_UPD 3607 { 413, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #413 = STRBT_POST 3608 { 414, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #414 = STRBT_POST_IMM 3609 { 415, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #415 = STRBT_POST_REG 3610 { 416, 7, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #416 = STRB_POST_IMM 3611 { 417, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #417 = STRB_POST_REG 3612 { 418, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #418 = STRB_PRE_IMM 3613 { 419, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #419 = STRB_PRE_REG 3614 { 420, 5, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #420 = STRBi12 3615 { 421, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #421 = STRBi_preidx 3616 { 422, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #422 = STRBr_preidx 3617 { 423, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #423 = STRBrs 3618 { 424, 7, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #424 = STRD 3619 { 425, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4c3ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #425 = STRD_POST 3620 { 426, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4a3ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #426 = STRD_PRE 3621 { 427, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #427 = STREX 3622 { 428, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #428 = STREXB 3623 { 429, 5, 1, 361, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo110,0,nullptr }, // Inst #429 = STREXD 3624 { 430, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #430 = STREXH 3625 { 431, 6, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x483ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #431 = STRH 3626 { 432, 6, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #432 = STRHTi 3627 { 433, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #433 = STRHTr 3628 { 434, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x4c3ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #434 = STRH_POST 3629 { 435, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4a3ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #435 = STRH_PRE 3630 { 436, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #436 = STRH_preidx 3631 { 437, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #437 = STRT_POST 3632 { 438, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #438 = STRT_POST_IMM 3633 { 439, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #439 = STRT_POST_REG 3634 { 440, 7, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #440 = STR_POST_IMM 3635 { 441, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #441 = STR_POST_REG 3636 { 442, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #442 = STR_PRE_IMM 3637 { 443, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #443 = STR_PRE_REG 3638 { 444, 5, 0, 358, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #444 = STRi12 3639 { 445, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #445 = STRi_preidx 3640 { 446, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #446 = STRr_preidx 3641 { 447, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #447 = STRrs 3642 { 448, 3, 0, 76, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #448 = SUBS_PC_LR 3643 { 449, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #449 = SUBSri 3644 { 450, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #450 = SUBSrr 3645 { 451, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #451 = SUBSrsi 3646 { 452, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #452 = SUBSrsr 3647 { 453, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #453 = SUBri 3648 { 454, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #454 = SUBrr 3649 { 455, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #455 = SUBrsi 3650 { 456, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #456 = SUBrsr 3651 { 457, 3, 0, 10, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo47,0,nullptr }, // Inst #457 = SVC 3652 { 458, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #458 = SWP 3653 { 459, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #459 = SWPB 3654 { 460, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #460 = SXTAB 3655 { 461, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #461 = SXTAB16 3656 { 462, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #462 = SXTAH 3657 { 463, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #463 = SXTB 3658 { 464, 5, 1, 290, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #464 = SXTB16 3659 { 465, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #465 = SXTH 3660 { 466, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo27,0,nullptr }, // Inst #466 = TAILJMPd 3661 { 467, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo122,0,nullptr }, // Inst #467 = TAILJMPr 3662 { 468, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo2,0,nullptr }, // Inst #468 = TCRETURNdi 3663 { 469, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo122,0,nullptr }, // Inst #469 = TCRETURNri 3664 { 470, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #470 = TEQri 3665 { 471, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #471 = TEQrr 3666 { 472, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #472 = TEQrsi 3667 { 473, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #473 = TEQrsr 3668 { 474, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, nullptr,0,nullptr }, // Inst #474 = TPsoft 3669 { 475, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #475 = TRAP 3670 { 476, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #476 = TRAPNaCl 3671 { 477, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #477 = TSTri 3672 { 478, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #478 = TSTrr 3673 { 479, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #479 = TSTrsi 3674 { 480, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #480 = TSTrsr 3675 { 481, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #481 = UADD16 3676 { 482, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #482 = UADD8 3677 { 483, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #483 = UASX 3678 { 484, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #484 = UBFX 3679 { 485, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #485 = UDF 3680 { 486, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #486 = UDIV 3681 { 487, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #487 = UHADD16 3682 { 488, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #488 = UHADD8 3683 { 489, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #489 = UHASX 3684 { 490, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #490 = UHSAX 3685 { 491, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #491 = UHSUB16 3686 { 492, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #492 = UHSUB8 3687 { 493, 6, 2, 281, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #493 = UMAAL 3688 { 494, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #494 = UMLAL 3689 { 495, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #495 = UMLALv5 3690 { 496, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #496 = UMULL 3691 { 497, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #497 = UMULLv5 3692 { 498, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #498 = UQADD16 3693 { 499, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #499 = UQADD8 3694 { 500, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #500 = UQASX 3695 { 501, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #501 = UQSAX 3696 { 502, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #502 = UQSUB16 3697 { 503, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #503 = UQSUB8 3698 { 504, 5, 1, 307, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #504 = USAD8 3699 { 505, 6, 1, 308, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #505 = USADA8 3700 { 506, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #506 = USAT 3701 { 507, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #507 = USAT16 3702 { 508, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #508 = USAX 3703 { 509, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #509 = USUB16 3704 { 510, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #510 = USUB8 3705 { 511, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #511 = UXTAB 3706 { 512, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #512 = UXTAB16 3707 { 513, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #513 = UXTAH 3708 { 514, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #514 = UXTB 3709 { 515, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #515 = UXTB16 3710 { 516, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #516 = UXTH 3711 { 517, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #517 = VABALsv2i64 3712 { 518, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #518 = VABALsv4i32 3713 { 519, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #519 = VABALsv8i16 3714 { 520, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #520 = VABALuv2i64 3715 { 521, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #521 = VABALuv4i32 3716 { 522, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #522 = VABALuv8i16 3717 { 523, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #523 = VABAsv16i8 3718 { 524, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #524 = VABAsv2i32 3719 { 525, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #525 = VABAsv4i16 3720 { 526, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #526 = VABAsv4i32 3721 { 527, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #527 = VABAsv8i16 3722 { 528, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #528 = VABAsv8i8 3723 { 529, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #529 = VABAuv16i8 3724 { 530, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #530 = VABAuv2i32 3725 { 531, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #531 = VABAuv4i16 3726 { 532, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #532 = VABAuv4i32 3727 { 533, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #533 = VABAuv8i16 3728 { 534, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #534 = VABAuv8i8 3729 { 535, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #535 = VABDLsv2i64 3730 { 536, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #536 = VABDLsv4i32 3731 { 537, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #537 = VABDLsv8i16 3732 { 538, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #538 = VABDLuv2i64 3733 { 539, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #539 = VABDLuv4i32 3734 { 540, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #540 = VABDLuv8i16 3735 { 541, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #541 = VABDfd 3736 { 542, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #542 = VABDfq 3737 { 543, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #543 = VABDsv16i8 3738 { 544, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #544 = VABDsv2i32 3739 { 545, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #545 = VABDsv4i16 3740 { 546, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #546 = VABDsv4i32 3741 { 547, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #547 = VABDsv8i16 3742 { 548, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #548 = VABDsv8i8 3743 { 549, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #549 = VABDuv16i8 3744 { 550, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #550 = VABDuv2i32 3745 { 551, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #551 = VABDuv4i16 3746 { 552, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #552 = VABDuv4i32 3747 { 553, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #553 = VABDuv8i16 3748 { 554, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #554 = VABDuv8i8 3749 { 555, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #555 = VABSD 3750 { 556, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #556 = VABSS 3751 { 557, 4, 1, 402, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #557 = VABSfd 3752 { 558, 4, 1, 403, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #558 = VABSfq 3753 { 559, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #559 = VABSv16i8 3754 { 560, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #560 = VABSv2i32 3755 { 561, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #561 = VABSv4i16 3756 { 562, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #562 = VABSv4i32 3757 { 563, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #563 = VABSv8i16 3758 { 564, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #564 = VABSv8i8 3759 { 565, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #565 = VACGEd 3760 { 566, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #566 = VACGEq 3761 { 567, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #567 = VACGTd 3762 { 568, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #568 = VACGTq 3763 { 569, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #569 = VADDD 3764 { 570, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #570 = VADDHNv2i32 3765 { 571, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #571 = VADDHNv4i16 3766 { 572, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #572 = VADDHNv8i8 3767 { 573, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #573 = VADDLsv2i64 3768 { 574, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #574 = VADDLsv4i32 3769 { 575, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #575 = VADDLsv8i16 3770 { 576, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #576 = VADDLuv2i64 3771 { 577, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #577 = VADDLuv4i32 3772 { 578, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #578 = VADDLuv8i16 3773 { 579, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #579 = VADDS 3774 { 580, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #580 = VADDWsv2i64 3775 { 581, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #581 = VADDWsv4i32 3776 { 582, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #582 = VADDWsv8i16 3777 { 583, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #583 = VADDWuv2i64 3778 { 584, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #584 = VADDWuv4i32 3779 { 585, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #585 = VADDWuv8i16 3780 { 586, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #586 = VADDfd 3781 { 587, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #587 = VADDfq 3782 { 588, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #588 = VADDv16i8 3783 { 589, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #589 = VADDv1i64 3784 { 590, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #590 = VADDv2i32 3785 { 591, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #591 = VADDv2i64 3786 { 592, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #592 = VADDv4i16 3787 { 593, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #593 = VADDv4i32 3788 { 594, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #594 = VADDv8i16 3789 { 595, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #595 = VADDv8i8 3790 { 596, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #596 = VANDd 3791 { 597, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #597 = VANDq 3792 { 598, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #598 = VBICd 3793 { 599, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #599 = VBICiv2i32 3794 { 600, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #600 = VBICiv4i16 3795 { 601, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #601 = VBICiv4i32 3796 { 602, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #602 = VBICiv8i16 3797 { 603, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #603 = VBICq 3798 { 604, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #604 = VBIFd 3799 { 605, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #605 = VBIFq 3800 { 606, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #606 = VBITd 3801 { 607, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #607 = VBITq 3802 { 608, 6, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #608 = VBSLd 3803 { 609, 6, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #609 = VBSLq 3804 { 610, 5, 1, 406, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #610 = VCEQfd 3805 { 611, 5, 1, 407, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #611 = VCEQfq 3806 { 612, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #612 = VCEQv16i8 3807 { 613, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #613 = VCEQv2i32 3808 { 614, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #614 = VCEQv4i16 3809 { 615, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #615 = VCEQv4i32 3810 { 616, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #616 = VCEQv8i16 3811 { 617, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #617 = VCEQv8i8 3812 { 618, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #618 = VCEQzv16i8 3813 { 619, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #619 = VCEQzv2f32 3814 { 620, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #620 = VCEQzv2i32 3815 { 621, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #621 = VCEQzv4f32 3816 { 622, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #622 = VCEQzv4i16 3817 { 623, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #623 = VCEQzv4i32 3818 { 624, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #624 = VCEQzv8i16 3819 { 625, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #625 = VCEQzv8i8 3820 { 626, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #626 = VCGEfd 3821 { 627, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #627 = VCGEfq 3822 { 628, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #628 = VCGEsv16i8 3823 { 629, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #629 = VCGEsv2i32 3824 { 630, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #630 = VCGEsv4i16 3825 { 631, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #631 = VCGEsv4i32 3826 { 632, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #632 = VCGEsv8i16 3827 { 633, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #633 = VCGEsv8i8 3828 { 634, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #634 = VCGEuv16i8 3829 { 635, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #635 = VCGEuv2i32 3830 { 636, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #636 = VCGEuv4i16 3831 { 637, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #637 = VCGEuv4i32 3832 { 638, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #638 = VCGEuv8i16 3833 { 639, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #639 = VCGEuv8i8 3834 { 640, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #640 = VCGEzv16i8 3835 { 641, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #641 = VCGEzv2f32 3836 { 642, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #642 = VCGEzv2i32 3837 { 643, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #643 = VCGEzv4f32 3838 { 644, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #644 = VCGEzv4i16 3839 { 645, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #645 = VCGEzv4i32 3840 { 646, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #646 = VCGEzv8i16 3841 { 647, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #647 = VCGEzv8i8 3842 { 648, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #648 = VCGTfd 3843 { 649, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #649 = VCGTfq 3844 { 650, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #650 = VCGTsv16i8 3845 { 651, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #651 = VCGTsv2i32 3846 { 652, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #652 = VCGTsv4i16 3847 { 653, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #653 = VCGTsv4i32 3848 { 654, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #654 = VCGTsv8i16 3849 { 655, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #655 = VCGTsv8i8 3850 { 656, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #656 = VCGTuv16i8 3851 { 657, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #657 = VCGTuv2i32 3852 { 658, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #658 = VCGTuv4i16 3853 { 659, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #659 = VCGTuv4i32 3854 { 660, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #660 = VCGTuv8i16 3855 { 661, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #661 = VCGTuv8i8 3856 { 662, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #662 = VCGTzv16i8 3857 { 663, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #663 = VCGTzv2f32 3858 { 664, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #664 = VCGTzv2i32 3859 { 665, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #665 = VCGTzv4f32 3860 { 666, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #666 = VCGTzv4i16 3861 { 667, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #667 = VCGTzv4i32 3862 { 668, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #668 = VCGTzv8i16 3863 { 669, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #669 = VCGTzv8i8 3864 { 670, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #670 = VCLEzv16i8 3865 { 671, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #671 = VCLEzv2f32 3866 { 672, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #672 = VCLEzv2i32 3867 { 673, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #673 = VCLEzv4f32 3868 { 674, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #674 = VCLEzv4i16 3869 { 675, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #675 = VCLEzv4i32 3870 { 676, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #676 = VCLEzv8i16 3871 { 677, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #677 = VCLEzv8i8 3872 { 678, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #678 = VCLSv16i8 3873 { 679, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #679 = VCLSv2i32 3874 { 680, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #680 = VCLSv4i16 3875 { 681, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #681 = VCLSv4i32 3876 { 682, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #682 = VCLSv8i16 3877 { 683, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #683 = VCLSv8i8 3878 { 684, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #684 = VCLTzv16i8 3879 { 685, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #685 = VCLTzv2f32 3880 { 686, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #686 = VCLTzv2i32 3881 { 687, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #687 = VCLTzv4f32 3882 { 688, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #688 = VCLTzv4i16 3883 { 689, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #689 = VCLTzv4i32 3884 { 690, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #690 = VCLTzv8i16 3885 { 691, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #691 = VCLTzv8i8 3886 { 692, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #692 = VCLZv16i8 3887 { 693, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #693 = VCLZv2i32 3888 { 694, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #694 = VCLZv4i16 3889 { 695, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #695 = VCLZv4i32 3890 { 696, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #696 = VCLZv8i16 3891 { 697, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #697 = VCLZv8i8 3892 { 698, 4, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList4, OperandInfo129,0,nullptr }, // Inst #698 = VCMPD 3893 { 699, 4, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList4, OperandInfo129,0,nullptr }, // Inst #699 = VCMPED 3894 { 700, 4, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList4, OperandInfo130,0,nullptr }, // Inst #700 = VCMPES 3895 { 701, 3, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList4, OperandInfo137,0,nullptr }, // Inst #701 = VCMPEZD 3896 { 702, 3, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList4, OperandInfo138,0,nullptr }, // Inst #702 = VCMPEZS 3897 { 703, 4, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList4, OperandInfo130,0,nullptr }, // Inst #703 = VCMPS 3898 { 704, 3, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList4, OperandInfo137,0,nullptr }, // Inst #704 = VCMPZD 3899 { 705, 3, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList4, OperandInfo138,0,nullptr }, // Inst #705 = VCMPZS 3900 { 706, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #706 = VCNTd 3901 { 707, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #707 = VCNTq 3902 { 708, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #708 = VCVTANSD 3903 { 709, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #709 = VCVTANSQ 3904 { 710, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #710 = VCVTANUD 3905 { 711, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #711 = VCVTANUQ 3906 { 712, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #712 = VCVTASD 3907 { 713, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #713 = VCVTASS 3908 { 714, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #714 = VCVTAUD 3909 { 715, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #715 = VCVTAUS 3910 { 716, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #716 = VCVTBDH 3911 { 717, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #717 = VCVTBHD 3912 { 718, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #718 = VCVTBHS 3913 { 719, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #719 = VCVTBSH 3914 { 720, 4, 1, 477, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #720 = VCVTDS 3915 { 721, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #721 = VCVTMNSD 3916 { 722, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #722 = VCVTMNSQ 3917 { 723, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #723 = VCVTMNUD 3918 { 724, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #724 = VCVTMNUQ 3919 { 725, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #725 = VCVTMSD 3920 { 726, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #726 = VCVTMSS 3921 { 727, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #727 = VCVTMUD 3922 { 728, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #728 = VCVTMUS 3923 { 729, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #729 = VCVTNNSD 3924 { 730, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #730 = VCVTNNSQ 3925 { 731, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #731 = VCVTNNUD 3926 { 732, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #732 = VCVTNNUQ 3927 { 733, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #733 = VCVTNSD 3928 { 734, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #734 = VCVTNSS 3929 { 735, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #735 = VCVTNUD 3930 { 736, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #736 = VCVTNUS 3931 { 737, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #737 = VCVTPNSD 3932 { 738, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #738 = VCVTPNSQ 3933 { 739, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #739 = VCVTPNUD 3934 { 740, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #740 = VCVTPNUQ 3935 { 741, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #741 = VCVTPSD 3936 { 742, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #742 = VCVTPSS 3937 { 743, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #743 = VCVTPUD 3938 { 744, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #744 = VCVTPUS 3939 { 745, 4, 1, 478, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #745 = VCVTSD 3940 { 746, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #746 = VCVTTDH 3941 { 747, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #747 = VCVTTHD 3942 { 748, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #748 = VCVTTHS 3943 { 749, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #749 = VCVTTSH 3944 { 750, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #750 = VCVTf2h 3945 { 751, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #751 = VCVTf2sd 3946 { 752, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #752 = VCVTf2sq 3947 { 753, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #753 = VCVTf2ud 3948 { 754, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #754 = VCVTf2uq 3949 { 755, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #755 = VCVTf2xsd 3950 { 756, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #756 = VCVTf2xsq 3951 { 757, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #757 = VCVTf2xud 3952 { 758, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #758 = VCVTf2xuq 3953 { 759, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #759 = VCVTh2f 3954 { 760, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #760 = VCVTs2fd 3955 { 761, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #761 = VCVTs2fq 3956 { 762, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #762 = VCVTu2fd 3957 { 763, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #763 = VCVTu2fq 3958 { 764, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #764 = VCVTxs2fd 3959 { 765, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #765 = VCVTxs2fq 3960 { 766, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #766 = VCVTxu2fd 3961 { 767, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #767 = VCVTxu2fq 3962 { 768, 5, 1, 588, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #768 = VDIVD 3963 { 769, 5, 1, 586, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #769 = VDIVS 3964 { 770, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #770 = VDUP16d 3965 { 771, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #771 = VDUP16q 3966 { 772, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #772 = VDUP32d 3967 { 773, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #773 = VDUP32q 3968 { 774, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #774 = VDUP8d 3969 { 775, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #775 = VDUP8q 3970 { 776, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #776 = VDUPLN16d 3971 { 777, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #777 = VDUPLN16q 3972 { 778, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #778 = VDUPLN32d 3973 { 779, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #779 = VDUPLN32q 3974 { 780, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #780 = VDUPLN8d 3975 { 781, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #781 = VDUPLN8q 3976 { 782, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #782 = VEORd 3977 { 783, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #783 = VEORq 3978 { 784, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #784 = VEXTd16 3979 { 785, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #785 = VEXTd32 3980 { 786, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #786 = VEXTd8 3981 { 787, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #787 = VEXTq16 3982 { 788, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #788 = VEXTq32 3983 { 789, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #789 = VEXTq64 3984 { 790, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #790 = VEXTq8 3985 { 791, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #791 = VFMAD 3986 { 792, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #792 = VFMAS 3987 { 793, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #793 = VFMAfd 3988 { 794, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #794 = VFMAfq 3989 { 795, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #795 = VFMSD 3990 { 796, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #796 = VFMSS 3991 { 797, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #797 = VFMSfd 3992 { 798, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #798 = VFMSfq 3993 { 799, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #799 = VFNMAD 3994 { 800, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #800 = VFNMAS 3995 { 801, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #801 = VFNMSD 3996 { 802, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #802 = VFNMSS 3997 { 803, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #803 = VGETLNi32 3998 { 804, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #804 = VGETLNs16 3999 { 805, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #805 = VGETLNs8 4000 { 806, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #806 = VGETLNu16 4001 { 807, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #807 = VGETLNu8 4002 { 808, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #808 = VHADDsv16i8 4003 { 809, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #809 = VHADDsv2i32 4004 { 810, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #810 = VHADDsv4i16 4005 { 811, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #811 = VHADDsv4i32 4006 { 812, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #812 = VHADDsv8i16 4007 { 813, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #813 = VHADDsv8i8 4008 { 814, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #814 = VHADDuv16i8 4009 { 815, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #815 = VHADDuv2i32 4010 { 816, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #816 = VHADDuv4i16 4011 { 817, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #817 = VHADDuv4i32 4012 { 818, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #818 = VHADDuv8i16 4013 { 819, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #819 = VHADDuv8i8 4014 { 820, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #820 = VHSUBsv16i8 4015 { 821, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #821 = VHSUBsv2i32 4016 { 822, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #822 = VHSUBsv4i16 4017 { 823, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #823 = VHSUBsv4i32 4018 { 824, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #824 = VHSUBsv8i16 4019 { 825, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #825 = VHSUBsv8i8 4020 { 826, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #826 = VHSUBuv16i8 4021 { 827, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #827 = VHSUBuv2i32 4022 { 828, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #828 = VHSUBuv4i16 4023 { 829, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #829 = VHSUBuv4i32 4024 { 830, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #830 = VHSUBuv8i16 4025 { 831, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #831 = VHSUBuv8i8 4026 { 832, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #832 = VLD1DUPd16 4027 { 833, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #833 = VLD1DUPd16wb_fixed 4028 { 834, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #834 = VLD1DUPd16wb_register 4029 { 835, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #835 = VLD1DUPd32 4030 { 836, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #836 = VLD1DUPd32wb_fixed 4031 { 837, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #837 = VLD1DUPd32wb_register 4032 { 838, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #838 = VLD1DUPd8 4033 { 839, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #839 = VLD1DUPd8wb_fixed 4034 { 840, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #840 = VLD1DUPd8wb_register 4035 { 841, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #841 = VLD1DUPq16 4036 { 842, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #842 = VLD1DUPq16wb_fixed 4037 { 843, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #843 = VLD1DUPq16wb_register 4038 { 844, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #844 = VLD1DUPq32 4039 { 845, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #845 = VLD1DUPq32wb_fixed 4040 { 846, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #846 = VLD1DUPq32wb_register 4041 { 847, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #847 = VLD1DUPq8 4042 { 848, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #848 = VLD1DUPq8wb_fixed 4043 { 849, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #849 = VLD1DUPq8wb_register 4044 { 850, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #850 = VLD1LNd16 4045 { 851, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #851 = VLD1LNd16_UPD 4046 { 852, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #852 = VLD1LNd32 4047 { 853, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #853 = VLD1LNd32_UPD 4048 { 854, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #854 = VLD1LNd8 4049 { 855, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #855 = VLD1LNd8_UPD 4050 { 856, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #856 = VLD1LNdAsm_16 4051 { 857, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #857 = VLD1LNdAsm_32 4052 { 858, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #858 = VLD1LNdAsm_8 4053 { 859, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #859 = VLD1LNdWB_fixed_Asm_16 4054 { 860, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #860 = VLD1LNdWB_fixed_Asm_32 4055 { 861, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #861 = VLD1LNdWB_fixed_Asm_8 4056 { 862, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #862 = VLD1LNdWB_register_Asm_16 4057 { 863, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #863 = VLD1LNdWB_register_Asm_32 4058 { 864, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #864 = VLD1LNdWB_register_Asm_8 4059 { 865, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #865 = VLD1LNq16Pseudo 4060 { 866, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #866 = VLD1LNq16Pseudo_UPD 4061 { 867, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #867 = VLD1LNq32Pseudo 4062 { 868, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #868 = VLD1LNq32Pseudo_UPD 4063 { 869, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #869 = VLD1LNq8Pseudo 4064 { 870, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #870 = VLD1LNq8Pseudo_UPD 4065 { 871, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #871 = VLD1d16 4066 { 872, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #872 = VLD1d16Q 4067 { 873, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #873 = VLD1d16Qwb_fixed 4068 { 874, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #874 = VLD1d16Qwb_register 4069 { 875, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #875 = VLD1d16T 4070 { 876, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #876 = VLD1d16Twb_fixed 4071 { 877, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #877 = VLD1d16Twb_register 4072 { 878, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #878 = VLD1d16wb_fixed 4073 { 879, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #879 = VLD1d16wb_register 4074 { 880, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #880 = VLD1d32 4075 { 881, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #881 = VLD1d32Q 4076 { 882, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #882 = VLD1d32Qwb_fixed 4077 { 883, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #883 = VLD1d32Qwb_register 4078 { 884, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #884 = VLD1d32T 4079 { 885, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #885 = VLD1d32Twb_fixed 4080 { 886, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #886 = VLD1d32Twb_register 4081 { 887, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #887 = VLD1d32wb_fixed 4082 { 888, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #888 = VLD1d32wb_register 4083 { 889, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #889 = VLD1d64 4084 { 890, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #890 = VLD1d64Q 4085 { 891, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #891 = VLD1d64QPseudo 4086 { 892, 6, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #892 = VLD1d64QPseudoWB_fixed 4087 { 893, 7, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #893 = VLD1d64QPseudoWB_register 4088 { 894, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #894 = VLD1d64Qwb_fixed 4089 { 895, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #895 = VLD1d64Qwb_register 4090 { 896, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #896 = VLD1d64T 4091 { 897, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #897 = VLD1d64TPseudo 4092 { 898, 6, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #898 = VLD1d64TPseudoWB_fixed 4093 { 899, 7, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #899 = VLD1d64TPseudoWB_register 4094 { 900, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #900 = VLD1d64Twb_fixed 4095 { 901, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #901 = VLD1d64Twb_register 4096 { 902, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #902 = VLD1d64wb_fixed 4097 { 903, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #903 = VLD1d64wb_register 4098 { 904, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #904 = VLD1d8 4099 { 905, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #905 = VLD1d8Q 4100 { 906, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #906 = VLD1d8Qwb_fixed 4101 { 907, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #907 = VLD1d8Qwb_register 4102 { 908, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #908 = VLD1d8T 4103 { 909, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #909 = VLD1d8Twb_fixed 4104 { 910, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #910 = VLD1d8Twb_register 4105 { 911, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #911 = VLD1d8wb_fixed 4106 { 912, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #912 = VLD1d8wb_register 4107 { 913, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #913 = VLD1q16 4108 { 914, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #914 = VLD1q16wb_fixed 4109 { 915, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #915 = VLD1q16wb_register 4110 { 916, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #916 = VLD1q32 4111 { 917, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #917 = VLD1q32wb_fixed 4112 { 918, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #918 = VLD1q32wb_register 4113 { 919, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #919 = VLD1q64 4114 { 920, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #920 = VLD1q64wb_fixed 4115 { 921, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #921 = VLD1q64wb_register 4116 { 922, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #922 = VLD1q8 4117 { 923, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #923 = VLD1q8wb_fixed 4118 { 924, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #924 = VLD1q8wb_register 4119 { 925, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #925 = VLD2DUPd16 4120 { 926, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #926 = VLD2DUPd16wb_fixed 4121 { 927, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #927 = VLD2DUPd16wb_register 4122 { 928, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #928 = VLD2DUPd16x2 4123 { 929, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #929 = VLD2DUPd16x2wb_fixed 4124 { 930, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #930 = VLD2DUPd16x2wb_register 4125 { 931, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #931 = VLD2DUPd32 4126 { 932, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #932 = VLD2DUPd32wb_fixed 4127 { 933, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #933 = VLD2DUPd32wb_register 4128 { 934, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #934 = VLD2DUPd32x2 4129 { 935, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #935 = VLD2DUPd32x2wb_fixed 4130 { 936, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #936 = VLD2DUPd32x2wb_register 4131 { 937, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #937 = VLD2DUPd8 4132 { 938, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #938 = VLD2DUPd8wb_fixed 4133 { 939, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #939 = VLD2DUPd8wb_register 4134 { 940, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #940 = VLD2DUPd8x2 4135 { 941, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #941 = VLD2DUPd8x2wb_fixed 4136 { 942, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #942 = VLD2DUPd8x2wb_register 4137 { 943, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #943 = VLD2LNd16 4138 { 944, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #944 = VLD2LNd16Pseudo 4139 { 945, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #945 = VLD2LNd16Pseudo_UPD 4140 { 946, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #946 = VLD2LNd16_UPD 4141 { 947, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #947 = VLD2LNd32 4142 { 948, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #948 = VLD2LNd32Pseudo 4143 { 949, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #949 = VLD2LNd32Pseudo_UPD 4144 { 950, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #950 = VLD2LNd32_UPD 4145 { 951, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #951 = VLD2LNd8 4146 { 952, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #952 = VLD2LNd8Pseudo 4147 { 953, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #953 = VLD2LNd8Pseudo_UPD 4148 { 954, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #954 = VLD2LNd8_UPD 4149 { 955, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #955 = VLD2LNdAsm_16 4150 { 956, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #956 = VLD2LNdAsm_32 4151 { 957, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #957 = VLD2LNdAsm_8 4152 { 958, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #958 = VLD2LNdWB_fixed_Asm_16 4153 { 959, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #959 = VLD2LNdWB_fixed_Asm_32 4154 { 960, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #960 = VLD2LNdWB_fixed_Asm_8 4155 { 961, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #961 = VLD2LNdWB_register_Asm_16 4156 { 962, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #962 = VLD2LNdWB_register_Asm_32 4157 { 963, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #963 = VLD2LNdWB_register_Asm_8 4158 { 964, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #964 = VLD2LNq16 4159 { 965, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #965 = VLD2LNq16Pseudo 4160 { 966, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #966 = VLD2LNq16Pseudo_UPD 4161 { 967, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #967 = VLD2LNq16_UPD 4162 { 968, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #968 = VLD2LNq32 4163 { 969, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #969 = VLD2LNq32Pseudo 4164 { 970, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #970 = VLD2LNq32Pseudo_UPD 4165 { 971, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #971 = VLD2LNq32_UPD 4166 { 972, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #972 = VLD2LNqAsm_16 4167 { 973, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #973 = VLD2LNqAsm_32 4168 { 974, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #974 = VLD2LNqWB_fixed_Asm_16 4169 { 975, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #975 = VLD2LNqWB_fixed_Asm_32 4170 { 976, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #976 = VLD2LNqWB_register_Asm_16 4171 { 977, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #977 = VLD2LNqWB_register_Asm_32 4172 { 978, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #978 = VLD2b16 4173 { 979, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #979 = VLD2b16wb_fixed 4174 { 980, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #980 = VLD2b16wb_register 4175 { 981, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #981 = VLD2b32 4176 { 982, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #982 = VLD2b32wb_fixed 4177 { 983, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #983 = VLD2b32wb_register 4178 { 984, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #984 = VLD2b8 4179 { 985, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #985 = VLD2b8wb_fixed 4180 { 986, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #986 = VLD2b8wb_register 4181 { 987, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #987 = VLD2d16 4182 { 988, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #988 = VLD2d16wb_fixed 4183 { 989, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #989 = VLD2d16wb_register 4184 { 990, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #990 = VLD2d32 4185 { 991, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #991 = VLD2d32wb_fixed 4186 { 992, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #992 = VLD2d32wb_register 4187 { 993, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #993 = VLD2d8 4188 { 994, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #994 = VLD2d8wb_fixed 4189 { 995, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #995 = VLD2d8wb_register 4190 { 996, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #996 = VLD2q16 4191 { 997, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #997 = VLD2q16Pseudo 4192 { 998, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #998 = VLD2q16PseudoWB_fixed 4193 { 999, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #999 = VLD2q16PseudoWB_register 4194 { 1000, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #1000 = VLD2q16wb_fixed 4195 { 1001, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1001 = VLD2q16wb_register 4196 { 1002, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1002 = VLD2q32 4197 { 1003, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1003 = VLD2q32Pseudo 4198 { 1004, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1004 = VLD2q32PseudoWB_fixed 4199 { 1005, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #1005 = VLD2q32PseudoWB_register 4200 { 1006, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #1006 = VLD2q32wb_fixed 4201 { 1007, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1007 = VLD2q32wb_register 4202 { 1008, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1008 = VLD2q8 4203 { 1009, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1009 = VLD2q8Pseudo 4204 { 1010, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1010 = VLD2q8PseudoWB_fixed 4205 { 1011, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #1011 = VLD2q8PseudoWB_register 4206 { 1012, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #1012 = VLD2q8wb_fixed 4207 { 1013, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1013 = VLD2q8wb_register 4208 { 1014, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1014 = VLD3DUPd16 4209 { 1015, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1015 = VLD3DUPd16Pseudo 4210 { 1016, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1016 = VLD3DUPd16Pseudo_UPD 4211 { 1017, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1017 = VLD3DUPd16_UPD 4212 { 1018, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1018 = VLD3DUPd32 4213 { 1019, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1019 = VLD3DUPd32Pseudo 4214 { 1020, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1020 = VLD3DUPd32Pseudo_UPD 4215 { 1021, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1021 = VLD3DUPd32_UPD 4216 { 1022, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1022 = VLD3DUPd8 4217 { 1023, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1023 = VLD3DUPd8Pseudo 4218 { 1024, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1024 = VLD3DUPd8Pseudo_UPD 4219 { 1025, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1025 = VLD3DUPd8_UPD 4220 { 1026, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1026 = VLD3DUPdAsm_16 4221 { 1027, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1027 = VLD3DUPdAsm_32 4222 { 1028, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1028 = VLD3DUPdAsm_8 4223 { 1029, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1029 = VLD3DUPdWB_fixed_Asm_16 4224 { 1030, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1030 = VLD3DUPdWB_fixed_Asm_32 4225 { 1031, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1031 = VLD3DUPdWB_fixed_Asm_8 4226 { 1032, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1032 = VLD3DUPdWB_register_Asm_16 4227 { 1033, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1033 = VLD3DUPdWB_register_Asm_32 4228 { 1034, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1034 = VLD3DUPdWB_register_Asm_8 4229 { 1035, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1035 = VLD3DUPq16 4230 { 1036, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1036 = VLD3DUPq16_UPD 4231 { 1037, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1037 = VLD3DUPq32 4232 { 1038, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1038 = VLD3DUPq32_UPD 4233 { 1039, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1039 = VLD3DUPq8 4234 { 1040, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1040 = VLD3DUPq8_UPD 4235 { 1041, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1041 = VLD3DUPqAsm_16 4236 { 1042, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1042 = VLD3DUPqAsm_32 4237 { 1043, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1043 = VLD3DUPqAsm_8 4238 { 1044, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1044 = VLD3DUPqWB_fixed_Asm_16 4239 { 1045, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1045 = VLD3DUPqWB_fixed_Asm_32 4240 { 1046, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1046 = VLD3DUPqWB_fixed_Asm_8 4241 { 1047, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1047 = VLD3DUPqWB_register_Asm_16 4242 { 1048, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1048 = VLD3DUPqWB_register_Asm_32 4243 { 1049, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1049 = VLD3DUPqWB_register_Asm_8 4244 { 1050, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1050 = VLD3LNd16 4245 { 1051, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1051 = VLD3LNd16Pseudo 4246 { 1052, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1052 = VLD3LNd16Pseudo_UPD 4247 { 1053, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1053 = VLD3LNd16_UPD 4248 { 1054, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1054 = VLD3LNd32 4249 { 1055, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1055 = VLD3LNd32Pseudo 4250 { 1056, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1056 = VLD3LNd32Pseudo_UPD 4251 { 1057, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1057 = VLD3LNd32_UPD 4252 { 1058, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1058 = VLD3LNd8 4253 { 1059, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1059 = VLD3LNd8Pseudo 4254 { 1060, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1060 = VLD3LNd8Pseudo_UPD 4255 { 1061, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1061 = VLD3LNd8_UPD 4256 { 1062, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1062 = VLD3LNdAsm_16 4257 { 1063, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1063 = VLD3LNdAsm_32 4258 { 1064, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1064 = VLD3LNdAsm_8 4259 { 1065, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1065 = VLD3LNdWB_fixed_Asm_16 4260 { 1066, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1066 = VLD3LNdWB_fixed_Asm_32 4261 { 1067, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1067 = VLD3LNdWB_fixed_Asm_8 4262 { 1068, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1068 = VLD3LNdWB_register_Asm_16 4263 { 1069, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1069 = VLD3LNdWB_register_Asm_32 4264 { 1070, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1070 = VLD3LNdWB_register_Asm_8 4265 { 1071, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1071 = VLD3LNq16 4266 { 1072, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1072 = VLD3LNq16Pseudo 4267 { 1073, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1073 = VLD3LNq16Pseudo_UPD 4268 { 1074, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1074 = VLD3LNq16_UPD 4269 { 1075, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1075 = VLD3LNq32 4270 { 1076, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1076 = VLD3LNq32Pseudo 4271 { 1077, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1077 = VLD3LNq32Pseudo_UPD 4272 { 1078, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1078 = VLD3LNq32_UPD 4273 { 1079, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1079 = VLD3LNqAsm_16 4274 { 1080, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1080 = VLD3LNqAsm_32 4275 { 1081, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1081 = VLD3LNqWB_fixed_Asm_16 4276 { 1082, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1082 = VLD3LNqWB_fixed_Asm_32 4277 { 1083, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1083 = VLD3LNqWB_register_Asm_16 4278 { 1084, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1084 = VLD3LNqWB_register_Asm_32 4279 { 1085, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1085 = VLD3d16 4280 { 1086, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1086 = VLD3d16Pseudo 4281 { 1087, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1087 = VLD3d16Pseudo_UPD 4282 { 1088, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1088 = VLD3d16_UPD 4283 { 1089, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1089 = VLD3d32 4284 { 1090, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1090 = VLD3d32Pseudo 4285 { 1091, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1091 = VLD3d32Pseudo_UPD 4286 { 1092, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1092 = VLD3d32_UPD 4287 { 1093, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1093 = VLD3d8 4288 { 1094, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1094 = VLD3d8Pseudo 4289 { 1095, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1095 = VLD3d8Pseudo_UPD 4290 { 1096, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1096 = VLD3d8_UPD 4291 { 1097, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1097 = VLD3dAsm_16 4292 { 1098, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1098 = VLD3dAsm_32 4293 { 1099, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1099 = VLD3dAsm_8 4294 { 1100, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1100 = VLD3dWB_fixed_Asm_16 4295 { 1101, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1101 = VLD3dWB_fixed_Asm_32 4296 { 1102, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1102 = VLD3dWB_fixed_Asm_8 4297 { 1103, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1103 = VLD3dWB_register_Asm_16 4298 { 1104, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1104 = VLD3dWB_register_Asm_32 4299 { 1105, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1105 = VLD3dWB_register_Asm_8 4300 { 1106, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1106 = VLD3q16 4301 { 1107, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1107 = VLD3q16Pseudo_UPD 4302 { 1108, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1108 = VLD3q16_UPD 4303 { 1109, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1109 = VLD3q16oddPseudo 4304 { 1110, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1110 = VLD3q16oddPseudo_UPD 4305 { 1111, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1111 = VLD3q32 4306 { 1112, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1112 = VLD3q32Pseudo_UPD 4307 { 1113, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1113 = VLD3q32_UPD 4308 { 1114, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1114 = VLD3q32oddPseudo 4309 { 1115, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1115 = VLD3q32oddPseudo_UPD 4310 { 1116, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1116 = VLD3q8 4311 { 1117, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1117 = VLD3q8Pseudo_UPD 4312 { 1118, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1118 = VLD3q8_UPD 4313 { 1119, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1119 = VLD3q8oddPseudo 4314 { 1120, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1120 = VLD3q8oddPseudo_UPD 4315 { 1121, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1121 = VLD3qAsm_16 4316 { 1122, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1122 = VLD3qAsm_32 4317 { 1123, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1123 = VLD3qAsm_8 4318 { 1124, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1124 = VLD3qWB_fixed_Asm_16 4319 { 1125, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1125 = VLD3qWB_fixed_Asm_32 4320 { 1126, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1126 = VLD3qWB_fixed_Asm_8 4321 { 1127, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1127 = VLD3qWB_register_Asm_16 4322 { 1128, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1128 = VLD3qWB_register_Asm_32 4323 { 1129, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1129 = VLD3qWB_register_Asm_8 4324 { 1130, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1130 = VLD4DUPd16 4325 { 1131, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1131 = VLD4DUPd16Pseudo 4326 { 1132, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1132 = VLD4DUPd16Pseudo_UPD 4327 { 1133, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1133 = VLD4DUPd16_UPD 4328 { 1134, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1134 = VLD4DUPd32 4329 { 1135, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1135 = VLD4DUPd32Pseudo 4330 { 1136, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1136 = VLD4DUPd32Pseudo_UPD 4331 { 1137, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1137 = VLD4DUPd32_UPD 4332 { 1138, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1138 = VLD4DUPd8 4333 { 1139, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1139 = VLD4DUPd8Pseudo 4334 { 1140, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1140 = VLD4DUPd8Pseudo_UPD 4335 { 1141, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1141 = VLD4DUPd8_UPD 4336 { 1142, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1142 = VLD4DUPdAsm_16 4337 { 1143, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1143 = VLD4DUPdAsm_32 4338 { 1144, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1144 = VLD4DUPdAsm_8 4339 { 1145, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1145 = VLD4DUPdWB_fixed_Asm_16 4340 { 1146, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1146 = VLD4DUPdWB_fixed_Asm_32 4341 { 1147, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1147 = VLD4DUPdWB_fixed_Asm_8 4342 { 1148, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1148 = VLD4DUPdWB_register_Asm_16 4343 { 1149, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1149 = VLD4DUPdWB_register_Asm_32 4344 { 1150, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1150 = VLD4DUPdWB_register_Asm_8 4345 { 1151, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1151 = VLD4DUPq16 4346 { 1152, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1152 = VLD4DUPq16_UPD 4347 { 1153, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1153 = VLD4DUPq32 4348 { 1154, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1154 = VLD4DUPq32_UPD 4349 { 1155, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1155 = VLD4DUPq8 4350 { 1156, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1156 = VLD4DUPq8_UPD 4351 { 1157, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1157 = VLD4DUPqAsm_16 4352 { 1158, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1158 = VLD4DUPqAsm_32 4353 { 1159, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1159 = VLD4DUPqAsm_8 4354 { 1160, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1160 = VLD4DUPqWB_fixed_Asm_16 4355 { 1161, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1161 = VLD4DUPqWB_fixed_Asm_32 4356 { 1162, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1162 = VLD4DUPqWB_fixed_Asm_8 4357 { 1163, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1163 = VLD4DUPqWB_register_Asm_16 4358 { 1164, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1164 = VLD4DUPqWB_register_Asm_32 4359 { 1165, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1165 = VLD4DUPqWB_register_Asm_8 4360 { 1166, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1166 = VLD4LNd16 4361 { 1167, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1167 = VLD4LNd16Pseudo 4362 { 1168, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1168 = VLD4LNd16Pseudo_UPD 4363 { 1169, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1169 = VLD4LNd16_UPD 4364 { 1170, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1170 = VLD4LNd32 4365 { 1171, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1171 = VLD4LNd32Pseudo 4366 { 1172, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1172 = VLD4LNd32Pseudo_UPD 4367 { 1173, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1173 = VLD4LNd32_UPD 4368 { 1174, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1174 = VLD4LNd8 4369 { 1175, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1175 = VLD4LNd8Pseudo 4370 { 1176, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1176 = VLD4LNd8Pseudo_UPD 4371 { 1177, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1177 = VLD4LNd8_UPD 4372 { 1178, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1178 = VLD4LNdAsm_16 4373 { 1179, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1179 = VLD4LNdAsm_32 4374 { 1180, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1180 = VLD4LNdAsm_8 4375 { 1181, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1181 = VLD4LNdWB_fixed_Asm_16 4376 { 1182, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1182 = VLD4LNdWB_fixed_Asm_32 4377 { 1183, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1183 = VLD4LNdWB_fixed_Asm_8 4378 { 1184, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1184 = VLD4LNdWB_register_Asm_16 4379 { 1185, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1185 = VLD4LNdWB_register_Asm_32 4380 { 1186, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1186 = VLD4LNdWB_register_Asm_8 4381 { 1187, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1187 = VLD4LNq16 4382 { 1188, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1188 = VLD4LNq16Pseudo 4383 { 1189, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1189 = VLD4LNq16Pseudo_UPD 4384 { 1190, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1190 = VLD4LNq16_UPD 4385 { 1191, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1191 = VLD4LNq32 4386 { 1192, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1192 = VLD4LNq32Pseudo 4387 { 1193, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1193 = VLD4LNq32Pseudo_UPD 4388 { 1194, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1194 = VLD4LNq32_UPD 4389 { 1195, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1195 = VLD4LNqAsm_16 4390 { 1196, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1196 = VLD4LNqAsm_32 4391 { 1197, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1197 = VLD4LNqWB_fixed_Asm_16 4392 { 1198, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1198 = VLD4LNqWB_fixed_Asm_32 4393 { 1199, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1199 = VLD4LNqWB_register_Asm_16 4394 { 1200, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1200 = VLD4LNqWB_register_Asm_32 4395 { 1201, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1201 = VLD4d16 4396 { 1202, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1202 = VLD4d16Pseudo 4397 { 1203, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1203 = VLD4d16Pseudo_UPD 4398 { 1204, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1204 = VLD4d16_UPD 4399 { 1205, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1205 = VLD4d32 4400 { 1206, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1206 = VLD4d32Pseudo 4401 { 1207, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1207 = VLD4d32Pseudo_UPD 4402 { 1208, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1208 = VLD4d32_UPD 4403 { 1209, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1209 = VLD4d8 4404 { 1210, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1210 = VLD4d8Pseudo 4405 { 1211, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1211 = VLD4d8Pseudo_UPD 4406 { 1212, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1212 = VLD4d8_UPD 4407 { 1213, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1213 = VLD4dAsm_16 4408 { 1214, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1214 = VLD4dAsm_32 4409 { 1215, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1215 = VLD4dAsm_8 4410 { 1216, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1216 = VLD4dWB_fixed_Asm_16 4411 { 1217, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1217 = VLD4dWB_fixed_Asm_32 4412 { 1218, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1218 = VLD4dWB_fixed_Asm_8 4413 { 1219, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1219 = VLD4dWB_register_Asm_16 4414 { 1220, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1220 = VLD4dWB_register_Asm_32 4415 { 1221, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1221 = VLD4dWB_register_Asm_8 4416 { 1222, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1222 = VLD4q16 4417 { 1223, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1223 = VLD4q16Pseudo_UPD 4418 { 1224, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1224 = VLD4q16_UPD 4419 { 1225, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1225 = VLD4q16oddPseudo 4420 { 1226, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1226 = VLD4q16oddPseudo_UPD 4421 { 1227, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1227 = VLD4q32 4422 { 1228, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1228 = VLD4q32Pseudo_UPD 4423 { 1229, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1229 = VLD4q32_UPD 4424 { 1230, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1230 = VLD4q32oddPseudo 4425 { 1231, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1231 = VLD4q32oddPseudo_UPD 4426 { 1232, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1232 = VLD4q8 4427 { 1233, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1233 = VLD4q8Pseudo_UPD 4428 { 1234, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1234 = VLD4q8_UPD 4429 { 1235, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1235 = VLD4q8oddPseudo 4430 { 1236, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1236 = VLD4q8oddPseudo_UPD 4431 { 1237, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1237 = VLD4qAsm_16 4432 { 1238, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1238 = VLD4qAsm_32 4433 { 1239, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1239 = VLD4qAsm_8 4434 { 1240, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1240 = VLD4qWB_fixed_Asm_16 4435 { 1241, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1241 = VLD4qWB_fixed_Asm_32 4436 { 1242, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1242 = VLD4qWB_fixed_Asm_8 4437 { 1243, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1243 = VLD4qWB_register_Asm_16 4438 { 1244, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1244 = VLD4qWB_register_Asm_32 4439 { 1245, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1245 = VLD4qWB_register_Asm_8 4440 { 1246, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1246 = VLDMDDB_UPD 4441 { 1247, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1247 = VLDMDIA 4442 { 1248, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1248 = VLDMDIA_UPD 4443 { 1249, 4, 1, 512, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1249 = VLDMQIA 4444 { 1250, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1250 = VLDMSDB_UPD 4445 { 1251, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1251 = VLDMSIA 4446 { 1252, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1252 = VLDMSIA_UPD 4447 { 1253, 5, 1, 508, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1253 = VLDRD 4448 { 1254, 5, 1, 509, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1254 = VLDRS 4449 { 1255, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1255 = VMAXNMD 4450 { 1256, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1256 = VMAXNMND 4451 { 1257, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #1257 = VMAXNMNQ 4452 { 1258, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #1258 = VMAXNMS 4453 { 1259, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1259 = VMAXfd 4454 { 1260, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1260 = VMAXfq 4455 { 1261, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1261 = VMAXsv16i8 4456 { 1262, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1262 = VMAXsv2i32 4457 { 1263, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1263 = VMAXsv4i16 4458 { 1264, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1264 = VMAXsv4i32 4459 { 1265, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1265 = VMAXsv8i16 4460 { 1266, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1266 = VMAXsv8i8 4461 { 1267, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1267 = VMAXuv16i8 4462 { 1268, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1268 = VMAXuv2i32 4463 { 1269, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1269 = VMAXuv4i16 4464 { 1270, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1270 = VMAXuv4i32 4465 { 1271, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1271 = VMAXuv8i16 4466 { 1272, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1272 = VMAXuv8i8 4467 { 1273, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1273 = VMINNMD 4468 { 1274, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1274 = VMINNMND 4469 { 1275, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #1275 = VMINNMNQ 4470 { 1276, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #1276 = VMINNMS 4471 { 1277, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1277 = VMINfd 4472 { 1278, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1278 = VMINfq 4473 { 1279, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1279 = VMINsv16i8 4474 { 1280, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1280 = VMINsv2i32 4475 { 1281, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1281 = VMINsv4i16 4476 { 1282, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1282 = VMINsv4i32 4477 { 1283, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1283 = VMINsv8i16 4478 { 1284, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1284 = VMINsv8i8 4479 { 1285, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1285 = VMINuv16i8 4480 { 1286, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1286 = VMINuv2i32 4481 { 1287, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1287 = VMINuv4i16 4482 { 1288, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1288 = VMINuv4i32 4483 { 1289, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1289 = VMINuv8i16 4484 { 1290, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1290 = VMINuv8i8 4485 { 1291, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1291 = VMLAD 4486 { 1292, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1292 = VMLALslsv2i32 4487 { 1293, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1293 = VMLALslsv4i16 4488 { 1294, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1294 = VMLALsluv2i32 4489 { 1295, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1295 = VMLALsluv4i16 4490 { 1296, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1296 = VMLALsv2i64 4491 { 1297, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1297 = VMLALsv4i32 4492 { 1298, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1298 = VMLALsv8i16 4493 { 1299, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1299 = VMLALuv2i64 4494 { 1300, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1300 = VMLALuv4i32 4495 { 1301, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1301 = VMLALuv8i16 4496 { 1302, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1302 = VMLAS 4497 { 1303, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1303 = VMLAfd 4498 { 1304, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1304 = VMLAfq 4499 { 1305, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1305 = VMLAslfd 4500 { 1306, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1306 = VMLAslfq 4501 { 1307, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1307 = VMLAslv2i32 4502 { 1308, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1308 = VMLAslv4i16 4503 { 1309, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1309 = VMLAslv4i32 4504 { 1310, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1310 = VMLAslv8i16 4505 { 1311, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1311 = VMLAv16i8 4506 { 1312, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1312 = VMLAv2i32 4507 { 1313, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1313 = VMLAv4i16 4508 { 1314, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1314 = VMLAv4i32 4509 { 1315, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1315 = VMLAv8i16 4510 { 1316, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1316 = VMLAv8i8 4511 { 1317, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1317 = VMLSD 4512 { 1318, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1318 = VMLSLslsv2i32 4513 { 1319, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1319 = VMLSLslsv4i16 4514 { 1320, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1320 = VMLSLsluv2i32 4515 { 1321, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1321 = VMLSLsluv4i16 4516 { 1322, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1322 = VMLSLsv2i64 4517 { 1323, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1323 = VMLSLsv4i32 4518 { 1324, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1324 = VMLSLsv8i16 4519 { 1325, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1325 = VMLSLuv2i64 4520 { 1326, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1326 = VMLSLuv4i32 4521 { 1327, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1327 = VMLSLuv8i16 4522 { 1328, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1328 = VMLSS 4523 { 1329, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1329 = VMLSfd 4524 { 1330, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1330 = VMLSfq 4525 { 1331, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1331 = VMLSslfd 4526 { 1332, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1332 = VMLSslfq 4527 { 1333, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1333 = VMLSslv2i32 4528 { 1334, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1334 = VMLSslv4i16 4529 { 1335, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1335 = VMLSslv4i32 4530 { 1336, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1336 = VMLSslv8i16 4531 { 1337, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1337 = VMLSv16i8 4532 { 1338, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1338 = VMLSv2i32 4533 { 1339, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1339 = VMLSv4i16 4534 { 1340, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1340 = VMLSv4i32 4535 { 1341, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1341 = VMLSv8i16 4536 { 1342, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1342 = VMLSv8i8 4537 { 1343, 4, 1, 487, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1343 = VMOVD 4538 { 1344, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1344 = VMOVD0 4539 { 1345, 5, 1, 501, 4, 0|(1<<MCID_Predicable)|(1<<MCID_RegSequence), 0x18a80ULL, nullptr, nullptr, OperandInfo201,0,nullptr }, // Inst #1345 = VMOVDRR 4540 { 1346, 5, 1, 487, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1346 = VMOVDcc 4541 { 1347, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1347 = VMOVLsv2i64 4542 { 1348, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1348 = VMOVLsv4i32 4543 { 1349, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1349 = VMOVLsv8i16 4544 { 1350, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1350 = VMOVLuv2i64 4545 { 1351, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1351 = VMOVLuv4i32 4546 { 1352, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1352 = VMOVLuv8i16 4547 { 1353, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1353 = VMOVNv2i32 4548 { 1354, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1354 = VMOVNv4i16 4549 { 1355, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1355 = VMOVNv8i8 4550 { 1356, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo203,0,nullptr }, // Inst #1356 = VMOVQ0 4551 { 1357, 5, 2, 500, 4, 0|(1<<MCID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo204,0,nullptr }, // Inst #1357 = VMOVRRD 4552 { 1358, 6, 2, 500, 4, 0|(1<<MCID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1358 = VMOVRRS 4553 { 1359, 4, 1, 497, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo206,0,nullptr }, // Inst #1359 = VMOVRS 4554 { 1360, 4, 1, 488, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1360 = VMOVS 4555 { 1361, 4, 1, 498, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo207,0,nullptr }, // Inst #1361 = VMOVSR 4556 { 1362, 6, 2, 502, 4, 0|(1<<MCID_Predicable), 0x18a80ULL, nullptr, nullptr, OperandInfo208,0,nullptr }, // Inst #1362 = VMOVSRR 4557 { 1363, 5, 1, 488, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo209,0,nullptr }, // Inst #1363 = VMOVScc 4558 { 1364, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1364 = VMOVv16i8 4559 { 1365, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1365 = VMOVv1i64 4560 { 1366, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1366 = VMOVv2f32 4561 { 1367, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1367 = VMOVv2i32 4562 { 1368, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1368 = VMOVv2i64 4563 { 1369, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1369 = VMOVv4f32 4564 { 1370, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1370 = VMOVv4i16 4565 { 1371, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1371 = VMOVv4i32 4566 { 1372, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1372 = VMOVv8i16 4567 { 1373, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1373 = VMOVv8i8 4568 { 1374, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1374 = VMRS 4569 { 1375, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1375 = VMRS_FPEXC 4570 { 1376, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1376 = VMRS_FPINST 4571 { 1377, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1377 = VMRS_FPINST2 4572 { 1378, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1378 = VMRS_FPSID 4573 { 1379, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1379 = VMRS_MVFR0 4574 { 1380, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1380 = VMRS_MVFR1 4575 { 1381, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1381 = VMRS_MVFR2 4576 { 1382, 3, 0, 506, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1382 = VMSR 4577 { 1383, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1383 = VMSR_FPEXC 4578 { 1384, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1384 = VMSR_FPINST 4579 { 1385, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1385 = VMSR_FPINST2 4580 { 1386, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1386 = VMSR_FPSID 4581 { 1387, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1387 = VMULD 4582 { 1388, 3, 1, 451, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo211,0,nullptr }, // Inst #1388 = VMULLp64 4583 { 1389, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1389 = VMULLp8 4584 { 1390, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1390 = VMULLslsv2i32 4585 { 1391, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1391 = VMULLslsv4i16 4586 { 1392, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1392 = VMULLsluv2i32 4587 { 1393, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1393 = VMULLsluv4i16 4588 { 1394, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1394 = VMULLsv2i64 4589 { 1395, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1395 = VMULLsv4i32 4590 { 1396, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1396 = VMULLsv8i16 4591 { 1397, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1397 = VMULLuv2i64 4592 { 1398, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1398 = VMULLuv4i32 4593 { 1399, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1399 = VMULLuv8i16 4594 { 1400, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1400 = VMULS 4595 { 1401, 5, 1, 455, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1401 = VMULfd 4596 { 1402, 5, 1, 456, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1402 = VMULfq 4597 { 1403, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1403 = VMULpd 4598 { 1404, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1404 = VMULpq 4599 { 1405, 6, 1, 458, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1405 = VMULslfd 4600 { 1406, 6, 1, 459, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1406 = VMULslfq 4601 { 1407, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1407 = VMULslv2i32 4602 { 1408, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1408 = VMULslv4i16 4603 { 1409, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1409 = VMULslv4i32 4604 { 1410, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1410 = VMULslv8i16 4605 { 1411, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1411 = VMULv16i8 4606 { 1412, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1412 = VMULv2i32 4607 { 1413, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1413 = VMULv4i16 4608 { 1414, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1414 = VMULv4i32 4609 { 1415, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1415 = VMULv8i16 4610 { 1416, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1416 = VMULv8i8 4611 { 1417, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1417 = VMVNd 4612 { 1418, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1418 = VMVNq 4613 { 1419, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1419 = VMVNv2i32 4614 { 1420, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1420 = VMVNv4i16 4615 { 1421, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1421 = VMVNv4i32 4616 { 1422, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1422 = VMVNv8i16 4617 { 1423, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1423 = VNEGD 4618 { 1424, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1424 = VNEGS 4619 { 1425, 4, 1, 390, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1425 = VNEGf32q 4620 { 1426, 4, 1, 391, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1426 = VNEGfd 4621 { 1427, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1427 = VNEGs16d 4622 { 1428, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1428 = VNEGs16q 4623 { 1429, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1429 = VNEGs32d 4624 { 1430, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1430 = VNEGs32q 4625 { 1431, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1431 = VNEGs8d 4626 { 1432, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1432 = VNEGs8q 4627 { 1433, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1433 = VNMLAD 4628 { 1434, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1434 = VNMLAS 4629 { 1435, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1435 = VNMLSD 4630 { 1436, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1436 = VNMLSS 4631 { 1437, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1437 = VNMULD 4632 { 1438, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1438 = VNMULS 4633 { 1439, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1439 = VORNd 4634 { 1440, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1440 = VORNq 4635 { 1441, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1441 = VORRd 4636 { 1442, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1442 = VORRiv2i32 4637 { 1443, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1443 = VORRiv4i16 4638 { 1444, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1444 = VORRiv4i32 4639 { 1445, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1445 = VORRiv8i16 4640 { 1446, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1446 = VORRq 4641 { 1447, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1447 = VPADALsv16i8 4642 { 1448, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1448 = VPADALsv2i32 4643 { 1449, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1449 = VPADALsv4i16 4644 { 1450, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1450 = VPADALsv4i32 4645 { 1451, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1451 = VPADALsv8i16 4646 { 1452, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1452 = VPADALsv8i8 4647 { 1453, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1453 = VPADALuv16i8 4648 { 1454, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1454 = VPADALuv2i32 4649 { 1455, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1455 = VPADALuv4i16 4650 { 1456, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1456 = VPADALuv4i32 4651 { 1457, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1457 = VPADALuv8i16 4652 { 1458, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1458 = VPADALuv8i8 4653 { 1459, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1459 = VPADDLsv16i8 4654 { 1460, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1460 = VPADDLsv2i32 4655 { 1461, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1461 = VPADDLsv4i16 4656 { 1462, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1462 = VPADDLsv4i32 4657 { 1463, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1463 = VPADDLsv8i16 4658 { 1464, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1464 = VPADDLsv8i8 4659 { 1465, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1465 = VPADDLuv16i8 4660 { 1466, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1466 = VPADDLuv2i32 4661 { 1467, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1467 = VPADDLuv4i16 4662 { 1468, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1468 = VPADDLuv4i32 4663 { 1469, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1469 = VPADDLuv8i16 4664 { 1470, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1470 = VPADDLuv8i8 4665 { 1471, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1471 = VPADDf 4666 { 1472, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1472 = VPADDi16 4667 { 1473, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1473 = VPADDi32 4668 { 1474, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1474 = VPADDi8 4669 { 1475, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1475 = VPMAXf 4670 { 1476, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1476 = VPMAXs16 4671 { 1477, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1477 = VPMAXs32 4672 { 1478, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1478 = VPMAXs8 4673 { 1479, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1479 = VPMAXu16 4674 { 1480, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1480 = VPMAXu32 4675 { 1481, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1481 = VPMAXu8 4676 { 1482, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1482 = VPMINf 4677 { 1483, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1483 = VPMINs16 4678 { 1484, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1484 = VPMINs32 4679 { 1485, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1485 = VPMINs8 4680 { 1486, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1486 = VPMINu16 4681 { 1487, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1487 = VPMINu32 4682 { 1488, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1488 = VPMINu8 4683 { 1489, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1489 = VQABSv16i8 4684 { 1490, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1490 = VQABSv2i32 4685 { 1491, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1491 = VQABSv4i16 4686 { 1492, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1492 = VQABSv4i32 4687 { 1493, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1493 = VQABSv8i16 4688 { 1494, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1494 = VQABSv8i8 4689 { 1495, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1495 = VQADDsv16i8 4690 { 1496, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1496 = VQADDsv1i64 4691 { 1497, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1497 = VQADDsv2i32 4692 { 1498, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1498 = VQADDsv2i64 4693 { 1499, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1499 = VQADDsv4i16 4694 { 1500, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1500 = VQADDsv4i32 4695 { 1501, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1501 = VQADDsv8i16 4696 { 1502, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1502 = VQADDsv8i8 4697 { 1503, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1503 = VQADDuv16i8 4698 { 1504, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1504 = VQADDuv1i64 4699 { 1505, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1505 = VQADDuv2i32 4700 { 1506, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1506 = VQADDuv2i64 4701 { 1507, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1507 = VQADDuv4i16 4702 { 1508, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1508 = VQADDuv4i32 4703 { 1509, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1509 = VQADDuv8i16 4704 { 1510, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1510 = VQADDuv8i8 4705 { 1511, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1511 = VQDMLALslv2i32 4706 { 1512, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1512 = VQDMLALslv4i16 4707 { 1513, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1513 = VQDMLALv2i64 4708 { 1514, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1514 = VQDMLALv4i32 4709 { 1515, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1515 = VQDMLSLslv2i32 4710 { 1516, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1516 = VQDMLSLslv4i16 4711 { 1517, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1517 = VQDMLSLv2i64 4712 { 1518, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1518 = VQDMLSLv4i32 4713 { 1519, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1519 = VQDMULHslv2i32 4714 { 1520, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1520 = VQDMULHslv4i16 4715 { 1521, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1521 = VQDMULHslv4i32 4716 { 1522, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1522 = VQDMULHslv8i16 4717 { 1523, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1523 = VQDMULHv2i32 4718 { 1524, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1524 = VQDMULHv4i16 4719 { 1525, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1525 = VQDMULHv4i32 4720 { 1526, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1526 = VQDMULHv8i16 4721 { 1527, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1527 = VQDMULLslv2i32 4722 { 1528, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1528 = VQDMULLslv4i16 4723 { 1529, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1529 = VQDMULLv2i64 4724 { 1530, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1530 = VQDMULLv4i32 4725 { 1531, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1531 = VQMOVNsuv2i32 4726 { 1532, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1532 = VQMOVNsuv4i16 4727 { 1533, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1533 = VQMOVNsuv8i8 4728 { 1534, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1534 = VQMOVNsv2i32 4729 { 1535, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1535 = VQMOVNsv4i16 4730 { 1536, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1536 = VQMOVNsv8i8 4731 { 1537, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1537 = VQMOVNuv2i32 4732 { 1538, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1538 = VQMOVNuv4i16 4733 { 1539, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1539 = VQMOVNuv8i8 4734 { 1540, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1540 = VQNEGv16i8 4735 { 1541, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1541 = VQNEGv2i32 4736 { 1542, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1542 = VQNEGv4i16 4737 { 1543, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1543 = VQNEGv4i32 4738 { 1544, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1544 = VQNEGv8i16 4739 { 1545, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1545 = VQNEGv8i8 4740 { 1546, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1546 = VQRDMULHslv2i32 4741 { 1547, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1547 = VQRDMULHslv4i16 4742 { 1548, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1548 = VQRDMULHslv4i32 4743 { 1549, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1549 = VQRDMULHslv8i16 4744 { 1550, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1550 = VQRDMULHv2i32 4745 { 1551, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1551 = VQRDMULHv4i16 4746 { 1552, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1552 = VQRDMULHv4i32 4747 { 1553, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1553 = VQRDMULHv8i16 4748 { 1554, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1554 = VQRSHLsv16i8 4749 { 1555, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1555 = VQRSHLsv1i64 4750 { 1556, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1556 = VQRSHLsv2i32 4751 { 1557, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1557 = VQRSHLsv2i64 4752 { 1558, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1558 = VQRSHLsv4i16 4753 { 1559, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1559 = VQRSHLsv4i32 4754 { 1560, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1560 = VQRSHLsv8i16 4755 { 1561, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1561 = VQRSHLsv8i8 4756 { 1562, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1562 = VQRSHLuv16i8 4757 { 1563, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1563 = VQRSHLuv1i64 4758 { 1564, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1564 = VQRSHLuv2i32 4759 { 1565, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1565 = VQRSHLuv2i64 4760 { 1566, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1566 = VQRSHLuv4i16 4761 { 1567, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1567 = VQRSHLuv4i32 4762 { 1568, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1568 = VQRSHLuv8i16 4763 { 1569, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1569 = VQRSHLuv8i8 4764 { 1570, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1570 = VQRSHRNsv2i32 4765 { 1571, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1571 = VQRSHRNsv4i16 4766 { 1572, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1572 = VQRSHRNsv8i8 4767 { 1573, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1573 = VQRSHRNuv2i32 4768 { 1574, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1574 = VQRSHRNuv4i16 4769 { 1575, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1575 = VQRSHRNuv8i8 4770 { 1576, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1576 = VQRSHRUNv2i32 4771 { 1577, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1577 = VQRSHRUNv4i16 4772 { 1578, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1578 = VQRSHRUNv8i8 4773 { 1579, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1579 = VQSHLsiv16i8 4774 { 1580, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1580 = VQSHLsiv1i64 4775 { 1581, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1581 = VQSHLsiv2i32 4776 { 1582, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1582 = VQSHLsiv2i64 4777 { 1583, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1583 = VQSHLsiv4i16 4778 { 1584, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1584 = VQSHLsiv4i32 4779 { 1585, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1585 = VQSHLsiv8i16 4780 { 1586, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1586 = VQSHLsiv8i8 4781 { 1587, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1587 = VQSHLsuv16i8 4782 { 1588, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1588 = VQSHLsuv1i64 4783 { 1589, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1589 = VQSHLsuv2i32 4784 { 1590, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1590 = VQSHLsuv2i64 4785 { 1591, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1591 = VQSHLsuv4i16 4786 { 1592, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1592 = VQSHLsuv4i32 4787 { 1593, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1593 = VQSHLsuv8i16 4788 { 1594, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1594 = VQSHLsuv8i8 4789 { 1595, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1595 = VQSHLsv16i8 4790 { 1596, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1596 = VQSHLsv1i64 4791 { 1597, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1597 = VQSHLsv2i32 4792 { 1598, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1598 = VQSHLsv2i64 4793 { 1599, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1599 = VQSHLsv4i16 4794 { 1600, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1600 = VQSHLsv4i32 4795 { 1601, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1601 = VQSHLsv8i16 4796 { 1602, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1602 = VQSHLsv8i8 4797 { 1603, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1603 = VQSHLuiv16i8 4798 { 1604, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1604 = VQSHLuiv1i64 4799 { 1605, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1605 = VQSHLuiv2i32 4800 { 1606, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1606 = VQSHLuiv2i64 4801 { 1607, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1607 = VQSHLuiv4i16 4802 { 1608, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1608 = VQSHLuiv4i32 4803 { 1609, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1609 = VQSHLuiv8i16 4804 { 1610, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1610 = VQSHLuiv8i8 4805 { 1611, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1611 = VQSHLuv16i8 4806 { 1612, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1612 = VQSHLuv1i64 4807 { 1613, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1613 = VQSHLuv2i32 4808 { 1614, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1614 = VQSHLuv2i64 4809 { 1615, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1615 = VQSHLuv4i16 4810 { 1616, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1616 = VQSHLuv4i32 4811 { 1617, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1617 = VQSHLuv8i16 4812 { 1618, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1618 = VQSHLuv8i8 4813 { 1619, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1619 = VQSHRNsv2i32 4814 { 1620, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1620 = VQSHRNsv4i16 4815 { 1621, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1621 = VQSHRNsv8i8 4816 { 1622, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1622 = VQSHRNuv2i32 4817 { 1623, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1623 = VQSHRNuv4i16 4818 { 1624, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1624 = VQSHRNuv8i8 4819 { 1625, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1625 = VQSHRUNv2i32 4820 { 1626, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1626 = VQSHRUNv4i16 4821 { 1627, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1627 = VQSHRUNv8i8 4822 { 1628, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1628 = VQSUBsv16i8 4823 { 1629, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1629 = VQSUBsv1i64 4824 { 1630, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1630 = VQSUBsv2i32 4825 { 1631, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1631 = VQSUBsv2i64 4826 { 1632, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1632 = VQSUBsv4i16 4827 { 1633, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1633 = VQSUBsv4i32 4828 { 1634, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1634 = VQSUBsv8i16 4829 { 1635, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1635 = VQSUBsv8i8 4830 { 1636, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1636 = VQSUBuv16i8 4831 { 1637, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1637 = VQSUBuv1i64 4832 { 1638, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1638 = VQSUBuv2i32 4833 { 1639, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1639 = VQSUBuv2i64 4834 { 1640, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1640 = VQSUBuv4i16 4835 { 1641, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1641 = VQSUBuv4i32 4836 { 1642, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1642 = VQSUBuv8i16 4837 { 1643, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1643 = VQSUBuv8i8 4838 { 1644, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1644 = VRADDHNv2i32 4839 { 1645, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1645 = VRADDHNv4i16 4840 { 1646, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1646 = VRADDHNv8i8 4841 { 1647, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1647 = VRECPEd 4842 { 1648, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1648 = VRECPEfd 4843 { 1649, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1649 = VRECPEfq 4844 { 1650, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1650 = VRECPEq 4845 { 1651, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1651 = VRECPSfd 4846 { 1652, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1652 = VRECPSfq 4847 { 1653, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1653 = VREV16d8 4848 { 1654, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1654 = VREV16q8 4849 { 1655, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1655 = VREV32d16 4850 { 1656, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1656 = VREV32d8 4851 { 1657, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1657 = VREV32q16 4852 { 1658, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1658 = VREV32q8 4853 { 1659, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1659 = VREV64d16 4854 { 1660, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1660 = VREV64d32 4855 { 1661, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1661 = VREV64d8 4856 { 1662, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1662 = VREV64q16 4857 { 1663, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1663 = VREV64q32 4858 { 1664, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1664 = VREV64q8 4859 { 1665, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1665 = VRHADDsv16i8 4860 { 1666, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1666 = VRHADDsv2i32 4861 { 1667, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1667 = VRHADDsv4i16 4862 { 1668, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1668 = VRHADDsv4i32 4863 { 1669, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1669 = VRHADDsv8i16 4864 { 1670, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1670 = VRHADDsv8i8 4865 { 1671, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1671 = VRHADDuv16i8 4866 { 1672, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1672 = VRHADDuv2i32 4867 { 1673, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1673 = VRHADDuv4i16 4868 { 1674, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1674 = VRHADDuv4i32 4869 { 1675, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1675 = VRHADDuv8i16 4870 { 1676, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1676 = VRHADDuv8i8 4871 { 1677, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1677 = VRINTAD 4872 { 1678, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1678 = VRINTAND 4873 { 1679, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1679 = VRINTANQ 4874 { 1680, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1680 = VRINTAS 4875 { 1681, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1681 = VRINTMD 4876 { 1682, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1682 = VRINTMND 4877 { 1683, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1683 = VRINTMNQ 4878 { 1684, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1684 = VRINTMS 4879 { 1685, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1685 = VRINTND 4880 { 1686, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1686 = VRINTNND 4881 { 1687, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1687 = VRINTNNQ 4882 { 1688, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1688 = VRINTNS 4883 { 1689, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1689 = VRINTPD 4884 { 1690, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1690 = VRINTPND 4885 { 1691, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1691 = VRINTPNQ 4886 { 1692, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1692 = VRINTPS 4887 { 1693, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1693 = VRINTRD 4888 { 1694, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1694 = VRINTRS 4889 { 1695, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1695 = VRINTXD 4890 { 1696, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1696 = VRINTXND 4891 { 1697, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1697 = VRINTXNQ 4892 { 1698, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1698 = VRINTXS 4893 { 1699, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1699 = VRINTZD 4894 { 1700, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1700 = VRINTZND 4895 { 1701, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1701 = VRINTZNQ 4896 { 1702, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1702 = VRINTZS 4897 { 1703, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1703 = VRSHLsv16i8 4898 { 1704, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1704 = VRSHLsv1i64 4899 { 1705, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1705 = VRSHLsv2i32 4900 { 1706, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1706 = VRSHLsv2i64 4901 { 1707, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1707 = VRSHLsv4i16 4902 { 1708, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1708 = VRSHLsv4i32 4903 { 1709, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1709 = VRSHLsv8i16 4904 { 1710, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1710 = VRSHLsv8i8 4905 { 1711, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1711 = VRSHLuv16i8 4906 { 1712, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1712 = VRSHLuv1i64 4907 { 1713, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1713 = VRSHLuv2i32 4908 { 1714, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1714 = VRSHLuv2i64 4909 { 1715, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1715 = VRSHLuv4i16 4910 { 1716, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1716 = VRSHLuv4i32 4911 { 1717, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1717 = VRSHLuv8i16 4912 { 1718, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1718 = VRSHLuv8i8 4913 { 1719, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1719 = VRSHRNv2i32 4914 { 1720, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1720 = VRSHRNv4i16 4915 { 1721, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1721 = VRSHRNv8i8 4916 { 1722, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1722 = VRSHRsv16i8 4917 { 1723, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1723 = VRSHRsv1i64 4918 { 1724, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1724 = VRSHRsv2i32 4919 { 1725, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1725 = VRSHRsv2i64 4920 { 1726, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1726 = VRSHRsv4i16 4921 { 1727, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1727 = VRSHRsv4i32 4922 { 1728, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1728 = VRSHRsv8i16 4923 { 1729, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1729 = VRSHRsv8i8 4924 { 1730, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1730 = VRSHRuv16i8 4925 { 1731, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1731 = VRSHRuv1i64 4926 { 1732, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1732 = VRSHRuv2i32 4927 { 1733, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1733 = VRSHRuv2i64 4928 { 1734, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1734 = VRSHRuv4i16 4929 { 1735, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1735 = VRSHRuv4i32 4930 { 1736, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1736 = VRSHRuv8i16 4931 { 1737, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1737 = VRSHRuv8i8 4932 { 1738, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1738 = VRSQRTEd 4933 { 1739, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1739 = VRSQRTEfd 4934 { 1740, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1740 = VRSQRTEfq 4935 { 1741, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1741 = VRSQRTEq 4936 { 1742, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1742 = VRSQRTSfd 4937 { 1743, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1743 = VRSQRTSfq 4938 { 1744, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1744 = VRSRAsv16i8 4939 { 1745, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1745 = VRSRAsv1i64 4940 { 1746, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1746 = VRSRAsv2i32 4941 { 1747, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1747 = VRSRAsv2i64 4942 { 1748, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1748 = VRSRAsv4i16 4943 { 1749, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1749 = VRSRAsv4i32 4944 { 1750, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1750 = VRSRAsv8i16 4945 { 1751, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1751 = VRSRAsv8i8 4946 { 1752, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1752 = VRSRAuv16i8 4947 { 1753, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1753 = VRSRAuv1i64 4948 { 1754, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1754 = VRSRAuv2i32 4949 { 1755, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1755 = VRSRAuv2i64 4950 { 1756, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1756 = VRSRAuv4i16 4951 { 1757, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1757 = VRSRAuv4i32 4952 { 1758, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1758 = VRSRAuv8i16 4953 { 1759, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1759 = VRSRAuv8i8 4954 { 1760, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1760 = VRSUBHNv2i32 4955 { 1761, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1761 = VRSUBHNv4i16 4956 { 1762, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1762 = VRSUBHNv8i8 4957 { 1763, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1763 = VSELEQD 4958 { 1764, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1764 = VSELEQS 4959 { 1765, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1765 = VSELGED 4960 { 1766, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1766 = VSELGES 4961 { 1767, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1767 = VSELGTD 4962 { 1768, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1768 = VSELGTS 4963 { 1769, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1769 = VSELVSD 4964 { 1770, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1770 = VSELVSS 4965 { 1771, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1771 = VSETLNi16 4966 { 1772, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1772 = VSETLNi32 4967 { 1773, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1773 = VSETLNi8 4968 { 1774, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1774 = VSHLLi16 4969 { 1775, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1775 = VSHLLi32 4970 { 1776, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1776 = VSHLLi8 4971 { 1777, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1777 = VSHLLsv2i64 4972 { 1778, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1778 = VSHLLsv4i32 4973 { 1779, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1779 = VSHLLsv8i16 4974 { 1780, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1780 = VSHLLuv2i64 4975 { 1781, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1781 = VSHLLuv4i32 4976 { 1782, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1782 = VSHLLuv8i16 4977 { 1783, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1783 = VSHLiv16i8 4978 { 1784, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1784 = VSHLiv1i64 4979 { 1785, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1785 = VSHLiv2i32 4980 { 1786, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1786 = VSHLiv2i64 4981 { 1787, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1787 = VSHLiv4i16 4982 { 1788, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1788 = VSHLiv4i32 4983 { 1789, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1789 = VSHLiv8i16 4984 { 1790, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1790 = VSHLiv8i8 4985 { 1791, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1791 = VSHLsv16i8 4986 { 1792, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1792 = VSHLsv1i64 4987 { 1793, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1793 = VSHLsv2i32 4988 { 1794, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1794 = VSHLsv2i64 4989 { 1795, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1795 = VSHLsv4i16 4990 { 1796, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1796 = VSHLsv4i32 4991 { 1797, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1797 = VSHLsv8i16 4992 { 1798, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1798 = VSHLsv8i8 4993 { 1799, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1799 = VSHLuv16i8 4994 { 1800, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1800 = VSHLuv1i64 4995 { 1801, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1801 = VSHLuv2i32 4996 { 1802, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1802 = VSHLuv2i64 4997 { 1803, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1803 = VSHLuv4i16 4998 { 1804, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1804 = VSHLuv4i32 4999 { 1805, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1805 = VSHLuv8i16 5000 { 1806, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1806 = VSHLuv8i8 5001 { 1807, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1807 = VSHRNv2i32 5002 { 1808, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1808 = VSHRNv4i16 5003 { 1809, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1809 = VSHRNv8i8 5004 { 1810, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1810 = VSHRsv16i8 5005 { 1811, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1811 = VSHRsv1i64 5006 { 1812, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1812 = VSHRsv2i32 5007 { 1813, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1813 = VSHRsv2i64 5008 { 1814, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1814 = VSHRsv4i16 5009 { 1815, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1815 = VSHRsv4i32 5010 { 1816, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1816 = VSHRsv8i16 5011 { 1817, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1817 = VSHRsv8i8 5012 { 1818, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1818 = VSHRuv16i8 5013 { 1819, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1819 = VSHRuv1i64 5014 { 1820, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1820 = VSHRuv2i32 5015 { 1821, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1821 = VSHRuv2i64 5016 { 1822, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1822 = VSHRuv4i16 5017 { 1823, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1823 = VSHRuv4i32 5018 { 1824, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1824 = VSHRuv8i16 5019 { 1825, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1825 = VSHRuv8i8 5020 { 1826, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1826 = VSHTOD 5021 { 1827, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1827 = VSHTOS 5022 { 1828, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1828 = VSITOD 5023 { 1829, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1829 = VSITOS 5024 { 1830, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1830 = VSLIv16i8 5025 { 1831, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1831 = VSLIv1i64 5026 { 1832, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1832 = VSLIv2i32 5027 { 1833, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1833 = VSLIv2i64 5028 { 1834, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1834 = VSLIv4i16 5029 { 1835, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1835 = VSLIv4i32 5030 { 1836, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1836 = VSLIv8i16 5031 { 1837, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1837 = VSLIv8i8 5032 { 1838, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1838 = VSLTOD 5033 { 1839, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1839 = VSLTOS 5034 { 1840, 4, 1, 589, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1840 = VSQRTD 5035 { 1841, 4, 1, 587, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1841 = VSQRTS 5036 { 1842, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1842 = VSRAsv16i8 5037 { 1843, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1843 = VSRAsv1i64 5038 { 1844, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1844 = VSRAsv2i32 5039 { 1845, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1845 = VSRAsv2i64 5040 { 1846, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1846 = VSRAsv4i16 5041 { 1847, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1847 = VSRAsv4i32 5042 { 1848, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1848 = VSRAsv8i16 5043 { 1849, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1849 = VSRAsv8i8 5044 { 1850, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1850 = VSRAuv16i8 5045 { 1851, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1851 = VSRAuv1i64 5046 { 1852, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1852 = VSRAuv2i32 5047 { 1853, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1853 = VSRAuv2i64 5048 { 1854, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1854 = VSRAuv4i16 5049 { 1855, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1855 = VSRAuv4i32 5050 { 1856, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1856 = VSRAuv8i16 5051 { 1857, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1857 = VSRAuv8i8 5052 { 1858, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1858 = VSRIv16i8 5053 { 1859, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1859 = VSRIv1i64 5054 { 1860, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1860 = VSRIv2i32 5055 { 1861, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1861 = VSRIv2i64 5056 { 1862, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1862 = VSRIv4i16 5057 { 1863, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1863 = VSRIv4i32 5058 { 1864, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1864 = VSRIv8i16 5059 { 1865, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1865 = VSRIv8i8 5060 { 1866, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1866 = VST1LNd16 5061 { 1867, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1867 = VST1LNd16_UPD 5062 { 1868, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1868 = VST1LNd32 5063 { 1869, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1869 = VST1LNd32_UPD 5064 { 1870, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1870 = VST1LNd8 5065 { 1871, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1871 = VST1LNd8_UPD 5066 { 1872, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1872 = VST1LNdAsm_16 5067 { 1873, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1873 = VST1LNdAsm_32 5068 { 1874, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1874 = VST1LNdAsm_8 5069 { 1875, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1875 = VST1LNdWB_fixed_Asm_16 5070 { 1876, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1876 = VST1LNdWB_fixed_Asm_32 5071 { 1877, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1877 = VST1LNdWB_fixed_Asm_8 5072 { 1878, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1878 = VST1LNdWB_register_Asm_16 5073 { 1879, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1879 = VST1LNdWB_register_Asm_32 5074 { 1880, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1880 = VST1LNdWB_register_Asm_8 5075 { 1881, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1881 = VST1LNq16Pseudo 5076 { 1882, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1882 = VST1LNq16Pseudo_UPD 5077 { 1883, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1883 = VST1LNq32Pseudo 5078 { 1884, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1884 = VST1LNq32Pseudo_UPD 5079 { 1885, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1885 = VST1LNq8Pseudo 5080 { 1886, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1886 = VST1LNq8Pseudo_UPD 5081 { 1887, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1887 = VST1d16 5082 { 1888, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1888 = VST1d16Q 5083 { 1889, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1889 = VST1d16Qwb_fixed 5084 { 1890, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1890 = VST1d16Qwb_register 5085 { 1891, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1891 = VST1d16T 5086 { 1892, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1892 = VST1d16Twb_fixed 5087 { 1893, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1893 = VST1d16Twb_register 5088 { 1894, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1894 = VST1d16wb_fixed 5089 { 1895, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1895 = VST1d16wb_register 5090 { 1896, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1896 = VST1d32 5091 { 1897, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1897 = VST1d32Q 5092 { 1898, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1898 = VST1d32Qwb_fixed 5093 { 1899, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1899 = VST1d32Qwb_register 5094 { 1900, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1900 = VST1d32T 5095 { 1901, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1901 = VST1d32Twb_fixed 5096 { 1902, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1902 = VST1d32Twb_register 5097 { 1903, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1903 = VST1d32wb_fixed 5098 { 1904, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1904 = VST1d32wb_register 5099 { 1905, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1905 = VST1d64 5100 { 1906, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1906 = VST1d64Q 5101 { 1907, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1907 = VST1d64QPseudo 5102 { 1908, 6, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1908 = VST1d64QPseudoWB_fixed 5103 { 1909, 7, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1909 = VST1d64QPseudoWB_register 5104 { 1910, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1910 = VST1d64Qwb_fixed 5105 { 1911, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1911 = VST1d64Qwb_register 5106 { 1912, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1912 = VST1d64T 5107 { 1913, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1913 = VST1d64TPseudo 5108 { 1914, 6, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1914 = VST1d64TPseudoWB_fixed 5109 { 1915, 7, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1915 = VST1d64TPseudoWB_register 5110 { 1916, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1916 = VST1d64Twb_fixed 5111 { 1917, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1917 = VST1d64Twb_register 5112 { 1918, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1918 = VST1d64wb_fixed 5113 { 1919, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1919 = VST1d64wb_register 5114 { 1920, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1920 = VST1d8 5115 { 1921, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1921 = VST1d8Q 5116 { 1922, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1922 = VST1d8Qwb_fixed 5117 { 1923, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1923 = VST1d8Qwb_register 5118 { 1924, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1924 = VST1d8T 5119 { 1925, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1925 = VST1d8Twb_fixed 5120 { 1926, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1926 = VST1d8Twb_register 5121 { 1927, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1927 = VST1d8wb_fixed 5122 { 1928, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1928 = VST1d8wb_register 5123 { 1929, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1929 = VST1q16 5124 { 1930, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1930 = VST1q16wb_fixed 5125 { 1931, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1931 = VST1q16wb_register 5126 { 1932, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1932 = VST1q32 5127 { 1933, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1933 = VST1q32wb_fixed 5128 { 1934, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1934 = VST1q32wb_register 5129 { 1935, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1935 = VST1q64 5130 { 1936, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1936 = VST1q64wb_fixed 5131 { 1937, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1937 = VST1q64wb_register 5132 { 1938, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1938 = VST1q8 5133 { 1939, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1939 = VST1q8wb_fixed 5134 { 1940, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1940 = VST1q8wb_register 5135 { 1941, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1941 = VST2LNd16 5136 { 1942, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1942 = VST2LNd16Pseudo 5137 { 1943, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1943 = VST2LNd16Pseudo_UPD 5138 { 1944, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1944 = VST2LNd16_UPD 5139 { 1945, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1945 = VST2LNd32 5140 { 1946, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1946 = VST2LNd32Pseudo 5141 { 1947, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1947 = VST2LNd32Pseudo_UPD 5142 { 1948, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1948 = VST2LNd32_UPD 5143 { 1949, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1949 = VST2LNd8 5144 { 1950, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1950 = VST2LNd8Pseudo 5145 { 1951, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1951 = VST2LNd8Pseudo_UPD 5146 { 1952, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1952 = VST2LNd8_UPD 5147 { 1953, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1953 = VST2LNdAsm_16 5148 { 1954, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1954 = VST2LNdAsm_32 5149 { 1955, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1955 = VST2LNdAsm_8 5150 { 1956, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1956 = VST2LNdWB_fixed_Asm_16 5151 { 1957, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1957 = VST2LNdWB_fixed_Asm_32 5152 { 1958, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1958 = VST2LNdWB_fixed_Asm_8 5153 { 1959, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1959 = VST2LNdWB_register_Asm_16 5154 { 1960, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1960 = VST2LNdWB_register_Asm_32 5155 { 1961, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1961 = VST2LNdWB_register_Asm_8 5156 { 1962, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1962 = VST2LNq16 5157 { 1963, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1963 = VST2LNq16Pseudo 5158 { 1964, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1964 = VST2LNq16Pseudo_UPD 5159 { 1965, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1965 = VST2LNq16_UPD 5160 { 1966, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1966 = VST2LNq32 5161 { 1967, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1967 = VST2LNq32Pseudo 5162 { 1968, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1968 = VST2LNq32Pseudo_UPD 5163 { 1969, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1969 = VST2LNq32_UPD 5164 { 1970, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1970 = VST2LNqAsm_16 5165 { 1971, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1971 = VST2LNqAsm_32 5166 { 1972, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1972 = VST2LNqWB_fixed_Asm_16 5167 { 1973, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1973 = VST2LNqWB_fixed_Asm_32 5168 { 1974, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1974 = VST2LNqWB_register_Asm_16 5169 { 1975, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1975 = VST2LNqWB_register_Asm_32 5170 { 1976, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1976 = VST2b16 5171 { 1977, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1977 = VST2b16wb_fixed 5172 { 1978, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1978 = VST2b16wb_register 5173 { 1979, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1979 = VST2b32 5174 { 1980, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1980 = VST2b32wb_fixed 5175 { 1981, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1981 = VST2b32wb_register 5176 { 1982, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1982 = VST2b8 5177 { 1983, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1983 = VST2b8wb_fixed 5178 { 1984, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1984 = VST2b8wb_register 5179 { 1985, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1985 = VST2d16 5180 { 1986, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1986 = VST2d16wb_fixed 5181 { 1987, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1987 = VST2d16wb_register 5182 { 1988, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1988 = VST2d32 5183 { 1989, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1989 = VST2d32wb_fixed 5184 { 1990, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1990 = VST2d32wb_register 5185 { 1991, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1991 = VST2d8 5186 { 1992, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1992 = VST2d8wb_fixed 5187 { 1993, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1993 = VST2d8wb_register 5188 { 1994, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1994 = VST2q16 5189 { 1995, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1995 = VST2q16Pseudo 5190 { 1996, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1996 = VST2q16PseudoWB_fixed 5191 { 1997, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1997 = VST2q16PseudoWB_register 5192 { 1998, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1998 = VST2q16wb_fixed 5193 { 1999, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1999 = VST2q16wb_register 5194 { 2000, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #2000 = VST2q32 5195 { 2001, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2001 = VST2q32Pseudo 5196 { 2002, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2002 = VST2q32PseudoWB_fixed 5197 { 2003, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #2003 = VST2q32PseudoWB_register 5198 { 2004, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #2004 = VST2q32wb_fixed 5199 { 2005, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #2005 = VST2q32wb_register 5200 { 2006, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #2006 = VST2q8 5201 { 2007, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2007 = VST2q8Pseudo 5202 { 2008, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2008 = VST2q8PseudoWB_fixed 5203 { 2009, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #2009 = VST2q8PseudoWB_register 5204 { 2010, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #2010 = VST2q8wb_fixed 5205 { 2011, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #2011 = VST2q8wb_register 5206 { 2012, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2012 = VST3LNd16 5207 { 2013, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2013 = VST3LNd16Pseudo 5208 { 2014, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2014 = VST3LNd16Pseudo_UPD 5209 { 2015, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2015 = VST3LNd16_UPD 5210 { 2016, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2016 = VST3LNd32 5211 { 2017, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2017 = VST3LNd32Pseudo 5212 { 2018, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2018 = VST3LNd32Pseudo_UPD 5213 { 2019, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2019 = VST3LNd32_UPD 5214 { 2020, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2020 = VST3LNd8 5215 { 2021, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2021 = VST3LNd8Pseudo 5216 { 2022, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2022 = VST3LNd8Pseudo_UPD 5217 { 2023, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2023 = VST3LNd8_UPD 5218 { 2024, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2024 = VST3LNdAsm_16 5219 { 2025, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2025 = VST3LNdAsm_32 5220 { 2026, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2026 = VST3LNdAsm_8 5221 { 2027, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2027 = VST3LNdWB_fixed_Asm_16 5222 { 2028, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2028 = VST3LNdWB_fixed_Asm_32 5223 { 2029, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2029 = VST3LNdWB_fixed_Asm_8 5224 { 2030, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2030 = VST3LNdWB_register_Asm_16 5225 { 2031, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2031 = VST3LNdWB_register_Asm_32 5226 { 2032, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2032 = VST3LNdWB_register_Asm_8 5227 { 2033, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2033 = VST3LNq16 5228 { 2034, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2034 = VST3LNq16Pseudo 5229 { 2035, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2035 = VST3LNq16Pseudo_UPD 5230 { 2036, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2036 = VST3LNq16_UPD 5231 { 2037, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2037 = VST3LNq32 5232 { 2038, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2038 = VST3LNq32Pseudo 5233 { 2039, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2039 = VST3LNq32Pseudo_UPD 5234 { 2040, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2040 = VST3LNq32_UPD 5235 { 2041, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2041 = VST3LNqAsm_16 5236 { 2042, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2042 = VST3LNqAsm_32 5237 { 2043, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2043 = VST3LNqWB_fixed_Asm_16 5238 { 2044, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2044 = VST3LNqWB_fixed_Asm_32 5239 { 2045, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2045 = VST3LNqWB_register_Asm_16 5240 { 2046, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2046 = VST3LNqWB_register_Asm_32 5241 { 2047, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2047 = VST3d16 5242 { 2048, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2048 = VST3d16Pseudo 5243 { 2049, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2049 = VST3d16Pseudo_UPD 5244 { 2050, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2050 = VST3d16_UPD 5245 { 2051, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2051 = VST3d32 5246 { 2052, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2052 = VST3d32Pseudo 5247 { 2053, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2053 = VST3d32Pseudo_UPD 5248 { 2054, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2054 = VST3d32_UPD 5249 { 2055, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2055 = VST3d8 5250 { 2056, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2056 = VST3d8Pseudo 5251 { 2057, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2057 = VST3d8Pseudo_UPD 5252 { 2058, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2058 = VST3d8_UPD 5253 { 2059, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2059 = VST3dAsm_16 5254 { 2060, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2060 = VST3dAsm_32 5255 { 2061, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2061 = VST3dAsm_8 5256 { 2062, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2062 = VST3dWB_fixed_Asm_16 5257 { 2063, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2063 = VST3dWB_fixed_Asm_32 5258 { 2064, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2064 = VST3dWB_fixed_Asm_8 5259 { 2065, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2065 = VST3dWB_register_Asm_16 5260 { 2066, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2066 = VST3dWB_register_Asm_32 5261 { 2067, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2067 = VST3dWB_register_Asm_8 5262 { 2068, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2068 = VST3q16 5263 { 2069, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2069 = VST3q16Pseudo_UPD 5264 { 2070, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2070 = VST3q16_UPD 5265 { 2071, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2071 = VST3q16oddPseudo 5266 { 2072, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2072 = VST3q16oddPseudo_UPD 5267 { 2073, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2073 = VST3q32 5268 { 2074, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2074 = VST3q32Pseudo_UPD 5269 { 2075, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2075 = VST3q32_UPD 5270 { 2076, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2076 = VST3q32oddPseudo 5271 { 2077, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2077 = VST3q32oddPseudo_UPD 5272 { 2078, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2078 = VST3q8 5273 { 2079, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2079 = VST3q8Pseudo_UPD 5274 { 2080, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2080 = VST3q8_UPD 5275 { 2081, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2081 = VST3q8oddPseudo 5276 { 2082, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2082 = VST3q8oddPseudo_UPD 5277 { 2083, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2083 = VST3qAsm_16 5278 { 2084, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2084 = VST3qAsm_32 5279 { 2085, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2085 = VST3qAsm_8 5280 { 2086, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2086 = VST3qWB_fixed_Asm_16 5281 { 2087, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2087 = VST3qWB_fixed_Asm_32 5282 { 2088, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2088 = VST3qWB_fixed_Asm_8 5283 { 2089, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2089 = VST3qWB_register_Asm_16 5284 { 2090, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2090 = VST3qWB_register_Asm_32 5285 { 2091, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2091 = VST3qWB_register_Asm_8 5286 { 2092, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2092 = VST4LNd16 5287 { 2093, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2093 = VST4LNd16Pseudo 5288 { 2094, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2094 = VST4LNd16Pseudo_UPD 5289 { 2095, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2095 = VST4LNd16_UPD 5290 { 2096, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2096 = VST4LNd32 5291 { 2097, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2097 = VST4LNd32Pseudo 5292 { 2098, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2098 = VST4LNd32Pseudo_UPD 5293 { 2099, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2099 = VST4LNd32_UPD 5294 { 2100, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2100 = VST4LNd8 5295 { 2101, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2101 = VST4LNd8Pseudo 5296 { 2102, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2102 = VST4LNd8Pseudo_UPD 5297 { 2103, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2103 = VST4LNd8_UPD 5298 { 2104, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2104 = VST4LNdAsm_16 5299 { 2105, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2105 = VST4LNdAsm_32 5300 { 2106, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2106 = VST4LNdAsm_8 5301 { 2107, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2107 = VST4LNdWB_fixed_Asm_16 5302 { 2108, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2108 = VST4LNdWB_fixed_Asm_32 5303 { 2109, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2109 = VST4LNdWB_fixed_Asm_8 5304 { 2110, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2110 = VST4LNdWB_register_Asm_16 5305 { 2111, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2111 = VST4LNdWB_register_Asm_32 5306 { 2112, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2112 = VST4LNdWB_register_Asm_8 5307 { 2113, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2113 = VST4LNq16 5308 { 2114, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2114 = VST4LNq16Pseudo 5309 { 2115, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2115 = VST4LNq16Pseudo_UPD 5310 { 2116, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2116 = VST4LNq16_UPD 5311 { 2117, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2117 = VST4LNq32 5312 { 2118, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2118 = VST4LNq32Pseudo 5313 { 2119, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2119 = VST4LNq32Pseudo_UPD 5314 { 2120, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2120 = VST4LNq32_UPD 5315 { 2121, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2121 = VST4LNqAsm_16 5316 { 2122, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2122 = VST4LNqAsm_32 5317 { 2123, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2123 = VST4LNqWB_fixed_Asm_16 5318 { 2124, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2124 = VST4LNqWB_fixed_Asm_32 5319 { 2125, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2125 = VST4LNqWB_register_Asm_16 5320 { 2126, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2126 = VST4LNqWB_register_Asm_32 5321 { 2127, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2127 = VST4d16 5322 { 2128, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2128 = VST4d16Pseudo 5323 { 2129, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2129 = VST4d16Pseudo_UPD 5324 { 2130, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2130 = VST4d16_UPD 5325 { 2131, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2131 = VST4d32 5326 { 2132, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2132 = VST4d32Pseudo 5327 { 2133, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2133 = VST4d32Pseudo_UPD 5328 { 2134, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2134 = VST4d32_UPD 5329 { 2135, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2135 = VST4d8 5330 { 2136, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2136 = VST4d8Pseudo 5331 { 2137, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2137 = VST4d8Pseudo_UPD 5332 { 2138, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2138 = VST4d8_UPD 5333 { 2139, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2139 = VST4dAsm_16 5334 { 2140, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2140 = VST4dAsm_32 5335 { 2141, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2141 = VST4dAsm_8 5336 { 2142, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2142 = VST4dWB_fixed_Asm_16 5337 { 2143, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2143 = VST4dWB_fixed_Asm_32 5338 { 2144, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2144 = VST4dWB_fixed_Asm_8 5339 { 2145, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2145 = VST4dWB_register_Asm_16 5340 { 2146, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2146 = VST4dWB_register_Asm_32 5341 { 2147, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2147 = VST4dWB_register_Asm_8 5342 { 2148, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2148 = VST4q16 5343 { 2149, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2149 = VST4q16Pseudo_UPD 5344 { 2150, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2150 = VST4q16_UPD 5345 { 2151, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2151 = VST4q16oddPseudo 5346 { 2152, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2152 = VST4q16oddPseudo_UPD 5347 { 2153, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2153 = VST4q32 5348 { 2154, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2154 = VST4q32Pseudo_UPD 5349 { 2155, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2155 = VST4q32_UPD 5350 { 2156, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2156 = VST4q32oddPseudo 5351 { 2157, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2157 = VST4q32oddPseudo_UPD 5352 { 2158, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2158 = VST4q8 5353 { 2159, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2159 = VST4q8Pseudo_UPD 5354 { 2160, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2160 = VST4q8_UPD 5355 { 2161, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2161 = VST4q8oddPseudo 5356 { 2162, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2162 = VST4q8oddPseudo_UPD 5357 { 2163, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2163 = VST4qAsm_16 5358 { 2164, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2164 = VST4qAsm_32 5359 { 2165, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2165 = VST4qAsm_8 5360 { 2166, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2166 = VST4qWB_fixed_Asm_16 5361 { 2167, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2167 = VST4qWB_fixed_Asm_32 5362 { 2168, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2168 = VST4qWB_fixed_Asm_8 5363 { 2169, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2169 = VST4qWB_register_Asm_16 5364 { 2170, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2170 = VST4qWB_register_Asm_32 5365 { 2171, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2171 = VST4qWB_register_Asm_8 5366 { 2172, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2172 = VSTMDDB_UPD 5367 { 2173, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2173 = VSTMDIA 5368 { 2174, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2174 = VSTMDIA_UPD 5369 { 2175, 4, 0, 513, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #2175 = VSTMQIA 5370 { 2176, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2176 = VSTMSDB_UPD 5371 { 2177, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2177 = VSTMSIA 5372 { 2178, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2178 = VSTMSIA_UPD 5373 { 2179, 5, 0, 510, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #2179 = VSTRD 5374 { 2180, 5, 0, 511, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #2180 = VSTRS 5375 { 2181, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2181 = VSUBD 5376 { 2182, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2182 = VSUBHNv2i32 5377 { 2183, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2183 = VSUBHNv4i16 5378 { 2184, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2184 = VSUBHNv8i8 5379 { 2185, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2185 = VSUBLsv2i64 5380 { 2186, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2186 = VSUBLsv4i32 5381 { 2187, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2187 = VSUBLsv8i16 5382 { 2188, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2188 = VSUBLuv2i64 5383 { 2189, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2189 = VSUBLuv4i32 5384 { 2190, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2190 = VSUBLuv8i16 5385 { 2191, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #2191 = VSUBS 5386 { 2192, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2192 = VSUBWsv2i64 5387 { 2193, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2193 = VSUBWsv4i32 5388 { 2194, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2194 = VSUBWsv8i16 5389 { 2195, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2195 = VSUBWuv2i64 5390 { 2196, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2196 = VSUBWuv4i32 5391 { 2197, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2197 = VSUBWuv8i16 5392 { 2198, 5, 1, 442, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2198 = VSUBfd 5393 { 2199, 5, 1, 443, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2199 = VSUBfq 5394 { 2200, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2200 = VSUBv16i8 5395 { 2201, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2201 = VSUBv1i64 5396 { 2202, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2202 = VSUBv2i32 5397 { 2203, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2203 = VSUBv2i64 5398 { 2204, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2204 = VSUBv4i16 5399 { 2205, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2205 = VSUBv4i32 5400 { 2206, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2206 = VSUBv8i16 5401 { 2207, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2207 = VSUBv8i8 5402 { 2208, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2208 = VSWPd 5403 { 2209, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2209 = VSWPq 5404 { 2210, 5, 1, 425, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2210 = VTBL1 5405 { 2211, 5, 1, 427, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2211 = VTBL2 5406 { 2212, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2212 = VTBL3 5407 { 2213, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2213 = VTBL3Pseudo 5408 { 2214, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2214 = VTBL4 5409 { 2215, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2215 = VTBL4Pseudo 5410 { 2216, 6, 1, 426, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2216 = VTBX1 5411 { 2217, 6, 1, 428, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo265,0,nullptr }, // Inst #2217 = VTBX2 5412 { 2218, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2218 = VTBX3 5413 { 2219, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo266,0,nullptr }, // Inst #2219 = VTBX3Pseudo 5414 { 2220, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2220 = VTBX4 5415 { 2221, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo266,0,nullptr }, // Inst #2221 = VTBX4Pseudo 5416 { 2222, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2222 = VTOSHD 5417 { 2223, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2223 = VTOSHS 5418 { 2224, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo142,0,nullptr }, // Inst #2224 = VTOSIRD 5419 { 2225, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo130,0,nullptr }, // Inst #2225 = VTOSIRS 5420 { 2226, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #2226 = VTOSIZD 5421 { 2227, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2227 = VTOSIZS 5422 { 2228, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2228 = VTOSLD 5423 { 2229, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2229 = VTOSLS 5424 { 2230, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2230 = VTOUHD 5425 { 2231, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2231 = VTOUHS 5426 { 2232, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo142,0,nullptr }, // Inst #2232 = VTOUIRD 5427 { 2233, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo130,0,nullptr }, // Inst #2233 = VTOUIRS 5428 { 2234, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #2234 = VTOUIZD 5429 { 2235, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2235 = VTOUIZS 5430 { 2236, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2236 = VTOULD 5431 { 2237, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2237 = VTOULS 5432 { 2238, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2238 = VTRNd16 5433 { 2239, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2239 = VTRNd32 5434 { 2240, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2240 = VTRNd8 5435 { 2241, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2241 = VTRNq16 5436 { 2242, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2242 = VTRNq32 5437 { 2243, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2243 = VTRNq8 5438 { 2244, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2244 = VTSTv16i8 5439 { 2245, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2245 = VTSTv2i32 5440 { 2246, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2246 = VTSTv4i16 5441 { 2247, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2247 = VTSTv4i32 5442 { 2248, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2248 = VTSTv8i16 5443 { 2249, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2249 = VTSTv8i8 5444 { 2250, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2250 = VUHTOD 5445 { 2251, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2251 = VUHTOS 5446 { 2252, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #2252 = VUITOD 5447 { 2253, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2253 = VUITOS 5448 { 2254, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2254 = VULTOD 5449 { 2255, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2255 = VULTOS 5450 { 2256, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2256 = VUZPd16 5451 { 2257, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2257 = VUZPd8 5452 { 2258, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2258 = VUZPq16 5453 { 2259, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2259 = VUZPq32 5454 { 2260, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2260 = VUZPq8 5455 { 2261, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2261 = VZIPd16 5456 { 2262, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2262 = VZIPd8 5457 { 2263, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2263 = VZIPq16 5458 { 2264, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2264 = VZIPq32 5459 { 2265, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2265 = VZIPq8 5460 { 2266, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, nullptr,0,nullptr }, // Inst #2266 = WIN__CHKSTK 5461 { 2267, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2267 = sysLDMDA 5462 { 2268, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2268 = sysLDMDA_UPD 5463 { 2269, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2269 = sysLDMDB 5464 { 2270, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2270 = sysLDMDB_UPD 5465 { 2271, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2271 = sysLDMIA 5466 { 2272, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2272 = sysLDMIA_UPD 5467 { 2273, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2273 = sysLDMIB 5468 { 2274, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2274 = sysLDMIB_UPD 5469 { 2275, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2275 = sysSTMDA 5470 { 2276, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2276 = sysSTMDA_UPD 5471 { 2277, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2277 = sysSTMDB 5472 { 2278, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2278 = sysSTMDB_UPD 5473 { 2279, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2279 = sysSTMIA 5474 { 2280, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2280 = sysSTMIA_UPD 5475 { 2281, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2281 = sysSTMIB 5476 { 2282, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2282 = sysSTMIB_UPD 5477 { 2283, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo267,0,nullptr }, // Inst #2283 = t2ABS 5478 { 2284, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2284 = t2ADCri 5479 { 2285, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2285 = t2ADCrr 5480 { 2286, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2286 = t2ADCrs 5481 { 2287, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2287 = t2ADDSri 5482 { 2288, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2288 = t2ADDSrr 5483 { 2289, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2289 = t2ADDSrs 5484 { 2290, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274,0,nullptr }, // Inst #2290 = t2ADDri 5485 { 2291, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2291 = t2ADDri12 5486 { 2292, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2292 = t2ADDrr 5487 { 2293, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2293 = t2ADDrs 5488 { 2294, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2294 = t2ADR 5489 { 2295, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2295 = t2ANDri 5490 { 2296, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2296 = t2ANDrr 5491 { 2297, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2297 = t2ANDrs 5492 { 2298, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2298 = t2ASRri 5493 { 2299, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2299 = t2ASRrr 5494 { 2300, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2300 = t2B 5495 { 2301, 5, 1, 297, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2301 = t2BFC 5496 { 2302, 6, 1, 298, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2302 = t2BFI 5497 { 2303, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2303 = t2BICri 5498 { 2304, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2304 = t2BICrr 5499 { 2305, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2305 = t2BICrs 5500 { 2306, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo36,0,nullptr }, // Inst #2306 = t2BR_JT 5501 { 2307, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo281,0,nullptr }, // Inst #2307 = t2BXJ 5502 { 2308, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2308 = t2Bcc 5503 { 2309, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2309 = t2CDP 5504 { 2310, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2310 = t2CDP2 5505 { 2311, 2, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2311 = t2CLREX 5506 { 2312, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2312 = t2CLZ 5507 { 2313, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2313 = t2CMNri 5508 { 2314, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2314 = t2CMNzrr 5509 { 2315, 5, 0, 240, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2315 = t2CMNzrs 5510 { 2316, 4, 0, 241, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2316 = t2CMPri 5511 { 2317, 4, 0, 242, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2317 = t2CMPrr 5512 { 2318, 5, 0, 243, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2318 = t2CMPrs 5513 { 2319, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2319 = t2CPS1p 5514 { 2320, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2320 = t2CPS2p 5515 { 2321, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #2321 = t2CPS3p 5516 { 2322, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2322 = t2CRC32B 5517 { 2323, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2323 = t2CRC32CB 5518 { 2324, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2324 = t2CRC32CH 5519 { 2325, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2325 = t2CRC32CW 5520 { 2326, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2326 = t2CRC32H 5521 { 2327, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2327 = t2CRC32W 5522 { 2328, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2328 = t2DBG 5523 { 2329, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2329 = t2DCPS1 5524 { 2330, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2330 = t2DCPS2 5525 { 2331, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2331 = t2DCPS3 5526 { 2332, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2332 = t2DMB 5527 { 2333, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2333 = t2DSB 5528 { 2334, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2334 = t2EORri 5529 { 2335, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2335 = t2EORrr 5530 { 2336, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2336 = t2EORrs 5531 { 2337, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2337 = t2HINT 5532 { 2338, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2338 = t2ISB 5533 { 2339, 2, 0, 378, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList12, OperandInfo7,0,0 }, // Inst #2339 = t2IT 5534 { 2340, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList13, OperandInfo287,0,nullptr }, // Inst #2340 = t2Int_eh_sjlj_setjmp 5535 { 2341, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList7, OperandInfo287,0,nullptr }, // Inst #2341 = t2Int_eh_sjlj_setjmp_nofp 5536 { 2342, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2342 = t2LDA 5537 { 2343, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2343 = t2LDAB 5538 { 2344, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2344 = t2LDAEX 5539 { 2345, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2345 = t2LDAEXB 5540 { 2346, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2346 = t2LDAEXD 5541 { 2347, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2347 = t2LDAEXH 5542 { 2348, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2348 = t2LDAH 5543 { 2349, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2349 = t2LDC2L_OFFSET 5544 { 2350, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2350 = t2LDC2L_OPTION 5545 { 2351, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2351 = t2LDC2L_POST 5546 { 2352, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2352 = t2LDC2L_PRE 5547 { 2353, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2353 = t2LDC2_OFFSET 5548 { 2354, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2354 = t2LDC2_OPTION 5549 { 2355, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2355 = t2LDC2_POST 5550 { 2356, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2356 = t2LDC2_PRE 5551 { 2357, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2357 = t2LDCL_OFFSET 5552 { 2358, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2358 = t2LDCL_OPTION 5553 { 2359, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2359 = t2LDCL_POST 5554 { 2360, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2360 = t2LDCL_PRE 5555 { 2361, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2361 = t2LDC_OFFSET 5556 { 2362, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2362 = t2LDC_OPTION 5557 { 2363, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2363 = t2LDC_POST 5558 { 2364, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2364 = t2LDC_PRE 5559 { 2365, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2365 = t2LDMDB 5560 { 2366, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2366 = t2LDMDB_UPD 5561 { 2367, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2367 = t2LDMIA 5562 { 2368, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2368 = t2LDMIA_RET 5563 { 2369, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2369 = t2LDMIA_UPD 5564 { 2370, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2370 = t2LDRBT 5565 { 2371, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2371 = t2LDRB_POST 5566 { 2372, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2372 = t2LDRB_PRE 5567 { 2373, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2373 = t2LDRBi12 5568 { 2374, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2374 = t2LDRBi8 5569 { 2375, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2375 = t2LDRBpci 5570 { 2376, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2376 = t2LDRBpcrel 5571 { 2377, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2377 = t2LDRBs 5572 { 2378, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2378 = t2LDRD_POST 5573 { 2379, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2379 = t2LDRD_PRE 5574 { 2380, 6, 2, 351, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2380 = t2LDRDi8 5575 { 2381, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo294,0,nullptr }, // Inst #2381 = t2LDREX 5576 { 2382, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2382 = t2LDREXB 5577 { 2383, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2383 = t2LDREXD 5578 { 2384, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2384 = t2LDREXH 5579 { 2385, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2385 = t2LDRHT 5580 { 2386, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2386 = t2LDRH_POST 5581 { 2387, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2387 = t2LDRH_PRE 5582 { 2388, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2388 = t2LDRHi12 5583 { 2389, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2389 = t2LDRHi8 5584 { 2390, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2390 = t2LDRHpci 5585 { 2391, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2391 = t2LDRHpcrel 5586 { 2392, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2392 = t2LDRHs 5587 { 2393, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2393 = t2LDRSBT 5588 { 2394, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2394 = t2LDRSB_POST 5589 { 2395, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2395 = t2LDRSB_PRE 5590 { 2396, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2396 = t2LDRSBi12 5591 { 2397, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2397 = t2LDRSBi8 5592 { 2398, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2398 = t2LDRSBpci 5593 { 2399, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2399 = t2LDRSBpcrel 5594 { 2400, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2400 = t2LDRSBs 5595 { 2401, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2401 = t2LDRSHT 5596 { 2402, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2402 = t2LDRSH_POST 5597 { 2403, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2403 = t2LDRSH_PRE 5598 { 2404, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2404 = t2LDRSHi12 5599 { 2405, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2405 = t2LDRSHi8 5600 { 2406, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2406 = t2LDRSHpci 5601 { 2407, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2407 = t2LDRSHpcrel 5602 { 2408, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2408 = t2LDRSHs 5603 { 2409, 5, 1, 347, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2409 = t2LDRT 5604 { 2410, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2410 = t2LDR_POST 5605 { 2411, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2411 = t2LDR_PRE 5606 { 2412, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2412 = t2LDRi12 5607 { 2413, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2413 = t2LDRi8 5608 { 2414, 4, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2414 = t2LDRpci 5609 { 2415, 3, 1, 331, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2415 = t2LDRpci_pic 5610 { 2416, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2416 = t2LDRpcrel 5611 { 2417, 6, 1, 332, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2417 = t2LDRs 5612 { 2418, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo296,0,nullptr }, // Inst #2418 = t2LEApcrel 5613 { 2419, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo297,0,nullptr }, // Inst #2419 = t2LEApcrelJT 5614 { 2420, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2420 = t2LSLri 5615 { 2421, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2421 = t2LSLrr 5616 { 2422, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2422 = t2LSRri 5617 { 2423, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2423 = t2LSRrr 5618 { 2424, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo69,0,0 }, // Inst #2424 = t2MCR 5619 { 2425, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo69,0,nullptr }, // Inst #2425 = t2MCR2 5620 { 2426, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2426 = t2MCRR 5621 { 2427, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2427 = t2MCRR2 5622 { 2428, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2428 = t2MLA 5623 { 2429, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2429 = t2MLS 5624 { 2430, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2430 = t2MOVCCasr 5625 { 2431, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2431 = t2MOVCCi 5626 { 2432, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2432 = t2MOVCCi16 5627 { 2433, 5, 1, 292, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2433 = t2MOVCCi32imm 5628 { 2434, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2434 = t2MOVCClsl 5629 { 2435, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2435 = t2MOVCClsr 5630 { 2436, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo302,0,nullptr }, // Inst #2436 = t2MOVCCr 5631 { 2437, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2437 = t2MOVCCror 5632 { 2438, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo303,0,nullptr }, // Inst #2438 = t2MOVSsi 5633 { 2439, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2439 = t2MOVSsr 5634 { 2440, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2440 = t2MOVTi16 5635 { 2441, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo305,0,nullptr }, // Inst #2441 = t2MOVTi16_ga_pcrel 5636 { 2442, 2, 1, 294, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo306,0,nullptr }, // Inst #2442 = t2MOV_ga_pcrel 5637 { 2443, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2443 = t2MOVi 5638 { 2444, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2444 = t2MOVi16 5639 { 2445, 3, 1, 295, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2445 = t2MOVi16_ga_pcrel 5640 { 2446, 2, 1, 293, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo306,0,nullptr }, // Inst #2446 = t2MOVi32imm 5641 { 2447, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2447 = t2MOVr 5642 { 2448, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo303,0,nullptr }, // Inst #2448 = t2MOVsi 5643 { 2449, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2449 = t2MOVsr 5644 { 2450, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo282,0,nullptr }, // Inst #2450 = t2MOVsra_flag 5645 { 2451, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo282,0,nullptr }, // Inst #2451 = t2MOVsrl_flag 5646 { 2452, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #2452 = t2MRC 5647 { 2453, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #2453 = t2MRC2 5648 { 2454, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2454 = t2MRRC 5649 { 2455, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2455 = t2MRRC2 5650 { 2456, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2456 = t2MRS_AR 5651 { 2457, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2457 = t2MRS_M 5652 { 2458, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2458 = t2MRSsys_AR 5653 { 2459, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo309,0,nullptr }, // Inst #2459 = t2MSR_AR 5654 { 2460, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo309,0,nullptr }, // Inst #2460 = t2MSR_M 5655 { 2461, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2461 = t2MUL 5656 { 2462, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2462 = t2MVNCCi 5657 { 2463, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2463 = t2MVNi 5658 { 2464, 5, 1, 53, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2464 = t2MVNr 5659 { 2465, 6, 1, 249, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312,0,nullptr }, // Inst #2465 = t2MVNs 5660 { 2466, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2466 = t2ORNri 5661 { 2467, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2467 = t2ORNrr 5662 { 2468, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2468 = t2ORNrs 5663 { 2469, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2469 = t2ORRri 5664 { 2470, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2470 = t2ORRrr 5665 { 2471, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2471 = t2ORRrs 5666 { 2472, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2472 = t2PKHBT 5667 { 2473, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2473 = t2PKHTB 5668 { 2474, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2474 = t2PLDWi12 5669 { 2475, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2475 = t2PLDWi8 5670 { 2476, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2476 = t2PLDWs 5671 { 2477, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2477 = t2PLDi12 5672 { 2478, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2478 = t2PLDi8 5673 { 2479, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2479 = t2PLDpci 5674 { 2480, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2480 = t2PLDs 5675 { 2481, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2481 = t2PLIi12 5676 { 2482, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2482 = t2PLIi8 5677 { 2483, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2483 = t2PLIpci 5678 { 2484, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2484 = t2PLIs 5679 { 2485, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2485 = t2QADD 5680 { 2486, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2486 = t2QADD16 5681 { 2487, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2487 = t2QADD8 5682 { 2488, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2488 = t2QASX 5683 { 2489, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2489 = t2QDADD 5684 { 2490, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2490 = t2QDSUB 5685 { 2491, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2491 = t2QSAX 5686 { 2492, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2492 = t2QSUB 5687 { 2493, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2493 = t2QSUB16 5688 { 2494, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2494 = t2QSUB8 5689 { 2495, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2495 = t2RBIT 5690 { 2496, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2496 = t2REV 5691 { 2497, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2497 = t2REV16 5692 { 2498, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2498 = t2REVSH 5693 { 2499, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2499 = t2RFEDB 5694 { 2500, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2500 = t2RFEDBW 5695 { 2501, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2501 = t2RFEIA 5696 { 2502, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2502 = t2RFEIAW 5697 { 2503, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2503 = t2RORri 5698 { 2504, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2504 = t2RORrr 5699 { 2505, 5, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo311,0,nullptr }, // Inst #2505 = t2RRX 5700 { 2506, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo316,0,nullptr }, // Inst #2506 = t2RSBSri 5701 { 2507, 6, 1, 58, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo317,0,nullptr }, // Inst #2507 = t2RSBSrs 5702 { 2508, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2508 = t2RSBri 5703 { 2509, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2509 = t2RSBrr 5704 { 2510, 7, 1, 250, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2510 = t2RSBrs 5705 { 2511, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2511 = t2SADD16 5706 { 2512, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2512 = t2SADD8 5707 { 2513, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2513 = t2SASX 5708 { 2514, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2514 = t2SBCri 5709 { 2515, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2515 = t2SBCrr 5710 { 2516, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2516 = t2SBCrs 5711 { 2517, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318,0,nullptr }, // Inst #2517 = t2SBFX 5712 { 2518, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2518 = t2SDIV 5713 { 2519, 5, 1, 296, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #2519 = t2SEL 5714 { 2520, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2520 = t2SHADD16 5715 { 2521, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2521 = t2SHADD8 5716 { 2522, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2522 = t2SHASX 5717 { 2523, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2523 = t2SHSAX 5718 { 2524, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2524 = t2SHSUB16 5719 { 2525, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2525 = t2SHSUB8 5720 { 2526, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2526 = t2SMC 5721 { 2527, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2527 = t2SMLABB 5722 { 2528, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2528 = t2SMLABT 5723 { 2529, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2529 = t2SMLAD 5724 { 2530, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2530 = t2SMLADX 5725 { 2531, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2531 = t2SMLAL 5726 { 2532, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2532 = t2SMLALBB 5727 { 2533, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2533 = t2SMLALBT 5728 { 2534, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2534 = t2SMLALD 5729 { 2535, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2535 = t2SMLALDX 5730 { 2536, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2536 = t2SMLALTB 5731 { 2537, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2537 = t2SMLALTT 5732 { 2538, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2538 = t2SMLATB 5733 { 2539, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2539 = t2SMLATT 5734 { 2540, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2540 = t2SMLAWB 5735 { 2541, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2541 = t2SMLAWT 5736 { 2542, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2542 = t2SMLSD 5737 { 2543, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2543 = t2SMLSDX 5738 { 2544, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2544 = t2SMLSLD 5739 { 2545, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2545 = t2SMLSLDX 5740 { 2546, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2546 = t2SMMLA 5741 { 2547, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2547 = t2SMMLAR 5742 { 2548, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2548 = t2SMMLS 5743 { 2549, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2549 = t2SMMLSR 5744 { 2550, 5, 1, 310, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2550 = t2SMMUL 5745 { 2551, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2551 = t2SMMULR 5746 { 2552, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2552 = t2SMUAD 5747 { 2553, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2553 = t2SMUADX 5748 { 2554, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2554 = t2SMULBB 5749 { 2555, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2555 = t2SMULBT 5750 { 2556, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2556 = t2SMULL 5751 { 2557, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2557 = t2SMULTB 5752 { 2558, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2558 = t2SMULTT 5753 { 2559, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2559 = t2SMULWB 5754 { 2560, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2560 = t2SMULWT 5755 { 2561, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2561 = t2SMUSD 5756 { 2562, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2562 = t2SMUSDX 5757 { 2563, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2563 = t2SRSDB 5758 { 2564, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2564 = t2SRSDB_UPD 5759 { 2565, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2565 = t2SRSIA 5760 { 2566, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2566 = t2SRSIA_UPD 5761 { 2567, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2567 = t2SSAT 5762 { 2568, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2568 = t2SSAT16 5763 { 2569, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2569 = t2SSAX 5764 { 2570, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2570 = t2SSUB16 5765 { 2571, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2571 = t2SSUB8 5766 { 2572, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2572 = t2STC2L_OFFSET 5767 { 2573, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2573 = t2STC2L_OPTION 5768 { 2574, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2574 = t2STC2L_POST 5769 { 2575, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2575 = t2STC2L_PRE 5770 { 2576, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2576 = t2STC2_OFFSET 5771 { 2577, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2577 = t2STC2_OPTION 5772 { 2578, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2578 = t2STC2_POST 5773 { 2579, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2579 = t2STC2_PRE 5774 { 2580, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2580 = t2STCL_OFFSET 5775 { 2581, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2581 = t2STCL_OPTION 5776 { 2582, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2582 = t2STCL_POST 5777 { 2583, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2583 = t2STCL_PRE 5778 { 2584, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2584 = t2STC_OFFSET 5779 { 2585, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2585 = t2STC_OPTION 5780 { 2586, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2586 = t2STC_POST 5781 { 2587, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2587 = t2STC_PRE 5782 { 2588, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2588 = t2STL 5783 { 2589, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2589 = t2STLB 5784 { 2590, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2590 = t2STLEX 5785 { 2591, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2591 = t2STLEXB 5786 { 2592, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2592 = t2STLEXD 5787 { 2593, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2593 = t2STLEXH 5788 { 2594, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2594 = t2STLH 5789 { 2595, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2595 = t2STMDB 5790 { 2596, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2596 = t2STMDB_UPD 5791 { 2597, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2597 = t2STMIA 5792 { 2598, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2598 = t2STMIA_UPD 5793 { 2599, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2599 = t2STRBT 5794 { 2600, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2600 = t2STRB_POST 5795 { 2601, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2601 = t2STRB_PRE 5796 { 2602, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2602 = t2STRB_preidx 5797 { 2603, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2603 = t2STRBi12 5798 { 2604, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2604 = t2STRBi8 5799 { 2605, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2605 = t2STRBs 5800 { 2606, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2606 = t2STRD_POST 5801 { 2607, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2607 = t2STRD_PRE 5802 { 2608, 6, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2608 = t2STRDi8 5803 { 2609, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo328,0,nullptr }, // Inst #2609 = t2STREX 5804 { 2610, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2610 = t2STREXB 5805 { 2611, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2611 = t2STREXD 5806 { 2612, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2612 = t2STREXH 5807 { 2613, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2613 = t2STRHT 5808 { 2614, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2614 = t2STRH_POST 5809 { 2615, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2615 = t2STRH_PRE 5810 { 2616, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2616 = t2STRH_preidx 5811 { 2617, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2617 = t2STRHi12 5812 { 2618, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2618 = t2STRHi8 5813 { 2619, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2619 = t2STRHs 5814 { 2620, 5, 1, 371, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2620 = t2STRT 5815 { 2621, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo329,0,nullptr }, // Inst #2621 = t2STR_POST 5816 { 2622, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo329,0,nullptr }, // Inst #2622 = t2STR_PRE 5817 { 2623, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2623 = t2STR_preidx 5818 { 2624, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2624 = t2STRi12 5819 { 2625, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2625 = t2STRi8 5820 { 2626, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2626 = t2STRs 5821 { 2627, 3, 0, 0, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, ImplicitList14, OperandInfo47,0,nullptr }, // Inst #2627 = t2SUBS_PC_LR 5822 { 2628, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2628 = t2SUBSri 5823 { 2629, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2629 = t2SUBSrr 5824 { 2630, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2630 = t2SUBSrs 5825 { 2631, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274,0,nullptr }, // Inst #2631 = t2SUBri 5826 { 2632, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2632 = t2SUBri12 5827 { 2633, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2633 = t2SUBrr 5828 { 2634, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2634 = t2SUBrs 5829 { 2635, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2635 = t2SXTAB 5830 { 2636, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2636 = t2SXTAB16 5831 { 2637, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2637 = t2SXTAH 5832 { 2638, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2638 = t2SXTB 5833 { 2639, 5, 1, 291, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2639 = t2SXTB16 5834 { 2640, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2640 = t2SXTH 5835 { 2641, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2641 = t2TBB 5836 { 2642, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #2642 = t2TBB_JT 5837 { 2643, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2643 = t2TBH 5838 { 2644, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #2644 = t2TBH_JT 5839 { 2645, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2645 = t2TEQri 5840 { 2646, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2646 = t2TEQrr 5841 { 2647, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2647 = t2TEQrs 5842 { 2648, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2648 = t2TSTri 5843 { 2649, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2649 = t2TSTrr 5844 { 2650, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2650 = t2TSTrs 5845 { 2651, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2651 = t2UADD16 5846 { 2652, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2652 = t2UADD8 5847 { 2653, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2653 = t2UASX 5848 { 2654, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318,0,nullptr }, // Inst #2654 = t2UBFX 5849 { 2655, 1, 0, 76, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2655 = t2UDF 5850 { 2656, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2656 = t2UDIV 5851 { 2657, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2657 = t2UHADD16 5852 { 2658, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2658 = t2UHADD8 5853 { 2659, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2659 = t2UHASX 5854 { 2660, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2660 = t2UHSAX 5855 { 2661, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2661 = t2UHSUB16 5856 { 2662, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2662 = t2UHSUB8 5857 { 2663, 6, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2663 = t2UMAAL 5858 { 2664, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2664 = t2UMLAL 5859 { 2665, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2665 = t2UMULL 5860 { 2666, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2666 = t2UQADD16 5861 { 2667, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2667 = t2UQADD8 5862 { 2668, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2668 = t2UQASX 5863 { 2669, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2669 = t2UQSAX 5864 { 2670, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2670 = t2UQSUB16 5865 { 2671, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2671 = t2UQSUB8 5866 { 2672, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2672 = t2USAD8 5867 { 2673, 6, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2673 = t2USADA8 5868 { 2674, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2674 = t2USAT 5869 { 2675, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2675 = t2USAT16 5870 { 2676, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2676 = t2USAX 5871 { 2677, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2677 = t2USUB16 5872 { 2678, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2678 = t2USUB8 5873 { 2679, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2679 = t2UXTAB 5874 { 2680, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2680 = t2UXTAB16 5875 { 2681, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2681 = t2UXTAH 5876 { 2682, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2682 = t2UXTB 5877 { 2683, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2683 = t2UXTB16 5878 { 2684, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2684 = t2UXTH 5879 { 2685, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2685 = tADC 5880 { 2686, 5, 1, 258, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #2686 = tADDhirr 5881 { 2687, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2687 = tADDi3 5882 { 2688, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2688 = tADDi8 5883 { 2689, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2689 = tADDrSP 5884 { 2690, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo335,0,nullptr }, // Inst #2690 = tADDrSPi 5885 { 2691, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2691 = tADDrr 5886 { 2692, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo337,0,nullptr }, // Inst #2692 = tADDspi 5887 { 2693, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo338,0,nullptr }, // Inst #2693 = tADDspr 5888 { 2694, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2,0,nullptr }, // Inst #2694 = tADJCALLSTACKDOWN 5889 { 2695, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8,0,nullptr }, // Inst #2695 = tADJCALLSTACKUP 5890 { 2696, 4, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2696 = tADR 5891 { 2697, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2697 = tAND 5892 { 2698, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2698 = tASRri 5893 { 2699, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2699 = tASRrr 5894 { 2700, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2700 = tB 5895 { 2701, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2701 = tBIC 5896 { 2702, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2702 = tBKPT 5897 { 2703, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo340,0,nullptr }, // Inst #2703 = tBL 5898 { 2704, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo340,0,nullptr }, // Inst #2704 = tBLXi 5899 { 2705, 3, 0, 12, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo341,0,nullptr }, // Inst #2705 = tBLXr 5900 { 2706, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2706 = tBRIND 5901 { 2707, 3, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo342,0,nullptr }, // Inst #2707 = tBR_JTr 5902 { 2708, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2708 = tBX 5903 { 2709, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #2709 = tBX_CALL 5904 { 2710, 2, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2710 = tBX_RET 5905 { 2711, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo343,0,nullptr }, // Inst #2711 = tBX_RET_vararg 5906 { 2712, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2712 = tBcc 5907 { 2713, 3, 0, 14, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo34,0,nullptr }, // Inst #2713 = tBfar 5908 { 2714, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344,0,nullptr }, // Inst #2714 = tCBNZ 5909 { 2715, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344,0,nullptr }, // Inst #2715 = tCBZ 5910 { 2716, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2716 = tCMNz 5911 { 2717, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #2717 = tCMPhir 5912 { 2718, 4, 0, 241, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2718 = tCMPi8 5913 { 2719, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2719 = tCMPr 5914 { 2720, 2, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2720 = tCPS 5915 { 2721, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2721 = tEOR 5916 { 2722, 3, 0, 0, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2722 = tHINT 5917 { 2723, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2723 = tHLT 5918 { 2724, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo11,0,nullptr }, // Inst #2724 = tInt_eh_sjlj_longjmp 5919 { 2725, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList15, OperandInfo287,0,nullptr }, // Inst #2725 = tInt_eh_sjlj_setjmp 5920 { 2726, 4, 0, 353, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo347,0,nullptr }, // Inst #2726 = tLDMIA 5921 { 2727, 5, 1, 354, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2727 = tLDMIA_UPD 5922 { 2728, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2728 = tLDRBi 5923 { 2729, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2729 = tLDRBr 5924 { 2730, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2730 = tLDRHi 5925 { 2731, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2731 = tLDRHr 5926 { 2732, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2732 = tLDRLIT_ga_abs 5927 { 2733, 2, 1, 34, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2733 = tLDRLIT_ga_pcrel 5928 { 2734, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2734 = tLDRSB 5929 { 2735, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2735 = tLDRSH 5930 { 2736, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2736 = tLDRi 5931 { 2737, 4, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2737 = tLDRpci 5932 { 2738, 3, 1, 327, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #2738 = tLDRpci_pic 5933 { 2739, 5, 1, 334, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2739 = tLDRr 5934 { 2740, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2740 = tLDRspi 5935 { 2741, 4, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo352,0,nullptr }, // Inst #2741 = tLEApcrel 5936 { 2742, 5, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo353,0,nullptr }, // Inst #2742 = tLEApcrelJT 5937 { 2743, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2743 = tLSLri 5938 { 2744, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2744 = tLSLrr 5939 { 2745, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2745 = tLSRri 5940 { 2746, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2746 = tLSRrr 5941 { 2747, 5, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo354,0,nullptr }, // Inst #2747 = tMOVCCr_pseudo 5942 { 2748, 2, 1, 48, 2, 0, 0xc80ULL, nullptr, ImplicitList1, OperandInfo287,0,nullptr }, // Inst #2748 = tMOVSr 5943 { 2749, 5, 2, 41, 2, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo355,0,nullptr }, // Inst #2749 = tMOVi8 5944 { 2750, 4, 1, 48, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #2750 = tMOVr 5945 { 2751, 6, 2, 51, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo356,0,nullptr }, // Inst #2751 = tMUL 5946 { 2752, 5, 2, 53, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2752 = tMVN 5947 { 2753, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2753 = tORR 5948 { 2754, 3, 1, 258, 2, 0|(1<<MCID_NotDuplicable), 0xc80ULL, nullptr, nullptr, OperandInfo358,0,nullptr }, // Inst #2754 = tPICADD 5949 { 2755, 3, 0, 356, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo359,0,nullptr }, // Inst #2755 = tPOP 5950 { 2756, 3, 0, 357, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo359,0,nullptr }, // Inst #2756 = tPOP_RET 5951 { 2757, 3, 0, 376, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo359,0,nullptr }, // Inst #2757 = tPUSH 5952 { 2758, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2758 = tREV 5953 { 2759, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2759 = tREV16 5954 { 2760, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2760 = tREVSH 5955 { 2761, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2761 = tROR 5956 { 2762, 5, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2762 = tRSB 5957 { 2763, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2763 = tSBC 5958 { 2764, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #2764 = tSETEND 5959 { 2765, 5, 1, 375, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo360,0,nullptr }, // Inst #2765 = tSTMIA_UPD 5960 { 2766, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2766 = tSTRBi 5961 { 2767, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2767 = tSTRBr 5962 { 2768, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2768 = tSTRHi 5963 { 2769, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2769 = tSTRHr 5964 { 2770, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2770 = tSTRi 5965 { 2771, 5, 0, 358, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2771 = tSTRr 5966 { 2772, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2772 = tSTRspi 5967 { 2773, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2773 = tSUBi3 5968 { 2774, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2774 = tSUBi8 5969 { 2775, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2775 = tSUBrr 5970 { 2776, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo337,0,nullptr }, // Inst #2776 = tSUBspi 5971 { 2777, 3, 0, 10, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo47,0,nullptr }, // Inst #2777 = tSVC 5972 { 2778, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2778 = tSXTB 5973 { 2779, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2779 = tSXTH 5974 { 2780, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo34,0,nullptr }, // Inst #2780 = tTAILJMPd 5975 { 2781, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo34,0,nullptr }, // Inst #2781 = tTAILJMPdND 5976 { 2782, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo122,0,nullptr }, // Inst #2782 = tTAILJMPr 5977 { 2783, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, nullptr,0,nullptr }, // Inst #2783 = tTPsoft 5978 { 2784, 0, 0, 10, 2, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #2784 = tTRAP 5979 { 2785, 4, 0, 263, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2785 = tTST 5980 { 2786, 1, 0, 76, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2786 = tUDF 5981 { 2787, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2787 = tUXTB 5982 { 2788, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2788 = tUXTH 5983}; 5984 5985 5986#endif // GET_INSTRINFO_MC_DESC 5987 5988