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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  *
5  */
6 #ifndef __FSL_STREAM_ID_H
7 #define __FSL_STREAM_ID_H
8 
9 /*
10  * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
11  * devices are not hardwired and are programmed by sw. There are a limited
12  * number of stream IDs available, and the partitioning of them is scenario
13  * dependent. This header defines the partitioning between legacy,
14  * PCI, and DPAA2 devices.
15  *
16  * This partitioning can be customized in this file depending
17  * on the specific hardware config:
18  *
19  *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
20  *     -all legacy devices get a unique stream ID assigned and programmed in
21  *      their AMQR registers by u-boot
22  *
23  *  -PCIe
24  *     -there is a range of stream IDs set aside for PCI in this
25  *      file.  U-boot will scan the PCI bus and for each device discovered:
26  *         -allocate a streamID
27  *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
28  *         -set a msi-map entry in the PEXn controller node in the
29  *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
30  *          for more info on the msi-map definition)
31  *         -set a iommu-map entry in the PEXn controller node in the
32  *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
33  *          for more info on the iommu-map definition)
34  *
35  *  -DPAA2
36  *     -u-boot will allocate a range of stream IDs to be used by the Management
37  *      Complex for containers and will set these values in the MC DPC image.
38  *     -the MC is responsible for allocating and setting up 'isolation context
39  *      IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
40  *
41  * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
42  * each of the different bus masters.  The relationship between
43  * the AMQ registers and stream IDs is defined in the table below:
44  *          AMQ bit    streamID bit
45  *      ---------------------------
46  *           PL[18]         9        // privilege bit
47  *          BMT[17]         8        // bypass translation
48  *           VA[16]         7        // reserved
49  *             [15]         -        // unused
50  *         ICID[14:7]       -        // unused
51  *         ICID[6:0]        6-0      // isolation context id
52  *     ----------------------------
53  *
54  */
55 
56 #define AMQ_PL_MASK			(0x1 << 18)   /* priviledge bit */
57 #define AMQ_BMT_MASK			(0x1 << 17)   /* bypass bit */
58 
59 #define FSL_INVALID_STREAM_ID		0
60 
61 #define FSL_BYPASS_AMQ			(AMQ_PL_MASK | AMQ_BMT_MASK)
62 
63 /* legacy devices */
64 #define FSL_USB1_STREAM_ID		1
65 #define FSL_USB2_STREAM_ID		2
66 #define FSL_SDMMC_STREAM_ID		3
67 #define FSL_SATA1_STREAM_ID		4
68 
69 #if defined(CONFIG_ARCH_LS2080A)
70 #define FSL_SATA2_STREAM_ID		5
71 #endif
72 
73 #if defined(CONFIG_ARCH_LS2080A)
74 #define FSL_DMA_STREAM_ID		6
75 #elif defined(CONFIG_ARCH_LS1088A)
76 #define FSL_DMA_STREAM_ID		5
77 #endif
78 
79 /* PCI - programmed in PEXn_LUT */
80 #define FSL_PEX_STREAM_ID_START		7
81 
82 #if defined(CONFIG_ARCH_LS2080A)
83 #define FSL_PEX_STREAM_ID_END		22
84 #elif defined(CONFIG_ARCH_LS1088A)
85 #define FSL_PEX_STREAM_ID_END		18
86 #endif
87 
88 
89 /* DPAA2 - set in MC DPC and alloced by MC */
90 #define FSL_DPAA2_STREAM_ID_START	23
91 #define FSL_DPAA2_STREAM_ID_END		63
92 
93 #endif
94