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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2012  Renesas Solutions Corp.
4  */
5 
6 #ifndef _ASM_CPU_SH7752_H_
7 #define _ASM_CPU_SH7752_H_
8 
9 #define CCR		0xFF00001C
10 #define WTCNT		0xFFCC0000
11 #define CCR_CACHE_INIT	0x0000090b
12 #define CACHE_OC_NUM_WAYS	1
13 
14 #ifndef __ASSEMBLY__		/* put C only stuff in this section */
15 /* MMU */
16 struct mmu_regs {
17 	unsigned int	reserved[4];
18 	unsigned int	mmucr;
19 };
20 #define MMU_BASE	((struct mmu_regs *)0xff000000)
21 
22 /* Watchdog */
23 #define WTCSR0		0xffcc0002
24 #define WRSTCSR_R	0xffcc0003
25 #define WRSTCSR_W	0xffcc0002
26 #define WTCSR_PREFIX		0xa500
27 #define WRSTCSR_PREFIX		0x6900
28 #define WRSTCSR_WOVF_PREFIX	0x9600
29 
30 /* SCIF */
31 #define SCIF0_BASE	0xfe4b0000	/* The real name is SCIF2 */
32 #define SCIF1_BASE	0xfe4c0000	/* The real name is SCIF3 */
33 #define SCIF2_BASE	0xfe4d0000	/* The real name is SCIF4 */
34 
35 /* TMU0 */
36 #define TMU_BASE	 0xFE430000
37 
38 /* ETHER, GETHER MAC address */
39 struct ether_mac_regs {
40 	unsigned int	reserved[114];
41 	unsigned int	mahr;
42 	unsigned int	reserved2;
43 	unsigned int	malr;
44 };
45 #define GETHER0_MAC_BASE	((struct ether_mac_regs *)0xfee0400)
46 #define GETHER1_MAC_BASE	((struct ether_mac_regs *)0xfee0c00)
47 #define ETHER0_MAC_BASE		((struct ether_mac_regs *)0xfef0000)
48 #define ETHER1_MAC_BASE		((struct ether_mac_regs *)0xfef0800)
49 
50 /* GETHER */
51 struct gether_control_regs {
52 	unsigned int	gbecont;
53 };
54 #define GETHER_CONTROL_BASE	((struct gether_control_regs *)0xffc10100)
55 #define GBECONT_RMII1		0x00020000
56 #define GBECONT_RMII0		0x00010000
57 
58 /* SerMux */
59 struct sermux_regs {
60 	unsigned char	smr0;
61 	unsigned char	smr1;
62 	unsigned char	smr2;
63 	unsigned char	smr3;
64 	unsigned char	smr4;
65 	unsigned char	smr5;
66 };
67 #define SERMUX_BASE	((struct sermux_regs *)0xfe470000)
68 
69 
70 /* USB0/1 */
71 struct usb_common_regs {
72 	unsigned short	reserved[129];
73 	unsigned short	suspmode;
74 };
75 #define USB0_COMMON_BASE	((struct usb_common_regs *)0xfe450000)
76 #define USB1_COMMON_BASE	((struct usb_common_regs *)0xfe4f0000)
77 
78 struct usb0_phy_regs {
79 	unsigned short	reset;
80 	unsigned short	reserved[4];
81 	unsigned short	portsel;
82 };
83 #define USB0_PHY_BASE		((struct usb0_phy_regs *)0xfe5f0000)
84 
85 struct usb1_port_regs {
86 	unsigned int	port1sel;
87 	unsigned int	reserved;
88 	unsigned int	usb1intsts;
89 };
90 #define USB1_PORT_BASE		((struct usb1_port_regs *)0xfe4f2000)
91 
92 struct usb1_alignment_regs {
93 	unsigned int	ehcidatac;	/* 0xfe4fe018 */
94 	unsigned int	reserved[63];
95 	unsigned int	ohcidatac;
96 };
97 #define USB1_ALIGNMENT_BASE	((struct usb1_alignment_regs *)0xfe4fe018)
98 
99 /* GPIO */
100 struct gpio_regs {
101 	unsigned short	pacr;
102 	unsigned short	pbcr;
103 	unsigned short	pccr;
104 	unsigned short	pdcr;
105 	unsigned short	pecr;
106 	unsigned short	pfcr;
107 	unsigned short	pgcr;
108 	unsigned short	phcr;
109 	unsigned short	picr;
110 	unsigned short	pjcr;
111 	unsigned short	pkcr;
112 	unsigned short	plcr;
113 	unsigned short	pmcr;
114 	unsigned short	pncr;
115 	unsigned short	pocr;
116 	unsigned short	reserved;
117 	unsigned short	pqcr;
118 	unsigned short	prcr;
119 	unsigned short	pscr;
120 	unsigned short	ptcr;
121 	unsigned short	pucr;
122 	unsigned short	pvcr;
123 	unsigned short	pwcr;
124 	unsigned short	pxcr;
125 	unsigned short	pycr;
126 	unsigned short	pzcr;
127 	unsigned char	padr;
128 	unsigned char	reserved_a;
129 	unsigned char	pbdr;
130 	unsigned char	reserved_b;
131 	unsigned char	pcdr;
132 	unsigned char	reserved_c;
133 	unsigned char	pddr;
134 	unsigned char	reserved_d;
135 	unsigned char	pedr;
136 	unsigned char	reserved_e;
137 	unsigned char	pfdr;
138 	unsigned char	reserved_f;
139 	unsigned char	pgdr;
140 	unsigned char	reserved_g;
141 	unsigned char	phdr;
142 	unsigned char	reserved_h;
143 	unsigned char	pidr;
144 	unsigned char	reserved_i;
145 	unsigned char	pjdr;
146 	unsigned char	reserved_j;
147 	unsigned char	pkdr;
148 	unsigned char	reserved_k;
149 	unsigned char	pldr;
150 	unsigned char	reserved_l;
151 	unsigned char	pmdr;
152 	unsigned char	reserved_m;
153 	unsigned char	pndr;
154 	unsigned char	reserved_n;
155 	unsigned char	podr;
156 	unsigned char	reserved_o;
157 	unsigned char	ppdr;
158 	unsigned char	reserved_p;
159 	unsigned char	pqdr;
160 	unsigned char	reserved_q;
161 	unsigned char	prdr;
162 	unsigned char	reserved_r;
163 	unsigned char	psdr;
164 	unsigned char	reserved_s;
165 	unsigned char	ptdr;
166 	unsigned char	reserved_t;
167 	unsigned char	pudr;
168 	unsigned char	reserved_u;
169 	unsigned char	pvdr;
170 	unsigned char	reserved_v;
171 	unsigned char	pwdr;
172 	unsigned char	reserved_w;
173 	unsigned char	pxdr;
174 	unsigned char	reserved_x;
175 	unsigned char	pydr;
176 	unsigned char	reserved_y;
177 	unsigned char	pzdr;
178 	unsigned char	reserved_z;
179 	unsigned short	ncer;
180 	unsigned short	ncmcr;
181 	unsigned short	nccsr;
182 	unsigned char	reserved2[2];
183 	unsigned short	psel0;		/* +0x70 */
184 	unsigned short	psel1;
185 	unsigned short	psel2;
186 	unsigned short	psel3;
187 	unsigned short	psel4;
188 	unsigned short	psel5;
189 	unsigned short	psel6;
190 	unsigned short	reserved3[2];
191 	unsigned short	psel7;
192 };
193 #define GPIO_BASE	((struct gpio_regs *)0xffec0000)
194 
195 #endif	/* ifndef __ASSEMBLY__ */
196 #endif	/* _ASM_CPU_SH7752_H_ */
197