1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Taken from the linux kernel file of the same name 4 * 5 * (C) Copyright 2012 6 * Graeme Russ, <graeme.russ@gmail.com> 7 */ 8 9 #ifndef _ASM_X86_MSR_INDEX_H 10 #define _ASM_X86_MSR_INDEX_H 11 12 /* CPU model specific register (MSR) numbers */ 13 14 /* x86-64 specific MSRs */ 15 #define MSR_EFER 0xc0000080 /* extended feature register */ 16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25 /* EFER bits: */ 26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27 #define _EFER_LME 8 /* Long mode enable */ 28 #define _EFER_LMA 10 /* Long mode active (read-only) */ 29 #define _EFER_NX 11 /* No execute enable */ 30 #define _EFER_SVME 12 /* Enable virtualization */ 31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34 #define EFER_SCE (1<<_EFER_SCE) 35 #define EFER_LME (1<<_EFER_LME) 36 #define EFER_LMA (1<<_EFER_LMA) 37 #define EFER_NX (1<<_EFER_NX) 38 #define EFER_SVME (1<<_EFER_SVME) 39 #define EFER_LMSLE (1<<_EFER_LMSLE) 40 #define EFER_FFXSR (1<<_EFER_FFXSR) 41 42 /* Intel MSRs. Some also available on other CPUs */ 43 #define MSR_PIC_MSG_CONTROL 0x2e 44 #define PLATFORM_INFO_SET_TDP (1 << 29) 45 46 #define MSR_IA32_PERFCTR0 0x000000c1 47 #define MSR_IA32_PERFCTR1 0x000000c2 48 #define MSR_FSB_FREQ 0x000000cd 49 #define MSR_NHM_PLATFORM_INFO 0x000000ce 50 51 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 52 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 53 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 54 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 55 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 56 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 57 58 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 59 #define MSR_PLATFORM_INFO 0x000000ce 60 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 61 #define SINGLE_PCTL (1 << 11) 62 63 #define MSR_MTRRcap 0x000000fe 64 #define MSR_IA32_BBL_CR_CTL 0x00000119 65 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 66 #define MSR_POWER_MISC 0x00000120 67 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 68 #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 69 70 #define MSR_IA32_SYSENTER_CS 0x00000174 71 #define MSR_IA32_SYSENTER_ESP 0x00000175 72 #define MSR_IA32_SYSENTER_EIP 0x00000176 73 74 #define MSR_IA32_MCG_CAP 0x00000179 75 #define MSR_IA32_MCG_STATUS 0x0000017a 76 #define MSR_IA32_MCG_CTL 0x0000017b 77 78 #define MSR_FLEX_RATIO 0x194 79 #define FLEX_RATIO_LOCK (1 << 20) 80 #define FLEX_RATIO_EN (1 << 16) 81 82 #define MSR_IA32_MISC_ENABLES 0x000001a0 83 #define MSR_TEMPERATURE_TARGET 0x1a2 84 #define MSR_OFFCORE_RSP_0 0x000001a6 85 #define MSR_OFFCORE_RSP_1 0x000001a7 86 #define MSR_MISC_PWR_MGMT 0x1aa 87 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 88 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 89 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 90 91 #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 92 #define ENERGY_POLICY_PERFORMANCE 0 93 #define ENERGY_POLICY_NORMAL 6 94 #define ENERGY_POLICY_POWERSAVE 15 95 96 #define MSR_LBR_SELECT 0x000001c8 97 #define MSR_LBR_TOS 0x000001c9 98 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 99 #define MSR_POWER_CTL 0x000001fc 100 #define MSR_LBR_NHM_FROM 0x00000680 101 #define MSR_LBR_NHM_TO 0x000006c0 102 #define MSR_LBR_CORE_FROM 0x00000040 103 #define MSR_LBR_CORE_TO 0x00000060 104 105 #define MSR_IA32_PEBS_ENABLE 0x000003f1 106 #define MSR_IA32_DS_AREA 0x00000600 107 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 108 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 109 110 #define MSR_MTRRfix64K_00000 0x00000250 111 #define MSR_MTRRfix16K_80000 0x00000258 112 #define MSR_MTRRfix16K_A0000 0x00000259 113 #define MSR_MTRRfix4K_C0000 0x00000268 114 #define MSR_MTRRfix4K_C8000 0x00000269 115 #define MSR_MTRRfix4K_D0000 0x0000026a 116 #define MSR_MTRRfix4K_D8000 0x0000026b 117 #define MSR_MTRRfix4K_E0000 0x0000026c 118 #define MSR_MTRRfix4K_E8000 0x0000026d 119 #define MSR_MTRRfix4K_F0000 0x0000026e 120 #define MSR_MTRRfix4K_F8000 0x0000026f 121 #define MSR_MTRRdefType 0x000002ff 122 123 #define MSR_IA32_CR_PAT 0x00000277 124 125 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 126 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 127 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 128 #define MSR_IA32_LASTINTFROMIP 0x000001dd 129 #define MSR_IA32_LASTINTTOIP 0x000001de 130 131 /* DEBUGCTLMSR bits (others vary by model): */ 132 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 133 /* single-step on branches */ 134 #define DEBUGCTLMSR_BTF (1UL << 1) 135 #define DEBUGCTLMSR_TR (1UL << 6) 136 #define DEBUGCTLMSR_BTS (1UL << 7) 137 #define DEBUGCTLMSR_BTINT (1UL << 8) 138 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 139 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 140 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 141 142 #define MSR_IA32_POWER_CTL 0x000001fc 143 144 #define MSR_IA32_MC0_CTL 0x00000400 145 #define MSR_IA32_MC0_STATUS 0x00000401 146 #define MSR_IA32_MC0_ADDR 0x00000402 147 #define MSR_IA32_MC0_MISC 0x00000403 148 149 /* C-state Residency Counters */ 150 #define MSR_PKG_C3_RESIDENCY 0x000003f8 151 #define MSR_PKG_C6_RESIDENCY 0x000003f9 152 #define MSR_PKG_C7_RESIDENCY 0x000003fa 153 #define MSR_CORE_C3_RESIDENCY 0x000003fc 154 #define MSR_CORE_C6_RESIDENCY 0x000003fd 155 #define MSR_CORE_C7_RESIDENCY 0x000003fe 156 #define MSR_PKG_C2_RESIDENCY 0x0000060d 157 #define MSR_PKG_C8_RESIDENCY 0x00000630 158 #define MSR_PKG_C9_RESIDENCY 0x00000631 159 #define MSR_PKG_C10_RESIDENCY 0x00000632 160 161 /* Run Time Average Power Limiting (RAPL) Interface */ 162 163 #define MSR_PKG_POWER_SKU_UNIT 0x00000606 164 165 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 166 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 167 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 168 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 169 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 170 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 171 #define IRTL_VALID (1 << 15) 172 #define IRTL_1_NS (0 << 10) 173 #define IRTL_32_NS (1 << 10) 174 #define IRTL_1024_NS (2 << 10) 175 #define IRTL_32768_NS (3 << 10) 176 #define IRTL_1048576_NS (4 << 10) 177 #define IRTL_33554432_NS (5 << 10) 178 #define IRTL_RESPONSE_MASK (0x3ff) 179 180 #define MSR_PKG_POWER_LIMIT 0x00000610 181 /* long duration in low dword, short duration in high dword */ 182 #define PKG_POWER_LIMIT_MASK 0x7fff 183 #define PKG_POWER_LIMIT_EN (1 << 15) 184 #define PKG_POWER_LIMIT_CLAMP (1 << 16) 185 #define PKG_POWER_LIMIT_TIME_SHIFT 17 186 #define PKG_POWER_LIMIT_TIME_MASK 0x7f 187 188 #define MSR_PKG_ENERGY_STATUS 0x00000611 189 #define MSR_PKG_PERF_STATUS 0x00000613 190 #define MSR_PKG_POWER_INFO 0x00000614 191 192 #define MSR_DRAM_POWER_LIMIT 0x00000618 193 #define MSR_DRAM_ENERGY_STATUS 0x00000619 194 #define MSR_DRAM_PERF_STATUS 0x0000061b 195 #define MSR_DRAM_POWER_INFO 0x0000061c 196 197 #define MSR_PP0_POWER_LIMIT 0x00000638 198 #define MSR_PP0_ENERGY_STATUS 0x00000639 199 #define MSR_PP0_POLICY 0x0000063a 200 #define MSR_PP0_PERF_STATUS 0x0000063b 201 202 #define MSR_PP1_POWER_LIMIT 0x00000640 203 #define MSR_PP1_ENERGY_STATUS 0x00000641 204 #define MSR_PP1_POLICY 0x00000642 205 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 206 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c 207 #define MSR_CORE_C1_RES 0x00000660 208 #define MSR_IACORE_RATIOS 0x0000066a 209 #define MSR_IACORE_TURBO_RATIOS 0x0000066c 210 #define MSR_IACORE_VIDS 0x0000066b 211 #define MSR_IACORE_TURBO_VIDS 0x0000066d 212 #define MSR_PKG_TURBO_CFG1 0x00000670 213 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 214 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 215 #define MSR_CPU_THERM_CFG1 0x00000673 216 #define MSR_CPU_THERM_CFG2 0x00000674 217 #define MSR_CPU_THERM_SENS_CFG 0x00000675 218 219 #define MSR_AMD64_MC0_MASK 0xc0010044 220 221 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 222 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 223 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 224 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 225 226 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 227 228 /* These are consecutive and not in the normal 4er MCE bank block */ 229 #define MSR_IA32_MC0_CTL2 0x00000280 230 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 231 232 #define MSR_P6_PERFCTR0 0x000000c1 233 #define MSR_P6_PERFCTR1 0x000000c2 234 #define MSR_P6_EVNTSEL0 0x00000186 235 #define MSR_P6_EVNTSEL1 0x00000187 236 237 #define MSR_KNC_PERFCTR0 0x00000020 238 #define MSR_KNC_PERFCTR1 0x00000021 239 #define MSR_KNC_EVNTSEL0 0x00000028 240 #define MSR_KNC_EVNTSEL1 0x00000029 241 242 /* Alternative perfctr range with full access. */ 243 #define MSR_IA32_PMC0 0x000004c1 244 245 /* AMD64 MSRs. Not complete. See the architecture manual for a more 246 complete list. */ 247 248 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 249 #define MSR_AMD64_TSC_RATIO 0xc0000104 250 #define MSR_AMD64_NB_CFG 0xc001001f 251 #define MSR_AMD64_PATCH_LOADER 0xc0010020 252 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 253 #define MSR_AMD64_OSVW_STATUS 0xc0010141 254 #define MSR_AMD64_LS_CFG 0xc0011020 255 #define MSR_AMD64_DC_CFG 0xc0011022 256 #define MSR_AMD64_BU_CFG2 0xc001102a 257 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 258 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 259 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 260 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 261 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 262 #define MSR_AMD64_IBSOPCTL 0xc0011033 263 #define MSR_AMD64_IBSOPRIP 0xc0011034 264 #define MSR_AMD64_IBSOPDATA 0xc0011035 265 #define MSR_AMD64_IBSOPDATA2 0xc0011036 266 #define MSR_AMD64_IBSOPDATA3 0xc0011037 267 #define MSR_AMD64_IBSDCLINAD 0xc0011038 268 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 269 #define MSR_AMD64_IBSOP_REG_COUNT 7 270 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 271 #define MSR_AMD64_IBSCTL 0xc001103a 272 #define MSR_AMD64_IBSBRTARGET 0xc001103b 273 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 274 275 /* Fam 16h MSRs */ 276 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 277 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 278 279 /* Fam 15h MSRs */ 280 #define MSR_F15H_PERF_CTL 0xc0010200 281 #define MSR_F15H_PERF_CTR 0xc0010201 282 #define MSR_F15H_NB_PERF_CTL 0xc0010240 283 #define MSR_F15H_NB_PERF_CTR 0xc0010241 284 285 /* Fam 10h MSRs */ 286 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 287 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 288 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 289 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 290 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 291 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 292 #define MSR_FAM10H_NODE_ID 0xc001100c 293 294 /* K8 MSRs */ 295 #define MSR_K8_TOP_MEM1 0xc001001a 296 #define MSR_K8_TOP_MEM2 0xc001001d 297 #define MSR_K8_SYSCFG 0xc0010010 298 #define MSR_K8_INT_PENDING_MSG 0xc0010055 299 /* C1E active bits in int pending message */ 300 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 301 #define MSR_K8_TSEG_ADDR 0xc0010112 302 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 303 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 304 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 305 306 /* K7 MSRs */ 307 #define MSR_K7_EVNTSEL0 0xc0010000 308 #define MSR_K7_PERFCTR0 0xc0010004 309 #define MSR_K7_EVNTSEL1 0xc0010001 310 #define MSR_K7_PERFCTR1 0xc0010005 311 #define MSR_K7_EVNTSEL2 0xc0010002 312 #define MSR_K7_PERFCTR2 0xc0010006 313 #define MSR_K7_EVNTSEL3 0xc0010003 314 #define MSR_K7_PERFCTR3 0xc0010007 315 #define MSR_K7_CLK_CTL 0xc001001b 316 #define MSR_K7_HWCR 0xc0010015 317 #define MSR_K7_FID_VID_CTL 0xc0010041 318 #define MSR_K7_FID_VID_STATUS 0xc0010042 319 320 /* K6 MSRs */ 321 #define MSR_K6_WHCR 0xc0000082 322 #define MSR_K6_UWCCR 0xc0000085 323 #define MSR_K6_EPMR 0xc0000086 324 #define MSR_K6_PSOR 0xc0000087 325 #define MSR_K6_PFIR 0xc0000088 326 327 /* Centaur-Hauls/IDT defined MSRs. */ 328 #define MSR_IDT_FCR1 0x00000107 329 #define MSR_IDT_FCR2 0x00000108 330 #define MSR_IDT_FCR3 0x00000109 331 #define MSR_IDT_FCR4 0x0000010a 332 333 #define MSR_IDT_MCR0 0x00000110 334 #define MSR_IDT_MCR1 0x00000111 335 #define MSR_IDT_MCR2 0x00000112 336 #define MSR_IDT_MCR3 0x00000113 337 #define MSR_IDT_MCR4 0x00000114 338 #define MSR_IDT_MCR5 0x00000115 339 #define MSR_IDT_MCR6 0x00000116 340 #define MSR_IDT_MCR7 0x00000117 341 #define MSR_IDT_MCR_CTRL 0x00000120 342 343 /* VIA Cyrix defined MSRs*/ 344 #define MSR_VIA_FCR 0x00001107 345 #define MSR_VIA_LONGHAUL 0x0000110a 346 #define MSR_VIA_RNG 0x0000110b 347 #define MSR_VIA_BCR2 0x00001147 348 349 /* Transmeta defined MSRs */ 350 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 351 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 352 #define MSR_TMTA_LRTI_READOUT 0x80868018 353 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 354 355 /* Intel defined MSRs. */ 356 #define MSR_IA32_P5_MC_ADDR 0x00000000 357 #define MSR_IA32_P5_MC_TYPE 0x00000001 358 #define MSR_IA32_TSC 0x00000010 359 #define MSR_IA32_PLATFORM_ID 0x00000017 360 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 361 #define MSR_EBC_FREQUENCY_ID 0x0000002c 362 #define MSR_SMI_COUNT 0x00000034 363 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 364 #define MSR_IA32_TSC_ADJUST 0x0000003b 365 366 #define FEATURE_CONTROL_LOCKED (1<<0) 367 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 368 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 369 370 #define MSR_IA32_APICBASE 0x0000001b 371 #define MSR_IA32_APICBASE_BSP (1<<8) 372 #define MSR_IA32_APICBASE_ENABLE (1<<11) 373 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 374 375 #define MSR_IA32_TSCDEADLINE 0x000006e0 376 377 #define MSR_IA32_UCODE_WRITE 0x00000079 378 #define MSR_IA32_UCODE_REV 0x0000008b 379 380 #define MSR_IA32_PERF_STATUS 0x00000198 381 #define MSR_IA32_PERF_CTL 0x00000199 382 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 383 #define MSR_AMD_PERF_STATUS 0xc0010063 384 #define MSR_AMD_PERF_CTL 0xc0010062 385 386 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 387 #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 388 #define MSR_IA32_MPERF 0x000000e7 389 #define MSR_IA32_APERF 0x000000e8 390 391 #define MSR_IA32_THERM_CONTROL 0x0000019a 392 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 393 394 #define THERM_INT_HIGH_ENABLE (1 << 0) 395 #define THERM_INT_LOW_ENABLE (1 << 1) 396 #define THERM_INT_PLN_ENABLE (1 << 24) 397 398 #define MSR_IA32_THERM_STATUS 0x0000019c 399 400 #define THERM_STATUS_PROCHOT (1 << 0) 401 #define THERM_STATUS_POWER_LIMIT (1 << 10) 402 403 #define MSR_THERM2_CTL 0x0000019d 404 405 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 406 407 #define MSR_IA32_MISC_ENABLE 0x000001a0 408 #define H_MISC_DISABLE_TURBO (1 << 6) 409 410 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 411 412 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 413 #define ENERGY_PERF_BIAS_PERFORMANCE 0 414 #define ENERGY_PERF_BIAS_NORMAL 6 415 #define ENERGY_PERF_BIAS_POWERSAVE 15 416 417 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 418 419 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 420 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 421 422 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 423 424 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 425 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 426 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 427 428 /* Thermal Thresholds Support */ 429 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 430 #define THERM_SHIFT_THRESHOLD0 8 431 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 432 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 433 #define THERM_SHIFT_THRESHOLD1 16 434 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 435 #define THERM_STATUS_THRESHOLD0 (1 << 6) 436 #define THERM_LOG_THRESHOLD0 (1 << 7) 437 #define THERM_STATUS_THRESHOLD1 (1 << 8) 438 #define THERM_LOG_THRESHOLD1 (1 << 9) 439 440 /* MISC_ENABLE bits: architectural */ 441 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 442 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 443 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 444 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 445 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 446 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 447 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 448 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 449 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 450 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 451 452 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 453 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 454 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 455 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 456 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 457 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 458 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 459 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 460 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 461 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 462 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 463 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 464 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 465 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 466 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 467 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 468 469 #define MSR_IA32_TSC_DEADLINE 0x000006E0 470 471 /* P4/Xeon+ specific */ 472 #define MSR_IA32_MCG_EAX 0x00000180 473 #define MSR_IA32_MCG_EBX 0x00000181 474 #define MSR_IA32_MCG_ECX 0x00000182 475 #define MSR_IA32_MCG_EDX 0x00000183 476 #define MSR_IA32_MCG_ESI 0x00000184 477 #define MSR_IA32_MCG_EDI 0x00000185 478 #define MSR_IA32_MCG_EBP 0x00000186 479 #define MSR_IA32_MCG_ESP 0x00000187 480 #define MSR_IA32_MCG_EFLAGS 0x00000188 481 #define MSR_IA32_MCG_EIP 0x00000189 482 #define MSR_IA32_MCG_RESERVED 0x0000018a 483 484 /* Pentium IV performance counter MSRs */ 485 #define MSR_P4_BPU_PERFCTR0 0x00000300 486 #define MSR_P4_BPU_PERFCTR1 0x00000301 487 #define MSR_P4_BPU_PERFCTR2 0x00000302 488 #define MSR_P4_BPU_PERFCTR3 0x00000303 489 #define MSR_P4_MS_PERFCTR0 0x00000304 490 #define MSR_P4_MS_PERFCTR1 0x00000305 491 #define MSR_P4_MS_PERFCTR2 0x00000306 492 #define MSR_P4_MS_PERFCTR3 0x00000307 493 #define MSR_P4_FLAME_PERFCTR0 0x00000308 494 #define MSR_P4_FLAME_PERFCTR1 0x00000309 495 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 496 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 497 #define MSR_P4_IQ_PERFCTR0 0x0000030c 498 #define MSR_P4_IQ_PERFCTR1 0x0000030d 499 #define MSR_P4_IQ_PERFCTR2 0x0000030e 500 #define MSR_P4_IQ_PERFCTR3 0x0000030f 501 #define MSR_P4_IQ_PERFCTR4 0x00000310 502 #define MSR_P4_IQ_PERFCTR5 0x00000311 503 #define MSR_P4_BPU_CCCR0 0x00000360 504 #define MSR_P4_BPU_CCCR1 0x00000361 505 #define MSR_P4_BPU_CCCR2 0x00000362 506 #define MSR_P4_BPU_CCCR3 0x00000363 507 #define MSR_P4_MS_CCCR0 0x00000364 508 #define MSR_P4_MS_CCCR1 0x00000365 509 #define MSR_P4_MS_CCCR2 0x00000366 510 #define MSR_P4_MS_CCCR3 0x00000367 511 #define MSR_P4_FLAME_CCCR0 0x00000368 512 #define MSR_P4_FLAME_CCCR1 0x00000369 513 #define MSR_P4_FLAME_CCCR2 0x0000036a 514 #define MSR_P4_FLAME_CCCR3 0x0000036b 515 #define MSR_P4_IQ_CCCR0 0x0000036c 516 #define MSR_P4_IQ_CCCR1 0x0000036d 517 #define MSR_P4_IQ_CCCR2 0x0000036e 518 #define MSR_P4_IQ_CCCR3 0x0000036f 519 #define MSR_P4_IQ_CCCR4 0x00000370 520 #define MSR_P4_IQ_CCCR5 0x00000371 521 #define MSR_P4_ALF_ESCR0 0x000003ca 522 #define MSR_P4_ALF_ESCR1 0x000003cb 523 #define MSR_P4_BPU_ESCR0 0x000003b2 524 #define MSR_P4_BPU_ESCR1 0x000003b3 525 #define MSR_P4_BSU_ESCR0 0x000003a0 526 #define MSR_P4_BSU_ESCR1 0x000003a1 527 #define MSR_P4_CRU_ESCR0 0x000003b8 528 #define MSR_P4_CRU_ESCR1 0x000003b9 529 #define MSR_P4_CRU_ESCR2 0x000003cc 530 #define MSR_P4_CRU_ESCR3 0x000003cd 531 #define MSR_P4_CRU_ESCR4 0x000003e0 532 #define MSR_P4_CRU_ESCR5 0x000003e1 533 #define MSR_P4_DAC_ESCR0 0x000003a8 534 #define MSR_P4_DAC_ESCR1 0x000003a9 535 #define MSR_P4_FIRM_ESCR0 0x000003a4 536 #define MSR_P4_FIRM_ESCR1 0x000003a5 537 #define MSR_P4_FLAME_ESCR0 0x000003a6 538 #define MSR_P4_FLAME_ESCR1 0x000003a7 539 #define MSR_P4_FSB_ESCR0 0x000003a2 540 #define MSR_P4_FSB_ESCR1 0x000003a3 541 #define MSR_P4_IQ_ESCR0 0x000003ba 542 #define MSR_P4_IQ_ESCR1 0x000003bb 543 #define MSR_P4_IS_ESCR0 0x000003b4 544 #define MSR_P4_IS_ESCR1 0x000003b5 545 #define MSR_P4_ITLB_ESCR0 0x000003b6 546 #define MSR_P4_ITLB_ESCR1 0x000003b7 547 #define MSR_P4_IX_ESCR0 0x000003c8 548 #define MSR_P4_IX_ESCR1 0x000003c9 549 #define MSR_P4_MOB_ESCR0 0x000003aa 550 #define MSR_P4_MOB_ESCR1 0x000003ab 551 #define MSR_P4_MS_ESCR0 0x000003c0 552 #define MSR_P4_MS_ESCR1 0x000003c1 553 #define MSR_P4_PMH_ESCR0 0x000003ac 554 #define MSR_P4_PMH_ESCR1 0x000003ad 555 #define MSR_P4_RAT_ESCR0 0x000003bc 556 #define MSR_P4_RAT_ESCR1 0x000003bd 557 #define MSR_P4_SAAT_ESCR0 0x000003ae 558 #define MSR_P4_SAAT_ESCR1 0x000003af 559 #define MSR_P4_SSU_ESCR0 0x000003be 560 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 561 562 #define MSR_P4_TBPU_ESCR0 0x000003c2 563 #define MSR_P4_TBPU_ESCR1 0x000003c3 564 #define MSR_P4_TC_ESCR0 0x000003c4 565 #define MSR_P4_TC_ESCR1 0x000003c5 566 #define MSR_P4_U2L_ESCR0 0x000003b0 567 #define MSR_P4_U2L_ESCR1 0x000003b1 568 569 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 570 571 /* Intel Core-based CPU performance counters */ 572 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 573 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 574 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 575 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 576 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 577 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 578 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 579 580 /* Geode defined MSRs */ 581 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 582 583 /* Intel VT MSRs */ 584 #define MSR_IA32_VMX_BASIC 0x00000480 585 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 586 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 587 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 588 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 589 #define MSR_IA32_VMX_MISC 0x00000485 590 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 591 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 592 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 593 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 594 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 595 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 596 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 597 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 598 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 599 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 600 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 601 #define MSR_IA32_VMX_VMFUNC 0x00000491 602 603 /* VMX_BASIC bits and bitmasks */ 604 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 605 #define VMX_BASIC_64 0x0001000000000000LLU 606 #define VMX_BASIC_MEM_TYPE_SHIFT 50 607 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 608 #define VMX_BASIC_MEM_TYPE_WB 6LLU 609 #define VMX_BASIC_INOUT 0x0040000000000000LLU 610 611 /* MSR_IA32_VMX_MISC bits */ 612 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 613 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 614 /* AMD-V MSRs */ 615 616 #define MSR_VM_CR 0xc0010114 617 #define MSR_VM_IGNNE 0xc0010115 618 #define MSR_VM_HSAVE_PA 0xc0010117 619 620 #endif /* _ASM_X86_MSR_INDEX_H */ 621