1 /*-
2 * Copyright (c) 2004 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/lib/msun/mips/fenv.c,v 1.1 2008/04/26 12:20:29 imp Exp $
27 */
28
29 #pragma once
30
31 #include <sys/cdefs.h>
32
33 #if defined(__mips__)
34
35 #if !defined(__BIONIC_FENV_INLINE)
36 #define __BIONIC_FENV_INLINE static __inline
37 #endif
38
39 #include <bits/fenv_mips.h>
40
41 __BEGIN_DECLS
42
43 #define FCSR_CAUSE_SHIFT 10
44 #define FCSR_ENABLE_SHIFT 5
45 #define FCSR_ENABLE_MASK (FE_ALL_EXCEPT << FCSR_ENABLE_SHIFT)
46
47 #define FCSR_RMASK 0x3
48
fegetenv(fenv_t * __envp)49 __BIONIC_FENV_INLINE int fegetenv(fenv_t* __envp) {
50 fenv_t _fcsr = 0;
51 #ifdef __mips_hard_float
52 __asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
53 #endif
54 *__envp = _fcsr;
55 return 0;
56 }
57
fesetenv(const fenv_t * __envp)58 __BIONIC_FENV_INLINE int fesetenv(const fenv_t* __envp) {
59 fenv_t _fcsr = *__envp;
60 #ifdef __mips_hard_float
61 __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
62 #endif
63 return 0;
64 }
65
feclearexcept(int __excepts)66 __BIONIC_FENV_INLINE int feclearexcept(int __excepts) {
67 fexcept_t __fcsr;
68 fegetenv(&__fcsr);
69 __excepts &= FE_ALL_EXCEPT;
70 __fcsr &= ~(__excepts | (__excepts << FCSR_CAUSE_SHIFT));
71 fesetenv(&__fcsr);
72 return 0;
73 }
74
fegetexceptflag(fexcept_t * __flagp,int __excepts)75 __BIONIC_FENV_INLINE int fegetexceptflag(fexcept_t* __flagp, int __excepts) {
76 fexcept_t __fcsr;
77 fegetenv(&__fcsr);
78 *__flagp = __fcsr & __excepts & FE_ALL_EXCEPT;
79 return 0;
80 }
81
fesetexceptflag(const fexcept_t * __flagp,int __excepts)82 __BIONIC_FENV_INLINE int fesetexceptflag(const fexcept_t* __flagp, int __excepts) {
83 fexcept_t __fcsr;
84 fegetenv(&__fcsr);
85 /* Ensure that flags are all legal */
86 __excepts &= FE_ALL_EXCEPT;
87 __fcsr &= ~__excepts;
88 __fcsr |= *__flagp & __excepts;
89 fesetenv(&__fcsr);
90 return 0;
91 }
92
feraiseexcept(int __excepts)93 __BIONIC_FENV_INLINE int feraiseexcept(int __excepts) {
94 fexcept_t __fcsr;
95 fegetenv(&__fcsr);
96 /* Ensure that flags are all legal */
97 __excepts &= FE_ALL_EXCEPT;
98 /* Cause bit needs to be set as well for generating the exception*/
99 __fcsr |= __excepts | (__excepts << FCSR_CAUSE_SHIFT);
100 fesetenv(&__fcsr);
101 return 0;
102 }
103
fetestexcept(int __excepts)104 __BIONIC_FENV_INLINE int fetestexcept(int __excepts) {
105 fexcept_t __FCSR;
106 fegetenv(&__FCSR);
107 return (__FCSR & __excepts & FE_ALL_EXCEPT);
108 }
109
fegetround(void)110 __BIONIC_FENV_INLINE int fegetround(void) {
111 fenv_t _fcsr;
112 fegetenv(&_fcsr);
113 return (_fcsr & FCSR_RMASK);
114 }
115
fesetround(int __round)116 __BIONIC_FENV_INLINE int fesetround(int __round) {
117 fenv_t _fcsr;
118 fegetenv(&_fcsr);
119 _fcsr &= ~FCSR_RMASK;
120 _fcsr |= (__round & FCSR_RMASK);
121 fesetenv(&_fcsr);
122 return 0;
123 }
124
feholdexcept(fenv_t * __envp)125 __BIONIC_FENV_INLINE int feholdexcept(fenv_t* __envp) {
126 fenv_t __env;
127 fegetenv(&__env);
128 *__envp = __env;
129 __env &= ~(FE_ALL_EXCEPT | FCSR_ENABLE_MASK);
130 fesetenv(&__env);
131 return 0;
132 }
133
feupdateenv(const fenv_t * __envp)134 __BIONIC_FENV_INLINE int feupdateenv(const fenv_t* __envp) {
135 fexcept_t __fcsr;
136 fegetenv(&__fcsr);
137 fesetenv(__envp);
138 feraiseexcept(__fcsr & FE_ALL_EXCEPT);
139 return 0;
140 }
141
feenableexcept(int __mask)142 __BIONIC_FENV_INLINE int feenableexcept(int __mask) {
143 fenv_t __old_fcsr, __new_fcsr;
144 fegetenv(&__old_fcsr);
145 __new_fcsr = __old_fcsr | (__mask & FE_ALL_EXCEPT) << FCSR_ENABLE_SHIFT;
146 fesetenv(&__new_fcsr);
147 return ((__old_fcsr >> FCSR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
148 }
149
fedisableexcept(int __mask)150 __BIONIC_FENV_INLINE int fedisableexcept(int __mask) {
151 fenv_t __old_fcsr, __new_fcsr;
152 fegetenv(&__old_fcsr);
153 __new_fcsr = __old_fcsr & ~((__mask & FE_ALL_EXCEPT) << FCSR_ENABLE_SHIFT);
154 fesetenv(&__new_fcsr);
155 return ((__old_fcsr >> FCSR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
156 }
157
fegetexcept(void)158 __BIONIC_FENV_INLINE int fegetexcept(void) {
159 fenv_t __fcsr;
160 fegetenv(&__fcsr);
161 return ((__fcsr & FCSR_ENABLE_MASK) >> FCSR_ENABLE_SHIFT);
162 }
163
164 #undef FCSR_CAUSE_SHIFT
165 #undef FCSR_ENABLE_SHIFT
166 #undef FCSR_ENABLE_MASK
167 #undef FCSR_RMASK
168
169 __END_DECLS
170
171 #endif
172