1 /*
2 * Copyright 2003 VMware, Inc.
3 * Copyright 2009, 2012 Intel Corporation.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "main/mtypes.h"
28 #include "main/condrender.h"
29 #include "swrast/swrast.h"
30 #include "drivers/common/meta.h"
31
32 #include "intel_batchbuffer.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
35 #include "intel_mipmap_tree.h"
36
37 #include "brw_context.h"
38 #include "brw_blorp.h"
39 #include "brw_defines.h"
40
41 #define FILE_DEBUG_FLAG DEBUG_BLIT
42
43 static const char *buffer_names[] = {
44 [BUFFER_FRONT_LEFT] = "front",
45 [BUFFER_BACK_LEFT] = "back",
46 [BUFFER_FRONT_RIGHT] = "front right",
47 [BUFFER_BACK_RIGHT] = "back right",
48 [BUFFER_DEPTH] = "depth",
49 [BUFFER_STENCIL] = "stencil",
50 [BUFFER_ACCUM] = "accum",
51 [BUFFER_AUX0] = "aux0",
52 [BUFFER_COLOR0] = "color0",
53 [BUFFER_COLOR1] = "color1",
54 [BUFFER_COLOR2] = "color2",
55 [BUFFER_COLOR3] = "color3",
56 [BUFFER_COLOR4] = "color4",
57 [BUFFER_COLOR5] = "color5",
58 [BUFFER_COLOR6] = "color6",
59 [BUFFER_COLOR7] = "color7",
60 };
61
62 static void
debug_mask(const char * name,GLbitfield mask)63 debug_mask(const char *name, GLbitfield mask)
64 {
65 GLuint i;
66
67 if (unlikely(INTEL_DEBUG & DEBUG_BLIT)) {
68 DBG("%s clear:", name);
69 for (i = 0; i < BUFFER_COUNT; i++) {
70 if (mask & (1 << i))
71 DBG(" %s", buffer_names[i]);
72 }
73 DBG("\n");
74 }
75 }
76
77 /**
78 * Returns true if the scissor is a noop (cuts out nothing).
79 */
80 static bool
noop_scissor(struct gl_framebuffer * fb)81 noop_scissor(struct gl_framebuffer *fb)
82 {
83 return fb->_Xmin <= 0 &&
84 fb->_Ymin <= 0 &&
85 fb->_Xmax >= fb->Width &&
86 fb->_Ymax >= fb->Height;
87 }
88
89 /**
90 * Implements fast depth clears on gen6+.
91 *
92 * Fast clears basically work by setting a flag in each of the subspans
93 * represented in the HiZ buffer that says "When you need the depth values for
94 * this subspan, it's the hardware's current clear value." Then later rendering
95 * can just use the static clear value instead of referencing memory.
96 *
97 * The tricky part of the implementation is that you have to have the clear
98 * value that was used on the depth buffer in place for all further rendering,
99 * at least until a resolve to the real depth buffer happens.
100 */
101 static bool
brw_fast_clear_depth(struct gl_context * ctx)102 brw_fast_clear_depth(struct gl_context *ctx)
103 {
104 struct brw_context *brw = brw_context(ctx);
105 struct gl_framebuffer *fb = ctx->DrawBuffer;
106 struct intel_renderbuffer *depth_irb =
107 intel_get_renderbuffer(fb, BUFFER_DEPTH);
108 struct intel_mipmap_tree *mt = depth_irb->mt;
109 struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
110 const struct gen_device_info *devinfo = &brw->screen->devinfo;
111
112 if (devinfo->gen < 6)
113 return false;
114
115 if (!intel_renderbuffer_has_hiz(depth_irb))
116 return false;
117
118 /* We only handle full buffer clears -- otherwise you'd have to track whether
119 * a previous clear had happened at a different clear value and resolve it
120 * first.
121 */
122 if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
123 perf_debug("Failed to fast clear %dx%d depth because of scissors. "
124 "Possible 5%% performance win if avoided.\n",
125 mt->surf.logical_level0_px.width,
126 mt->surf.logical_level0_px.height);
127 return false;
128 }
129
130 switch (mt->format) {
131 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
132 case MESA_FORMAT_Z24_UNORM_S8_UINT:
133 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
134 *
135 * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
136 * enabled (the legacy method of clearing must be performed):
137 *
138 * - If the depth buffer format is D32_FLOAT_S8X24_UINT or
139 * D24_UNORM_S8_UINT.
140 */
141 return false;
142
143 case MESA_FORMAT_Z_UNORM16:
144 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
145 *
146 * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
147 * enabled (the legacy method of clearing must be performed):
148 *
149 * - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
150 * width of the map (LOD0) is not multiple of 16, fast clear
151 * optimization must be disabled.
152 */
153 if (devinfo->gen == 6 &&
154 (minify(mt->surf.phys_level0_sa.width,
155 depth_irb->mt_level - mt->first_level) % 16) != 0)
156 return false;
157 break;
158
159 default:
160 break;
161 }
162
163 /* Quantize the clear value to what can be stored in the actual depth
164 * buffer. This makes the following check more accurate because it now
165 * checks if the actual depth bits will match. It also prevents us from
166 * getting a too-accurate depth value during depth testing or when sampling
167 * with HiZ enabled.
168 */
169 float clear_value =
170 mt->format == MESA_FORMAT_Z_FLOAT32 ? ctx->Depth.Clear :
171 (unsigned)(ctx->Depth.Clear * fb->_DepthMax) / (float)fb->_DepthMax;
172
173 const uint32_t num_layers = depth_att->Layered ? depth_irb->layer_count : 1;
174
175 /* If we're clearing to a new clear value, then we need to resolve any clear
176 * flags out of the HiZ buffer into the real depth buffer.
177 */
178 if (mt->fast_clear_color.f32[0] != clear_value) {
179 for (uint32_t level = mt->first_level; level <= mt->last_level; level++) {
180 if (!intel_miptree_level_has_hiz(mt, level))
181 continue;
182
183 const unsigned level_layers = brw_get_num_logical_layers(mt, level);
184
185 for (uint32_t layer = 0; layer < level_layers; layer++) {
186 if (level == depth_irb->mt_level &&
187 layer >= depth_irb->mt_layer &&
188 layer < depth_irb->mt_layer + num_layers) {
189 /* We're going to clear this layer anyway. Leave it alone. */
190 continue;
191 }
192
193 enum isl_aux_state aux_state =
194 intel_miptree_get_aux_state(mt, level, layer);
195
196 if (aux_state != ISL_AUX_STATE_CLEAR &&
197 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
198 /* This slice doesn't have any fast-cleared bits. */
199 continue;
200 }
201
202 /* If we got here, then the level may have fast-clear bits that
203 * use the old clear value. We need to do a depth resolve to get
204 * rid of their use of the clear value before we can change it.
205 * Fortunately, few applications ever change their depth clear
206 * value so this shouldn't happen often.
207 */
208 intel_hiz_exec(brw, mt, level, layer, 1,
209 BLORP_HIZ_OP_DEPTH_RESOLVE);
210 intel_miptree_set_aux_state(brw, mt, level, layer, 1,
211 ISL_AUX_STATE_RESOLVED);
212 }
213 }
214
215 intel_miptree_set_depth_clear_value(ctx, mt, clear_value);
216 }
217
218 bool need_clear = false;
219 for (unsigned a = 0; a < num_layers; a++) {
220 enum isl_aux_state aux_state =
221 intel_miptree_get_aux_state(mt, depth_irb->mt_level,
222 depth_irb->mt_layer + a);
223
224 if (aux_state != ISL_AUX_STATE_CLEAR) {
225 need_clear = true;
226 break;
227 }
228 }
229
230 if (!need_clear) {
231 /* If all of the layers we intend to clear are already in the clear
232 * state then simply updating the miptree fast clear value is sufficient
233 * to change their clear value.
234 */
235 return true;
236 }
237
238 for (unsigned a = 0; a < num_layers; a++) {
239 enum isl_aux_state aux_state =
240 intel_miptree_get_aux_state(mt, depth_irb->mt_level,
241 depth_irb->mt_layer + a);
242
243 if (aux_state != ISL_AUX_STATE_CLEAR) {
244 intel_hiz_exec(brw, mt, depth_irb->mt_level,
245 depth_irb->mt_layer + a, 1,
246 BLORP_HIZ_OP_DEPTH_CLEAR);
247 }
248 }
249
250 /* Now, the HiZ buffer contains data that needs to be resolved to the depth
251 * buffer.
252 */
253 intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
254 depth_irb->mt_layer, num_layers,
255 ISL_AUX_STATE_CLEAR);
256
257 return true;
258 }
259
260 /**
261 * Called by ctx->Driver.Clear.
262 */
263 static void
brw_clear(struct gl_context * ctx,GLbitfield mask)264 brw_clear(struct gl_context *ctx, GLbitfield mask)
265 {
266 struct brw_context *brw = brw_context(ctx);
267 struct gl_framebuffer *fb = ctx->DrawBuffer;
268 const struct gen_device_info *devinfo = &brw->screen->devinfo;
269 bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb);
270
271 if (!_mesa_check_conditional_render(ctx))
272 return;
273
274 if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
275 brw->front_buffer_dirty = true;
276 }
277
278 intel_prepare_render(brw);
279 brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask);
280
281 if (mask & BUFFER_BIT_DEPTH) {
282 if (brw_fast_clear_depth(ctx)) {
283 DBG("fast clear: depth\n");
284 mask &= ~BUFFER_BIT_DEPTH;
285 }
286 }
287
288 if (mask & BUFFER_BIT_STENCIL) {
289 struct intel_renderbuffer *stencil_irb =
290 intel_get_renderbuffer(fb, BUFFER_STENCIL);
291 struct intel_mipmap_tree *mt = stencil_irb->mt;
292 if (mt && mt->stencil_mt)
293 mt->stencil_mt->r8stencil_needs_update = true;
294 }
295
296 if (mask & BUFFER_BITS_COLOR) {
297 brw_blorp_clear_color(brw, fb, mask, partial_clear,
298 ctx->Color.sRGBEnabled);
299 debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
300 mask &= ~BUFFER_BITS_COLOR;
301 }
302
303 if (devinfo->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {
304 brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear);
305 debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);
306 mask &= ~BUFFER_BITS_DEPTH_STENCIL;
307 }
308
309 GLbitfield tri_mask = mask & (BUFFER_BIT_STENCIL |
310 BUFFER_BIT_DEPTH);
311
312 if (tri_mask) {
313 debug_mask("tri", tri_mask);
314 mask &= ~tri_mask;
315 _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
316 }
317
318 /* Any strange buffers get passed off to swrast. The only thing that
319 * should be left at this point is the accumulation buffer.
320 */
321 assert((mask & ~BUFFER_BIT_ACCUM) == 0);
322 if (mask) {
323 debug_mask("swrast", mask);
324 _swrast_Clear(ctx, mask);
325 }
326 }
327
328
329 void
intelInitClearFuncs(struct dd_function_table * functions)330 intelInitClearFuncs(struct dd_function_table *functions)
331 {
332 functions->Clear = brw_clear;
333 }
334