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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  * (C) Copyright 2002-2006
5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6  *
7  * (C) Copyright 2002
8  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9  * Marius Groeger <mgroeger@sysgo.de>
10  */
11 
12 #include <common.h>
13 #include <console.h>
14 #include <environment.h>
15 #include <dm.h>
16 #include <fdtdec.h>
17 #include <fs.h>
18 #include <i2c.h>
19 #include <initcall.h>
20 #include <malloc.h>
21 #include <mapmem.h>
22 #include <os.h>
23 #include <post.h>
24 #include <relocate.h>
25 #include <spi.h>
26 #include <status_led.h>
27 #include <timer.h>
28 #include <trace.h>
29 #include <video.h>
30 #include <watchdog.h>
31 #ifdef CONFIG_MACH_TYPE
32 #include <asm/mach-types.h>
33 #endif
34 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
35 #include <asm/mp.h>
36 #endif
37 #include <asm/io.h>
38 #include <asm/sections.h>
39 #include <dm/root.h>
40 #include <linux/errno.h>
41 
42 /*
43  * Pointer to initial global data area
44  *
45  * Here we initialize it if needed.
46  */
47 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
48 #undef	XTRN_DECLARE_GLOBAL_DATA_PTR
49 #define XTRN_DECLARE_GLOBAL_DATA_PTR	/* empty = allocate here */
50 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
51 #else
52 DECLARE_GLOBAL_DATA_PTR;
53 #endif
54 
55 /*
56  * TODO(sjg@chromium.org): IMO this code should be
57  * refactored to a single function, something like:
58  *
59  * void led_set_state(enum led_colour_t colour, int on);
60  */
61 /************************************************************************
62  * Coloured LED functionality
63  ************************************************************************
64  * May be supplied by boards if desired
65  */
coloured_LED_init(void)66 __weak void coloured_LED_init(void) {}
red_led_on(void)67 __weak void red_led_on(void) {}
red_led_off(void)68 __weak void red_led_off(void) {}
green_led_on(void)69 __weak void green_led_on(void) {}
green_led_off(void)70 __weak void green_led_off(void) {}
yellow_led_on(void)71 __weak void yellow_led_on(void) {}
yellow_led_off(void)72 __weak void yellow_led_off(void) {}
blue_led_on(void)73 __weak void blue_led_on(void) {}
blue_led_off(void)74 __weak void blue_led_off(void) {}
75 
76 /*
77  * Why is gd allocated a register? Prior to reloc it might be better to
78  * just pass it around to each function in this file?
79  *
80  * After reloc one could argue that it is hardly used and doesn't need
81  * to be in a register. Or if it is it should perhaps hold pointers to all
82  * global data for all modules, so that post-reloc we can avoid the massive
83  * literal pool we get on ARM. Or perhaps just encourage each module to use
84  * a structure...
85  */
86 
87 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
init_func_watchdog_init(void)88 static int init_func_watchdog_init(void)
89 {
90 # if defined(CONFIG_HW_WATCHDOG) && \
91 	(defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
92 	defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
93 	defined(CONFIG_DESIGNWARE_WATCHDOG) || \
94 	defined(CONFIG_IMX_WATCHDOG))
95 	hw_watchdog_init();
96 	puts("       Watchdog enabled\n");
97 # endif
98 	WATCHDOG_RESET();
99 
100 	return 0;
101 }
102 
init_func_watchdog_reset(void)103 int init_func_watchdog_reset(void)
104 {
105 	WATCHDOG_RESET();
106 
107 	return 0;
108 }
109 #endif /* CONFIG_WATCHDOG */
110 
board_add_ram_info(int use_default)111 __weak void board_add_ram_info(int use_default)
112 {
113 	/* please define platform specific board_add_ram_info() */
114 }
115 
init_baud_rate(void)116 static int init_baud_rate(void)
117 {
118 	gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
119 	return 0;
120 }
121 
display_text_info(void)122 static int display_text_info(void)
123 {
124 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
125 	ulong bss_start, bss_end, text_base;
126 
127 	bss_start = (ulong)&__bss_start;
128 	bss_end = (ulong)&__bss_end;
129 
130 #ifdef CONFIG_SYS_TEXT_BASE
131 	text_base = CONFIG_SYS_TEXT_BASE;
132 #else
133 	text_base = CONFIG_SYS_MONITOR_BASE;
134 #endif
135 
136 	debug("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
137 	      text_base, bss_start, bss_end);
138 #endif
139 
140 	return 0;
141 }
142 
announce_dram_init(void)143 static int announce_dram_init(void)
144 {
145 	puts("DRAM:  ");
146 	return 0;
147 }
148 
show_dram_config(void)149 static int show_dram_config(void)
150 {
151 	unsigned long long size;
152 
153 #ifdef CONFIG_NR_DRAM_BANKS
154 	int i;
155 
156 	debug("\nRAM Configuration:\n");
157 	for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
158 		size += gd->bd->bi_dram[i].size;
159 		debug("Bank #%d: %llx ", i,
160 		      (unsigned long long)(gd->bd->bi_dram[i].start));
161 #ifdef DEBUG
162 		print_size(gd->bd->bi_dram[i].size, "\n");
163 #endif
164 	}
165 	debug("\nDRAM:  ");
166 #else
167 	size = gd->ram_size;
168 #endif
169 
170 	print_size(size, "");
171 	board_add_ram_info(0);
172 	putc('\n');
173 
174 	return 0;
175 }
176 
dram_init_banksize(void)177 __weak int dram_init_banksize(void)
178 {
179 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
180 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
181 	gd->bd->bi_dram[0].size = get_effective_memsize();
182 #endif
183 
184 	return 0;
185 }
186 
187 #if defined(CONFIG_SYS_I2C)
init_func_i2c(void)188 static int init_func_i2c(void)
189 {
190 	puts("I2C:   ");
191 #ifdef CONFIG_SYS_I2C
192 	i2c_init_all();
193 #else
194 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
195 #endif
196 	puts("ready\n");
197 	return 0;
198 }
199 #endif
200 
201 #if defined(CONFIG_VID)
init_func_vid(void)202 __weak int init_func_vid(void)
203 {
204 	return 0;
205 }
206 #endif
207 
208 #if defined(CONFIG_HARD_SPI)
init_func_spi(void)209 static int init_func_spi(void)
210 {
211 	puts("SPI:   ");
212 	spi_init();
213 	puts("ready\n");
214 	return 0;
215 }
216 #endif
217 
setup_mon_len(void)218 static int setup_mon_len(void)
219 {
220 #if defined(__ARM__) || defined(__MICROBLAZE__)
221 	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
222 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
223 	gd->mon_len = (ulong)&_end - (ulong)_init;
224 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
225 	gd->mon_len = CONFIG_SYS_MONITOR_LEN;
226 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
227 	gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
228 #elif defined(CONFIG_SYS_MONITOR_BASE)
229 	/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
230 	gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
231 #endif
232 	return 0;
233 }
234 
arch_cpu_init(void)235 __weak int arch_cpu_init(void)
236 {
237 	return 0;
238 }
239 
mach_cpu_init(void)240 __weak int mach_cpu_init(void)
241 {
242 	return 0;
243 }
244 
245 /* Get the top of usable RAM */
board_get_usable_ram_top(ulong total_size)246 __weak ulong board_get_usable_ram_top(ulong total_size)
247 {
248 #ifdef CONFIG_SYS_SDRAM_BASE
249 	/*
250 	 * Detect whether we have so much RAM that it goes past the end of our
251 	 * 32-bit address space. If so, clip the usable RAM so it doesn't.
252 	 */
253 	if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
254 		/*
255 		 * Will wrap back to top of 32-bit space when reservations
256 		 * are made.
257 		 */
258 		return 0;
259 #endif
260 	return gd->ram_top;
261 }
262 
setup_dest_addr(void)263 static int setup_dest_addr(void)
264 {
265 	debug("Monitor len: %08lX\n", gd->mon_len);
266 	/*
267 	 * Ram is setup, size stored in gd !!
268 	 */
269 	debug("Ram size: %08lX\n", (ulong)gd->ram_size);
270 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
271 	/*
272 	 * Subtract specified amount of memory to hide so that it won't
273 	 * get "touched" at all by U-Boot. By fixing up gd->ram_size
274 	 * the Linux kernel should now get passed the now "corrected"
275 	 * memory size and won't touch it either. This should work
276 	 * for arch/ppc and arch/powerpc. Only Linux board ports in
277 	 * arch/powerpc with bootwrapper support, that recalculate the
278 	 * memory size from the SDRAM controller setup will have to
279 	 * get fixed.
280 	 */
281 	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
282 #endif
283 #ifdef CONFIG_SYS_SDRAM_BASE
284 	gd->ram_top = CONFIG_SYS_SDRAM_BASE;
285 #endif
286 	gd->ram_top += get_effective_memsize();
287 	gd->ram_top = board_get_usable_ram_top(gd->mon_len);
288 	gd->relocaddr = gd->ram_top;
289 	debug("Ram top: %08lX\n", (ulong)gd->ram_top);
290 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
291 	/*
292 	 * We need to make sure the location we intend to put secondary core
293 	 * boot code is reserved and not used by any part of u-boot
294 	 */
295 	if (gd->relocaddr > determine_mp_bootpg(NULL)) {
296 		gd->relocaddr = determine_mp_bootpg(NULL);
297 		debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
298 	}
299 #endif
300 	return 0;
301 }
302 
303 #ifdef CONFIG_PRAM
304 /* reserve protected RAM */
reserve_pram(void)305 static int reserve_pram(void)
306 {
307 	ulong reg;
308 
309 	reg = env_get_ulong("pram", 10, CONFIG_PRAM);
310 	gd->relocaddr -= (reg << 10);		/* size is in kB */
311 	debug("Reserving %ldk for protected RAM at %08lx\n", reg,
312 	      gd->relocaddr);
313 	return 0;
314 }
315 #endif /* CONFIG_PRAM */
316 
317 /* Round memory pointer down to next 4 kB limit */
reserve_round_4k(void)318 static int reserve_round_4k(void)
319 {
320 	gd->relocaddr &= ~(4096 - 1);
321 	return 0;
322 }
323 
324 #ifdef CONFIG_ARM
reserve_mmu(void)325 __weak int reserve_mmu(void)
326 {
327 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
328 	/* reserve TLB table */
329 	gd->arch.tlb_size = PGTABLE_SIZE;
330 	gd->relocaddr -= gd->arch.tlb_size;
331 
332 	/* round down to next 64 kB limit */
333 	gd->relocaddr &= ~(0x10000 - 1);
334 
335 	gd->arch.tlb_addr = gd->relocaddr;
336 	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
337 	      gd->arch.tlb_addr + gd->arch.tlb_size);
338 
339 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
340 	/*
341 	 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
342 	 * with location within secure ram.
343 	 */
344 	gd->arch.tlb_allocated = gd->arch.tlb_addr;
345 #endif
346 #endif
347 
348 	return 0;
349 }
350 #endif
351 
reserve_video(void)352 static int reserve_video(void)
353 {
354 #ifdef CONFIG_DM_VIDEO
355 	ulong addr;
356 	int ret;
357 
358 	addr = gd->relocaddr;
359 	ret = video_reserve(&addr);
360 	if (ret)
361 		return ret;
362 	gd->relocaddr = addr;
363 #elif defined(CONFIG_LCD)
364 #  ifdef CONFIG_FB_ADDR
365 	gd->fb_base = CONFIG_FB_ADDR;
366 #  else
367 	/* reserve memory for LCD display (always full pages) */
368 	gd->relocaddr = lcd_setmem(gd->relocaddr);
369 	gd->fb_base = gd->relocaddr;
370 #  endif /* CONFIG_FB_ADDR */
371 #elif defined(CONFIG_VIDEO) && \
372 		(!defined(CONFIG_PPC)) && \
373 		!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
374 		!defined(CONFIG_M68K)
375 	/* reserve memory for video display (always full pages) */
376 	gd->relocaddr = video_setmem(gd->relocaddr);
377 	gd->fb_base = gd->relocaddr;
378 #endif
379 
380 	return 0;
381 }
382 
reserve_trace(void)383 static int reserve_trace(void)
384 {
385 #ifdef CONFIG_TRACE
386 	gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
387 	gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
388 	debug("Reserving %dk for trace data at: %08lx\n",
389 	      CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
390 #endif
391 
392 	return 0;
393 }
394 
reserve_uboot(void)395 static int reserve_uboot(void)
396 {
397 	if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
398 		/*
399 		 * reserve memory for U-Boot code, data & bss
400 		 * round down to next 4 kB limit
401 		 */
402 		gd->relocaddr -= gd->mon_len;
403 		gd->relocaddr &= ~(4096 - 1);
404 	#if defined(CONFIG_E500) || defined(CONFIG_MIPS)
405 		/* round down to next 64 kB limit so that IVPR stays aligned */
406 		gd->relocaddr &= ~(65536 - 1);
407 	#endif
408 
409 		debug("Reserving %ldk for U-Boot at: %08lx\n",
410 		      gd->mon_len >> 10, gd->relocaddr);
411 	}
412 
413 	gd->start_addr_sp = gd->relocaddr;
414 
415 	return 0;
416 }
417 
418 /* reserve memory for malloc() area */
reserve_malloc(void)419 static int reserve_malloc(void)
420 {
421 	gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
422 	debug("Reserving %dk for malloc() at: %08lx\n",
423 	      TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
424 	return 0;
425 }
426 
427 /* (permanently) allocate a Board Info struct */
reserve_board(void)428 static int reserve_board(void)
429 {
430 	if (!gd->bd) {
431 		gd->start_addr_sp -= sizeof(bd_t);
432 		gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
433 		memset(gd->bd, '\0', sizeof(bd_t));
434 		debug("Reserving %zu Bytes for Board Info at: %08lx\n",
435 		      sizeof(bd_t), gd->start_addr_sp);
436 	}
437 	return 0;
438 }
439 
setup_machine(void)440 static int setup_machine(void)
441 {
442 #ifdef CONFIG_MACH_TYPE
443 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
444 #endif
445 	return 0;
446 }
447 
reserve_global_data(void)448 static int reserve_global_data(void)
449 {
450 	gd->start_addr_sp -= sizeof(gd_t);
451 	gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
452 	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
453 	      sizeof(gd_t), gd->start_addr_sp);
454 	return 0;
455 }
456 
reserve_fdt(void)457 static int reserve_fdt(void)
458 {
459 #ifndef CONFIG_OF_EMBED
460 	/*
461 	 * If the device tree is sitting immediately above our image then we
462 	 * must relocate it. If it is embedded in the data section, then it
463 	 * will be relocated with other data.
464 	 */
465 	if (gd->fdt_blob) {
466 		gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
467 
468 		gd->start_addr_sp -= gd->fdt_size;
469 		gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
470 		debug("Reserving %lu Bytes for FDT at: %08lx\n",
471 		      gd->fdt_size, gd->start_addr_sp);
472 	}
473 #endif
474 
475 	return 0;
476 }
477 
reserve_bootstage(void)478 static int reserve_bootstage(void)
479 {
480 #ifdef CONFIG_BOOTSTAGE
481 	int size = bootstage_get_size();
482 
483 	gd->start_addr_sp -= size;
484 	gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
485 	debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
486 	      gd->start_addr_sp);
487 #endif
488 
489 	return 0;
490 }
491 
arch_reserve_stacks(void)492 __weak int arch_reserve_stacks(void)
493 {
494 	return 0;
495 }
496 
reserve_stacks(void)497 static int reserve_stacks(void)
498 {
499 	/* make stack pointer 16-byte aligned */
500 	gd->start_addr_sp -= 16;
501 	gd->start_addr_sp &= ~0xf;
502 
503 	/*
504 	 * let the architecture-specific code tailor gd->start_addr_sp and
505 	 * gd->irq_sp
506 	 */
507 	return arch_reserve_stacks();
508 }
509 
display_new_sp(void)510 static int display_new_sp(void)
511 {
512 	debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
513 
514 	return 0;
515 }
516 
517 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
518 	defined(CONFIG_SH)
setup_board_part1(void)519 static int setup_board_part1(void)
520 {
521 	bd_t *bd = gd->bd;
522 
523 	/*
524 	 * Save local variables to board info struct
525 	 */
526 	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;	/* start of memory */
527 	bd->bi_memsize = gd->ram_size;			/* size in bytes */
528 
529 #ifdef CONFIG_SYS_SRAM_BASE
530 	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;	/* start of SRAM */
531 	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;		/* size  of SRAM */
532 #endif
533 
534 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
535 	bd->bi_immr_base = CONFIG_SYS_IMMR;	/* base  of IMMR register     */
536 #endif
537 #if defined(CONFIG_M68K)
538 	bd->bi_mbar_base = CONFIG_SYS_MBAR;	/* base of internal registers */
539 #endif
540 #if defined(CONFIG_MPC83xx)
541 	bd->bi_immrbar = CONFIG_SYS_IMMR;
542 #endif
543 
544 	return 0;
545 }
546 #endif
547 
548 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
setup_board_part2(void)549 static int setup_board_part2(void)
550 {
551 	bd_t *bd = gd->bd;
552 
553 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
554 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
555 #if defined(CONFIG_CPM2)
556 	bd->bi_cpmfreq = gd->arch.cpm_clk;
557 	bd->bi_brgfreq = gd->arch.brg_clk;
558 	bd->bi_sccfreq = gd->arch.scc_clk;
559 	bd->bi_vco = gd->arch.vco_out;
560 #endif /* CONFIG_CPM2 */
561 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
562 	bd->bi_pcifreq = gd->pci_clk;
563 #endif
564 #if defined(CONFIG_EXTRA_CLOCK)
565 	bd->bi_inpfreq = gd->arch.inp_clk;	/* input Freq in Hz */
566 	bd->bi_vcofreq = gd->arch.vco_clk;	/* vco Freq in Hz */
567 	bd->bi_flbfreq = gd->arch.flb_clk;	/* flexbus Freq in Hz */
568 #endif
569 
570 	return 0;
571 }
572 #endif
573 
574 #ifdef CONFIG_POST
init_post(void)575 static int init_post(void)
576 {
577 	post_bootmode_init();
578 	post_run(NULL, POST_ROM | post_bootmode_get(0));
579 
580 	return 0;
581 }
582 #endif
583 
reloc_fdt(void)584 static int reloc_fdt(void)
585 {
586 #ifndef CONFIG_OF_EMBED
587 	if (gd->flags & GD_FLG_SKIP_RELOC)
588 		return 0;
589 	if (gd->new_fdt) {
590 		memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
591 		gd->fdt_blob = gd->new_fdt;
592 	}
593 #endif
594 
595 	return 0;
596 }
597 
reloc_bootstage(void)598 static int reloc_bootstage(void)
599 {
600 #ifdef CONFIG_BOOTSTAGE
601 	if (gd->flags & GD_FLG_SKIP_RELOC)
602 		return 0;
603 	if (gd->new_bootstage) {
604 		int size = bootstage_get_size();
605 
606 		debug("Copying bootstage from %p to %p, size %x\n",
607 		      gd->bootstage, gd->new_bootstage, size);
608 		memcpy(gd->new_bootstage, gd->bootstage, size);
609 		gd->bootstage = gd->new_bootstage;
610 	}
611 #endif
612 
613 	return 0;
614 }
615 
setup_reloc(void)616 static int setup_reloc(void)
617 {
618 	if (gd->flags & GD_FLG_SKIP_RELOC) {
619 		debug("Skipping relocation due to flag\n");
620 		return 0;
621 	}
622 
623 #ifdef CONFIG_SYS_TEXT_BASE
624 #ifdef ARM
625 	gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
626 #elif defined(CONFIG_M68K)
627 	/*
628 	 * On all ColdFire arch cpu, monitor code starts always
629 	 * just after the default vector table location, so at 0x400
630 	 */
631 	gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
632 #else
633 	gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
634 #endif
635 #endif
636 	memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
637 
638 	debug("Relocation Offset is: %08lx\n", gd->reloc_off);
639 	debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
640 	      gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
641 	      gd->start_addr_sp);
642 
643 	return 0;
644 }
645 
646 #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt(void)647 static int fix_fdt(void)
648 {
649 	return board_fix_fdt((void *)gd->fdt_blob);
650 }
651 #endif
652 
653 /* ARM calls relocate_code from its crt0.S */
654 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
655 		!CONFIG_IS_ENABLED(X86_64)
656 
jump_to_copy(void)657 static int jump_to_copy(void)
658 {
659 	if (gd->flags & GD_FLG_SKIP_RELOC)
660 		return 0;
661 	/*
662 	 * x86 is special, but in a nice way. It uses a trampoline which
663 	 * enables the dcache if possible.
664 	 *
665 	 * For now, other archs use relocate_code(), which is implemented
666 	 * similarly for all archs. When we do generic relocation, hopefully
667 	 * we can make all archs enable the dcache prior to relocation.
668 	 */
669 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
670 	/*
671 	 * SDRAM and console are now initialised. The final stack can now
672 	 * be setup in SDRAM. Code execution will continue in Flash, but
673 	 * with the stack in SDRAM and Global Data in temporary memory
674 	 * (CPU cache)
675 	 */
676 	arch_setup_gd(gd->new_gd);
677 	board_init_f_r_trampoline(gd->start_addr_sp);
678 #else
679 	relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
680 #endif
681 
682 	return 0;
683 }
684 #endif
685 
686 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
initf_bootstage(void)687 static int initf_bootstage(void)
688 {
689 	bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
690 			IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
691 	int ret;
692 
693 	ret = bootstage_init(!from_spl);
694 	if (ret)
695 		return ret;
696 	if (from_spl) {
697 		const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
698 					       CONFIG_BOOTSTAGE_STASH_SIZE);
699 
700 		ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
701 		if (ret && ret != -ENOENT) {
702 			debug("Failed to unstash bootstage: err=%d\n", ret);
703 			return ret;
704 		}
705 	}
706 
707 	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
708 
709 	return 0;
710 }
711 
initf_console_record(void)712 static int initf_console_record(void)
713 {
714 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
715 	return console_record_init();
716 #else
717 	return 0;
718 #endif
719 }
720 
initf_dm(void)721 static int initf_dm(void)
722 {
723 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
724 	int ret;
725 
726 	bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
727 	ret = dm_init_and_scan(true);
728 	bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
729 	if (ret)
730 		return ret;
731 #endif
732 #ifdef CONFIG_TIMER_EARLY
733 	ret = dm_timer_init();
734 	if (ret)
735 		return ret;
736 #endif
737 
738 	return 0;
739 }
740 
741 /* Architecture-specific memory reservation */
reserve_arch(void)742 __weak int reserve_arch(void)
743 {
744 	return 0;
745 }
746 
arch_cpu_init_dm(void)747 __weak int arch_cpu_init_dm(void)
748 {
749 	return 0;
750 }
751 
752 static const init_fnc_t init_sequence_f[] = {
753 	setup_mon_len,
754 #ifdef CONFIG_OF_CONTROL
755 	fdtdec_setup,
756 #endif
757 #ifdef CONFIG_TRACE
758 	trace_early_init,
759 #endif
760 	initf_malloc,
761 	log_init,
762 	initf_bootstage,	/* uses its own timer, so does not need DM */
763 	initf_console_record,
764 #if defined(CONFIG_HAVE_FSP)
765 	arch_fsp_init,
766 #endif
767 	arch_cpu_init,		/* basic arch cpu dependent setup */
768 	mach_cpu_init,		/* SoC/machine dependent CPU setup */
769 	initf_dm,
770 	arch_cpu_init_dm,
771 #if defined(CONFIG_BOARD_EARLY_INIT_F)
772 	board_early_init_f,
773 #endif
774 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
775 	/* get CPU and bus clocks according to the environment variable */
776 	get_clocks,		/* get CPU and bus clocks (etc.) */
777 #endif
778 #if !defined(CONFIG_M68K)
779 	timer_init,		/* initialize timer */
780 #endif
781 #if defined(CONFIG_BOARD_POSTCLK_INIT)
782 	board_postclk_init,
783 #endif
784 	env_init,		/* initialize environment */
785 	init_baud_rate,		/* initialze baudrate settings */
786 	serial_init,		/* serial communications setup */
787 	console_init_f,		/* stage 1 init of console */
788 	display_options,	/* say that we are here */
789 	display_text_info,	/* show debugging info if required */
790 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
791 	checkcpu,
792 #endif
793 #if defined(CONFIG_DISPLAY_CPUINFO)
794 	print_cpuinfo,		/* display cpu info (and speed) */
795 #endif
796 #if defined(CONFIG_DTB_RESELECT)
797 	embedded_dtb_select,
798 #endif
799 #if defined(CONFIG_DISPLAY_BOARDINFO)
800 	show_board_info,
801 #endif
802 	INIT_FUNC_WATCHDOG_INIT
803 #if defined(CONFIG_MISC_INIT_F)
804 	misc_init_f,
805 #endif
806 	INIT_FUNC_WATCHDOG_RESET
807 #if defined(CONFIG_SYS_I2C)
808 	init_func_i2c,
809 #endif
810 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
811 	init_func_vid,
812 #endif
813 #if defined(CONFIG_HARD_SPI)
814 	init_func_spi,
815 #endif
816 	announce_dram_init,
817 	dram_init,		/* configure available RAM banks */
818 #ifdef CONFIG_POST
819 	post_init_f,
820 #endif
821 	INIT_FUNC_WATCHDOG_RESET
822 #if defined(CONFIG_SYS_DRAM_TEST)
823 	testdram,
824 #endif /* CONFIG_SYS_DRAM_TEST */
825 	INIT_FUNC_WATCHDOG_RESET
826 
827 #ifdef CONFIG_POST
828 	init_post,
829 #endif
830 	INIT_FUNC_WATCHDOG_RESET
831 	/*
832 	 * Now that we have DRAM mapped and working, we can
833 	 * relocate the code and continue running from DRAM.
834 	 *
835 	 * Reserve memory at end of RAM for (top down in that order):
836 	 *  - area that won't get touched by U-Boot and Linux (optional)
837 	 *  - kernel log buffer
838 	 *  - protected RAM
839 	 *  - LCD framebuffer
840 	 *  - monitor code
841 	 *  - board info struct
842 	 */
843 	setup_dest_addr,
844 #ifdef CONFIG_PRAM
845 	reserve_pram,
846 #endif
847 	reserve_round_4k,
848 #ifdef CONFIG_ARM
849 	reserve_mmu,
850 #endif
851 	reserve_video,
852 	reserve_trace,
853 	reserve_uboot,
854 	reserve_malloc,
855 	reserve_board,
856 	setup_machine,
857 	reserve_global_data,
858 	reserve_fdt,
859 	reserve_bootstage,
860 	reserve_arch,
861 	reserve_stacks,
862 	dram_init_banksize,
863 	show_dram_config,
864 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
865 	defined(CONFIG_SH)
866 	setup_board_part1,
867 #endif
868 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
869 	INIT_FUNC_WATCHDOG_RESET
870 	setup_board_part2,
871 #endif
872 	display_new_sp,
873 #ifdef CONFIG_OF_BOARD_FIXUP
874 	fix_fdt,
875 #endif
876 	INIT_FUNC_WATCHDOG_RESET
877 	reloc_fdt,
878 	reloc_bootstage,
879 	setup_reloc,
880 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
881 	copy_uboot_to_ram,
882 	do_elf_reloc_fixups,
883 	clear_bss,
884 #endif
885 #if defined(CONFIG_XTENSA)
886 	clear_bss,
887 #endif
888 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
889 		!CONFIG_IS_ENABLED(X86_64)
890 	jump_to_copy,
891 #endif
892 	NULL,
893 };
894 
board_init_f(ulong boot_flags)895 void board_init_f(ulong boot_flags)
896 {
897 	gd->flags = boot_flags;
898 	gd->have_console = 0;
899 
900 	if (initcall_run_list(init_sequence_f))
901 		hang();
902 
903 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
904 		!defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
905 		!defined(CONFIG_ARC)
906 	/* NOTREACHED - jump_to_copy() does not return */
907 	hang();
908 #endif
909 }
910 
911 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
912 /*
913  * For now this code is only used on x86.
914  *
915  * init_sequence_f_r is the list of init functions which are run when
916  * U-Boot is executing from Flash with a semi-limited 'C' environment.
917  * The following limitations must be considered when implementing an
918  * '_f_r' function:
919  *  - 'static' variables are read-only
920  *  - Global Data (gd->xxx) is read/write
921  *
922  * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
923  * supported).  It _should_, if possible, copy global data to RAM and
924  * initialise the CPU caches (to speed up the relocation process)
925  *
926  * NOTE: At present only x86 uses this route, but it is intended that
927  * all archs will move to this when generic relocation is implemented.
928  */
929 static const init_fnc_t init_sequence_f_r[] = {
930 #if !CONFIG_IS_ENABLED(X86_64)
931 	init_cache_f_r,
932 #endif
933 
934 	NULL,
935 };
936 
board_init_f_r(void)937 void board_init_f_r(void)
938 {
939 	if (initcall_run_list(init_sequence_f_r))
940 		hang();
941 
942 	/*
943 	 * The pre-relocation drivers may be using memory that has now gone
944 	 * away. Mark serial as unavailable - this will fall back to the debug
945 	 * UART if available.
946 	 *
947 	 * Do the same with log drivers since the memory may not be available.
948 	 */
949 	gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
950 #ifdef CONFIG_TIMER
951 	gd->timer = NULL;
952 #endif
953 
954 	/*
955 	 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
956 	 * Transfer execution from Flash to RAM by calculating the address
957 	 * of the in-RAM copy of board_init_r() and calling it
958 	 */
959 	(board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
960 
961 	/* NOTREACHED - board_init_r() does not return */
962 	hang();
963 }
964 #endif /* CONFIG_X86 */
965