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1 /*
2  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __CORTEX_A75_H__
8 #define __CORTEX_A75_H__
9 
10 /* Cortex-A75 MIDR */
11 #define CORTEX_A75_MIDR		0x410fd0a0
12 
13 /*******************************************************************************
14  * CPU Extended Control register specific definitions.
15  ******************************************************************************/
16 #define CORTEX_A75_CPUPWRCTLR_EL1	S3_0_C15_C2_7
17 #define CORTEX_A75_CPUECTLR_EL1		S3_0_C15_C1_4
18 
19 /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
20 #define CORTEX_A75_CORE_PWRDN_EN_MASK	0x1
21 
22 #endif /* __CORTEX_A75_H__ */
23