1ARM CPU Specific Build Macros 2============================= 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10This document describes the various build options present in the CPU specific 11operations framework to enable errata workarounds and to enable optimizations 12for a specific CPU on a platform. 13 14CPU Errata Workarounds 15---------------------- 16 17ARM Trusted Firmware exports a series of build flags which control the 18errata workarounds that are applied to each CPU by the reset handler. The 19errata details can be found in the CPU specific errata documents published 20by ARM: 21 22- `Cortex-A53 MPCore Software Developers Errata Notice`_ 23- `Cortex-A57 MPCore Software Developers Errata Notice`_ 24- `Cortex-A72 MPCore Software Developers Errata Notice`_ 25 26The errata workarounds are implemented for a particular revision or a set of 27processor revisions. This is checked by the reset handler at runtime. Each 28errata workaround is identified by its ``ID`` as specified in the processor's 29errata notice document. The format of the define used to enable/disable the 30errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 31is for example ``A57`` for the ``Cortex_A57`` CPU. 32 33Refer to the section *CPU errata status reporting* in 34`Firmware Design guide`_ for information on how to write errata workaround 35functions. 36 37All workarounds are disabled by default. The platform is responsible for 38enabling these workarounds according to its requirement by defining the 39errata workaround build flags in the platform specific makefile. In case 40these workarounds are enabled for the wrong CPU revision then the errata 41workaround is not applied. In the DEBUG build, this is indicated by 42printing a warning to the crash console. 43 44In the current implementation, a platform which has more than 1 variant 45with different revisions of a processor has no runtime mechanism available 46for it to specify which errata workarounds should be enabled or not. 47 48The value of the build flags are 0 by default, that is, disabled. Any other 49value will enable it. 50 51For Cortex-A53, following errata build flags are defined : 52 53- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 54 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 55 56- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 57 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 58 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 59 sections. 60 61- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 62 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 63 r0p4 and onwards, this errata is enabled by default in hardware. 64 65- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 66 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 67 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 68 which are 4kB aligned. 69 70- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 71 CPUs. Though the erratum is present in every revision of the CPU, 72 this workaround is only applied to CPUs from r0p3 onwards, which feature 73 a chicken bit in CPUACTLR\_EL1 to enable a hardware workaround. 74 Earlier revisions of the CPU have other errata which require the same 75 workaround in software, so they should be covered anyway. 76 77For Cortex-A57, following errata build flags are defined : 78 79- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 80 CPU. This needs to be enabled only for revision r0p0 of the CPU. 81 82- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 83 CPU. This needs to be enabled only for revision r0p0 of the CPU. 84 85- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 86 CPU. This needs to be enabled only for revision r0p0 of the CPU. 87 88- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 89 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 90 91- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 92 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 93 94- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 95 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 96 97- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 101 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 102 103- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 104 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 105 106 107For Cortex-A72, following errata build flags are defined : 108 109- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 110 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 111 112CPU Specific optimizations 113-------------------------- 114 115This section describes some of the optimizations allowed by the CPU micro 116architecture that can be enabled by the platform as desired. 117 118- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 119 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 120 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 121 of the L2 by set/way flushes any dirty lines from the L1 as well. This 122 is a known safe deviation from the Cortex-A57 TRM defined power down 123 sequence. Each Cortex-A57 based platform must make its own decision on 124 whether to use the optimization. 125 126- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 127 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 128 in a way most programmers expect, and will most probably result in a 129 significant speed degradation to any code that employs them. The ARMv8-A 130 architecture (see ARM DDI 0487A.h, section D3.4.3) allows cores to ignore 131 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 132 flag enforces this behaviour. This needs to be enabled only for revisions 133 <= r0p3 of the CPU and is enabled by default. 134 135- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 136 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 137 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 138 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 139 `Cortex-A57 Software Optimization Guide`_. 140 141-------------- 142 143*Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.* 144 145.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf 146.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf 147.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 148.. _Firmware Design guide: firmware-design.rst 149.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 150