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1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 
25 #ifndef __MSM_DRM_H__
26 #define __MSM_DRM_H__
27 
28 #include "drm.h"
29 
30 #if defined(__cplusplus)
31 extern "C" {
32 #endif
33 
34 /* Please note that modifications to all structs defined here are
35  * subject to backwards-compatibility constraints:
36  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
37  *     user/kernel compatibility
38  *  2) Keep fields aligned to their size
39  *  3) Because of how drm_ioctl() works, we can add new fields at
40  *     the end of an ioctl if some care is taken: drm_ioctl() will
41  *     zero out the new fields at the tail of the ioctl, so a zero
42  *     value should have a backwards compatible meaning.  And for
43  *     output params, userspace won't see the newly added output
44  *     fields.. so that has to be somehow ok.
45  */
46 
47 #define MSM_PIPE_NONE        0x00
48 #define MSM_PIPE_2D0         0x01
49 #define MSM_PIPE_2D1         0x02
50 #define MSM_PIPE_3D0         0x10
51 
52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in
53  * the upper 16 bits (which could be extended further, if needed, maybe
54  * we extend/overload the pipe-id some day to deal with multiple rings,
55  * but even then I don't think we need the full lower 16 bits).
56  */
57 #define MSM_PIPE_ID_MASK     0xffff
58 #define MSM_PIPE_ID(x)       ((x) & MSM_PIPE_ID_MASK)
59 #define MSM_PIPE_FLAGS(x)    ((x) & ~MSM_PIPE_ID_MASK)
60 
61 /* timeouts are specified in clock-monotonic absolute times (to simplify
62  * restarting interrupted ioctls).  The following struct is logically the
63  * same as 'struct timespec' but 32/64b ABI safe.
64  */
65 struct drm_msm_timespec {
66 	__s64 tv_sec;          /* seconds */
67 	__s64 tv_nsec;         /* nanoseconds */
68 };
69 
70 #define MSM_PARAM_GPU_ID     0x01
71 #define MSM_PARAM_GMEM_SIZE  0x02
72 #define MSM_PARAM_CHIP_ID    0x03
73 #define MSM_PARAM_MAX_FREQ   0x04
74 #define MSM_PARAM_TIMESTAMP  0x05
75 #define MSM_PARAM_GMEM_BASE  0x06
76 #define MSM_PARAM_NR_RINGS   0x07
77 
78 struct drm_msm_param {
79 	__u32 pipe;           /* in, MSM_PIPE_x */
80 	__u32 param;          /* in, MSM_PARAM_x */
81 	__u64 value;          /* out (get_param) or in (set_param) */
82 };
83 
84 /*
85  * GEM buffers:
86  */
87 
88 #define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
89 #define MSM_BO_GPU_READONLY  0x00000002
90 #define MSM_BO_CACHE_MASK    0x000f0000
91 /* cache modes */
92 #define MSM_BO_CACHED        0x00010000
93 #define MSM_BO_WC            0x00020000
94 #define MSM_BO_UNCACHED      0x00040000
95 
96 #define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
97                               MSM_BO_GPU_READONLY | \
98                               MSM_BO_CACHED | \
99                               MSM_BO_WC | \
100                               MSM_BO_UNCACHED)
101 
102 struct drm_msm_gem_new {
103 	__u64 size;           /* in */
104 	__u32 flags;          /* in, mask of MSM_BO_x */
105 	__u32 handle;         /* out */
106 };
107 
108 /* Get or set GEM buffer info.  The requested value can be passed
109  * directly in 'value', or for data larger than 64b 'value' is a
110  * pointer to userspace buffer, with 'len' specifying the number of
111  * bytes copied into that buffer.  For info returned by pointer,
112  * calling the GEM_INFO ioctl with null 'value' will return the
113  * required buffer size in 'len'
114  */
115 #define MSM_INFO_GET_OFFSET	0x00   /* get mmap() offset, returned by value */
116 #define MSM_INFO_GET_IOVA	0x01   /* get iova, returned by value */
117 #define MSM_INFO_SET_NAME	0x02   /* set the debug name (by pointer) */
118 #define MSM_INFO_GET_NAME	0x03   /* get debug name, returned by pointer */
119 
120 struct drm_msm_gem_info {
121 	__u32 handle;         /* in */
122 	__u32 info;           /* in - one of MSM_INFO_* */
123 	__u64 value;          /* in or out */
124 	__u32 len;            /* in or out */
125 	__u32 pad;
126 };
127 
128 #define MSM_PREP_READ        0x01
129 #define MSM_PREP_WRITE       0x02
130 #define MSM_PREP_NOSYNC      0x04
131 
132 #define MSM_PREP_FLAGS       (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
133 
134 struct drm_msm_gem_cpu_prep {
135 	__u32 handle;         /* in */
136 	__u32 op;             /* in, mask of MSM_PREP_x */
137 	struct drm_msm_timespec timeout;   /* in */
138 };
139 
140 struct drm_msm_gem_cpu_fini {
141 	__u32 handle;         /* in */
142 };
143 
144 /*
145  * Cmdstream Submission:
146  */
147 
148 /* The value written into the cmdstream is logically:
149  *
150  *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
151  *
152  * When we have GPU's w/ >32bit ptrs, it should be possible to deal
153  * with this by emit'ing two reloc entries with appropriate shift
154  * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
155  *
156  * NOTE that reloc's must be sorted by order of increasing submit_offset,
157  * otherwise EINVAL.
158  */
159 struct drm_msm_gem_submit_reloc {
160 	__u32 submit_offset;  /* in, offset from submit_bo */
161 	__u32 or;             /* in, value OR'd with result */
162 	__s32 shift;          /* in, amount of left shift (can be negative) */
163 	__u32 reloc_idx;      /* in, index of reloc_bo buffer */
164 	__u64 reloc_offset;   /* in, offset from start of reloc_bo */
165 };
166 
167 /* submit-types:
168  *   BUF - this cmd buffer is executed normally.
169  *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
170  *      processed normally, but the kernel does not setup an IB to
171  *      this buffer in the first-level ringbuffer
172  *   CTX_RESTORE_BUF - only executed if there has been a GPU context
173  *      switch since the last SUBMIT ioctl
174  */
175 #define MSM_SUBMIT_CMD_BUF             0x0001
176 #define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
177 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
178 struct drm_msm_gem_submit_cmd {
179 	__u32 type;           /* in, one of MSM_SUBMIT_CMD_x */
180 	__u32 submit_idx;     /* in, index of submit_bo cmdstream buffer */
181 	__u32 submit_offset;  /* in, offset into submit_bo */
182 	__u32 size;           /* in, cmdstream size */
183 	__u32 pad;
184 	__u32 nr_relocs;      /* in, number of submit_reloc's */
185 	__u64 relocs;         /* in, ptr to array of submit_reloc's */
186 };
187 
188 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
189  * cmdstream buffer(s) themselves or reloc entries) has one (and only
190  * one) entry in the submit->bos[] table.
191  *
192  * As a optimization, the current buffer (gpu virtual address) can be
193  * passed back through the 'presumed' field.  If on a subsequent reloc,
194  * userspace passes back a 'presumed' address that is still valid,
195  * then patching the cmdstream for this entry is skipped.  This can
196  * avoid kernel needing to map/access the cmdstream bo in the common
197  * case.
198  */
199 #define MSM_SUBMIT_BO_READ             0x0001
200 #define MSM_SUBMIT_BO_WRITE            0x0002
201 #define MSM_SUBMIT_BO_DUMP             0x0004
202 
203 #define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | \
204 					MSM_SUBMIT_BO_WRITE | \
205 					MSM_SUBMIT_BO_DUMP)
206 
207 struct drm_msm_gem_submit_bo {
208 	__u32 flags;          /* in, mask of MSM_SUBMIT_BO_x */
209 	__u32 handle;         /* in, GEM handle */
210 	__u64 presumed;       /* in/out, presumed buffer address */
211 };
212 
213 /* Valid submit ioctl flags: */
214 #define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
215 #define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
216 #define MSM_SUBMIT_FENCE_FD_OUT  0x20000000 /* enable output fence_fd */
217 #define MSM_SUBMIT_SUDO          0x10000000 /* run submitted cmds from RB */
218 #define MSM_SUBMIT_FLAGS                ( \
219 		MSM_SUBMIT_NO_IMPLICIT   | \
220 		MSM_SUBMIT_FENCE_FD_IN   | \
221 		MSM_SUBMIT_FENCE_FD_OUT  | \
222 		MSM_SUBMIT_SUDO          | \
223 		0)
224 
225 /* Each cmdstream submit consists of a table of buffers involved, and
226  * one or more cmdstream buffers.  This allows for conditional execution
227  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
228  */
229 struct drm_msm_gem_submit {
230 	__u32 flags;          /* MSM_PIPE_x | MSM_SUBMIT_x */
231 	__u32 fence;          /* out */
232 	__u32 nr_bos;         /* in, number of submit_bo's */
233 	__u32 nr_cmds;        /* in, number of submit_cmd's */
234 	__u64 bos;            /* in, ptr to array of submit_bo's */
235 	__u64 cmds;           /* in, ptr to array of submit_cmd's */
236 	__s32 fence_fd;       /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
237 	__u32 queueid;         /* in, submitqueue id */
238 };
239 
240 /* The normal way to synchronize with the GPU is just to CPU_PREP on
241  * a buffer if you need to access it from the CPU (other cmdstream
242  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
243  * handle the required synchronization under the hood).  This ioctl
244  * mainly just exists as a way to implement the gallium pipe_fence
245  * APIs without requiring a dummy bo to synchronize on.
246  */
247 struct drm_msm_wait_fence {
248 	__u32 fence;          /* in */
249 	__u32 pad;
250 	struct drm_msm_timespec timeout;   /* in */
251 	__u32 queueid;         /* in, submitqueue id */
252 };
253 
254 /* madvise provides a way to tell the kernel in case a buffers contents
255  * can be discarded under memory pressure, which is useful for userspace
256  * bo cache where we want to optimistically hold on to buffer allocate
257  * and potential mmap, but allow the pages to be discarded under memory
258  * pressure.
259  *
260  * Typical usage would involve madvise(DONTNEED) when buffer enters BO
261  * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
262  * In the WILLNEED case, 'retained' indicates to userspace whether the
263  * backing pages still exist.
264  */
265 #define MSM_MADV_WILLNEED 0       /* backing pages are needed, status returned in 'retained' */
266 #define MSM_MADV_DONTNEED 1       /* backing pages not needed */
267 #define __MSM_MADV_PURGED 2       /* internal state */
268 
269 struct drm_msm_gem_madvise {
270 	__u32 handle;         /* in, GEM handle */
271 	__u32 madv;           /* in, MSM_MADV_x */
272 	__u32 retained;       /* out, whether backing store still exists */
273 };
274 
275 /*
276  * Draw queues allow the user to set specific submission parameter. Command
277  * submissions specify a specific submitqueue to use.  ID 0 is reserved for
278  * backwards compatibility as a "default" submitqueue
279  */
280 
281 #define MSM_SUBMITQUEUE_FLAGS (0)
282 
283 struct drm_msm_submitqueue {
284 	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
285 	__u32 prio;    /* in, Priority level */
286 	__u32 id;      /* out, identifier */
287 };
288 
289 #define DRM_MSM_GET_PARAM              0x00
290 /* placeholder:
291 #define DRM_MSM_SET_PARAM              0x01
292  */
293 #define DRM_MSM_GEM_NEW                0x02
294 #define DRM_MSM_GEM_INFO               0x03
295 #define DRM_MSM_GEM_CPU_PREP           0x04
296 #define DRM_MSM_GEM_CPU_FINI           0x05
297 #define DRM_MSM_GEM_SUBMIT             0x06
298 #define DRM_MSM_WAIT_FENCE             0x07
299 #define DRM_MSM_GEM_MADVISE            0x08
300 /* placeholder:
301 #define DRM_MSM_GEM_SVM_NEW            0x09
302  */
303 #define DRM_MSM_SUBMITQUEUE_NEW        0x0A
304 #define DRM_MSM_SUBMITQUEUE_CLOSE      0x0B
305 
306 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
307 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
308 #define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
309 #define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
310 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
311 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
312 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
313 #define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
314 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW    DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
315 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
316 
317 #if defined(__cplusplus)
318 }
319 #endif
320 
321 #endif /* __MSM_DRM_H__ */
322