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1 /*
2  * Copyright 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26 
27 #include "drm.h"
28 
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32 
33 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
34 				 ((__u32)(c) << 16) | ((__u32)(d) << 24))
35 
36 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
37 
38 /* color index */
39 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
40 
41 /* 8 bpp Red */
42 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
43 
44 /* 16 bpp Red */
45 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
46 
47 /* 16 bpp RG */
48 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
49 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
50 
51 /* 32 bpp RG */
52 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
53 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
54 
55 /* 8 bpp RGB */
56 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
57 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
58 
59 /* 16 bpp RGB */
60 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
61 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
62 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
63 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
64 
65 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
66 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
67 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
68 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
69 
70 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
71 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
72 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
73 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
74 
75 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
76 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
77 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
78 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
79 
80 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
81 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
82 
83 /* 24 bpp RGB */
84 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
85 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
86 
87 /* 32 bpp RGB */
88 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
89 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
90 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
91 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
92 
93 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
94 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
95 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
96 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
97 
98 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
99 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
100 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
101 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
102 
103 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
104 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
105 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
106 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
107 
108 /* packed YCbCr */
109 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
110 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
111 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
112 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
113 
114 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
115 
116 /*
117  * 2 plane RGB + A
118  * index 0 = RGB plane, same format as the corresponding non _A8 format has
119  * index 1 = A plane, [7:0] A
120  */
121 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
122 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
123 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
124 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
125 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
126 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
127 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
128 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
129 
130 /*
131  * 2 plane YCbCr
132  * index 0 = Y plane, [7:0] Y
133  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
134  * or
135  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
136  */
137 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
138 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
139 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
140 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
141 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
142 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
143 
144 /*
145  * 3 plane YCbCr
146  * index 0: Y plane, [7:0] Y
147  * index 1: Cb plane, [7:0] Cb
148  * index 2: Cr plane, [7:0] Cr
149  * or
150  * index 1: Cr plane, [7:0] Cr
151  * index 2: Cb plane, [7:0] Cb
152  */
153 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
154 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
155 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
156 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
157 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
158 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
159 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
160 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
161 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
162 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
163 
164 
165 /*
166  * Format Modifiers:
167  *
168  * Format modifiers describe, typically, a re-ordering or modification
169  * of the data in a plane of an FB.  This can be used to express tiled/
170  * swizzled formats, or compression, or a combination of the two.
171  *
172  * The upper 8 bits of the format modifier are a vendor-id as assigned
173  * below.  The lower 56 bits are assigned as vendor sees fit.
174  */
175 
176 /* Vendor Ids: */
177 #define DRM_FORMAT_MOD_NONE           0
178 #define DRM_FORMAT_MOD_VENDOR_NONE    0
179 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
180 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
181 #define DRM_FORMAT_MOD_VENDOR_NV      0x03
182 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
183 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
184 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
185 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
186 /* add more to the end as needed */
187 
188 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
189 
190 #define fourcc_mod_code(vendor, val) \
191 	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
192 
193 /*
194  * Format Modifier tokens:
195  *
196  * When adding a new token please document the layout with a code comment,
197  * similar to the fourcc codes above. drm_fourcc.h is considered the
198  * authoritative source for all of these.
199  */
200 
201 /*
202  * Invalid Modifier
203  *
204  * This modifier can be used as a sentinel to terminate the format modifiers
205  * list, or to initialize a variable with an invalid modifier. It might also be
206  * used to report an error back to userspace for certain APIs.
207  */
208 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
209 
210 /*
211  * Linear Layout
212  *
213  * Just plain linear layout. Note that this is different from no specifying any
214  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
215  * which tells the driver to also take driver-internal information into account
216  * and so might actually result in a tiled framebuffer.
217  */
218 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
219 
220 /* Intel framebuffer modifiers */
221 
222 /*
223  * Intel X-tiling layout
224  *
225  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
226  * in row-major layout. Within the tile bytes are laid out row-major, with
227  * a platform-dependent stride. On top of that the memory can apply
228  * platform-depending swizzling of some higher address bits into bit6.
229  *
230  * This format is highly platforms specific and not useful for cross-driver
231  * sharing. It exists since on a given platform it does uniquely identify the
232  * layout in a simple way for i915-specific userspace.
233  */
234 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
235 
236 /*
237  * Intel Y-tiling layout
238  *
239  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
240  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
241  * chunks column-major, with a platform-dependent height. On top of that the
242  * memory can apply platform-depending swizzling of some higher address bits
243  * into bit6.
244  *
245  * This format is highly platforms specific and not useful for cross-driver
246  * sharing. It exists since on a given platform it does uniquely identify the
247  * layout in a simple way for i915-specific userspace.
248  */
249 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
250 
251 /*
252  * Intel Yf-tiling layout
253  *
254  * This is a tiled layout using 4Kb tiles in row-major layout.
255  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
256  * are arranged in four groups (two wide, two high) with column-major layout.
257  * Each group therefore consits out of four 256 byte units, which are also laid
258  * out as 2x2 column-major.
259  * 256 byte units are made out of four 64 byte blocks of pixels, producing
260  * either a square block or a 2:1 unit.
261  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
262  * in pixel depends on the pixel depth.
263  */
264 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
265 
266 /*
267  * Intel color control surface (CCS) for render compression
268  *
269  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
270  * The main surface will be plane index 0 and must be Y/Yf-tiled,
271  * the CCS will be plane index 1.
272  *
273  * Each CCS tile matches a 1024x512 pixel area of the main surface.
274  * To match certain aspects of the 3D hardware the CCS is
275  * considered to be made up of normal 128Bx32 Y tiles, Thus
276  * the CCS pitch must be specified in multiples of 128 bytes.
277  *
278  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
279  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
280  * But that fact is not relevant unless the memory is accessed
281  * directly.
282  */
283 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
284 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
285 
286 /*
287  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
288  *
289  * Macroblocks are laid in a Z-shape, and each pixel data is following the
290  * standard NV12 style.
291  * As for NV12, an image is the result of two frame buffers: one for Y,
292  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
293  * Alignment requirements are (for each buffer):
294  * - multiple of 128 pixels for the width
295  * - multiple of  32 pixels for the height
296  *
297  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
298  */
299 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
300 
301 /* Vivante framebuffer modifiers */
302 
303 /*
304  * Vivante 4x4 tiling layout
305  *
306  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
307  * layout.
308  */
309 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
310 
311 /*
312  * Vivante 64x64 super-tiling layout
313  *
314  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
315  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
316  * major layout.
317  *
318  * For more information: see
319  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
320  */
321 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
322 
323 /*
324  * Vivante 4x4 tiling layout for dual-pipe
325  *
326  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
327  * different base address. Offsets from the base addresses are therefore halved
328  * compared to the non-split tiled layout.
329  */
330 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
331 
332 /*
333  * Vivante 64x64 super-tiling layout for dual-pipe
334  *
335  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
336  * starts at a different base address. Offsets from the base addresses are
337  * therefore halved compared to the non-split super-tiled layout.
338  */
339 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
340 
341 /* NVIDIA Tegra frame buffer modifiers */
342 
343 /*
344  * Some modifiers take parameters, for example the number of vertical GOBs in
345  * a block. Reserve the lower 32 bits for parameters
346  */
347 #define __fourcc_mod_tegra_mode_shift 32
348 #define fourcc_mod_tegra_code(val, params) \
349 	fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
350 #define fourcc_mod_tegra_mod(m) \
351 	(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
352 #define fourcc_mod_tegra_param(m) \
353 	(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
354 
355 /*
356  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
357  *
358  * Pixels are arranged in simple tiles of 16 x 16 bytes.
359  */
360 #define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
361 
362 /*
363  * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
364  *
365  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
366  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
367  *
368  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
369  *
370  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
371  * Valid values are:
372  *
373  * 0 == ONE_GOB
374  * 1 == TWO_GOBS
375  * 2 == FOUR_GOBS
376  * 3 == EIGHT_GOBS
377  * 4 == SIXTEEN_GOBS
378  * 5 == THIRTYTWO_GOBS
379  *
380  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
381  * in full detail.
382  */
383 #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
384 
385 /*
386  * Broadcom VC4 "T" format
387  *
388  * This is the primary layout that the V3D GPU can texture from (it
389  * can't do linear).  The T format has:
390  *
391  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
392  *   pixels at 32 bit depth.
393  *
394  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
395  *   16x16 pixels).
396  *
397  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
398  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
399  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
400  *
401  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
402  *   tiles) or right-to-left (odd rows of 4k tiles).
403  */
404 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
405 
406 #if defined(__cplusplus)
407 }
408 #endif
409 
410 #endif /* DRM_FOURCC_H */
411