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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Machine Specific Values for SMDK5250 board based on EXYNOS5
4  *
5  * Copyright (C) 2012 Samsung Electronics
6  */
7 
8 #ifndef _SMDK5250_SETUP_H
9 #define _SMDK5250_SETUP_H
10 
11 #include <config.h>
12 #include <asm/arch/dmc.h>
13 
14 #define NOT_AVAILABLE		0
15 #define DATA_MASK		0xFFFFF
16 
17 #define ENABLE_BIT		0x1
18 #define DISABLE_BIT		0x0
19 #define CA_SWAP_EN		(1 << 0)
20 
21 /* Set PLL */
22 #define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
23 
24 /* MEMCONTROL register bit fields */
25 #define DMC_MEMCONTROL_CLK_STOP_DISABLE	(0 << 0)
26 #define DMC_MEMCONTROL_DPWRDN_DISABLE	(0 << 1)
27 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE	(0 << 2)
28 #define DMC_MEMCONTROL_TP_DISABLE	(0 << 4)
29 #define DMC_MEMCONTROL_DSREF_DISABLE	(0 << 5)
30 #define DMC_MEMCONTROL_DSREF_ENABLE	(1 << 5)
31 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x)    (x << 6)
32 
33 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3  (7 << 8)
34 #define DMC_MEMCONTROL_MEM_TYPE_DDR3    (6 << 8)
35 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2  (5 << 8)
36 
37 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT  (2 << 12)
38 
39 #define DMC_MEMCONTROL_NUM_CHIP_1       (0 << 16)
40 #define DMC_MEMCONTROL_NUM_CHIP_2       (1 << 16)
41 
42 #define DMC_MEMCONTROL_BL_8             (3 << 20)
43 #define DMC_MEMCONTROL_BL_4             (2 << 20)
44 
45 #define DMC_MEMCONTROL_PZQ_DISABLE      (0 << 24)
46 
47 #define DMC_MEMCONTROL_MRR_BYTE_7_0     (0 << 25)
48 #define DMC_MEMCONTROL_MRR_BYTE_15_8    (1 << 25)
49 #define DMC_MEMCONTROL_MRR_BYTE_23_16   (2 << 25)
50 #define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
51 
52 /* MEMCONFIG0 register bit fields */
53 #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
54 #define DMC_MEMCONFIG_CHIP_MAP_SPLIT		(2 << 12)
55 #define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
56 #define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
57 #define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
58 #define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)
59 
60 #define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
61 #define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
62 #define DMC_MEMBASECONFIG_VAL(x)        (       \
63 	DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
64 	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
65 )
66 
67 /*
68  * As we use channel interleaving, therefore value of the base address
69  * register must be set as half of the bus base address
70  * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
71  * we need to set half 0x10 to the membaseconfigx registers
72  * see exynos5420 UM section 17.17.3.21 for more.
73  */
74 #define DMC_CHIP_BASE_0 0x10
75 #define DMC_CHIP_BASE_1 0x50
76 #define DMC_CHIP_MASK	0x7C0
77 
78 #define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)
79 #define DMC_MEMBASECONFIG1_VAL  DMC_MEMBASECONFIG_VAL(0x80)
80 
81 #define DMC_PRECHCONFIG_VAL             0xFF000000
82 #define DMC_PWRDNCONFIG_VAL             0xFFFF00FF
83 
84 #define DMC_CONCONTROL_RESET_VAL	0x0FFF0000
85 #define DFI_INIT_START		(1 << 28)
86 #define EMPTY			(1 << 8)
87 #define AREF_EN			(1 << 5)
88 
89 #define DFI_INIT_COMPLETE_CHO	(1 << 2)
90 #define DFI_INIT_COMPLETE_CH1	(1 << 3)
91 
92 #define RDLVL_COMPLETE_CHO	(1 << 14)
93 #define RDLVL_COMPLETE_CH1	(1 << 15)
94 
95 #define CLK_STOP_EN	(1 << 0)
96 #define DPWRDN_EN	(1 << 1)
97 #define DSREF_EN	(1 << 5)
98 
99 /* COJCONTROL register bit fields */
100 #define DMC_CONCONTROL_IO_PD_CON_DISABLE	(0 << 3)
101 #define DMC_CONCONTROL_IO_PD_CON_ENABLE		(1 << 3)
102 #define DMC_CONCONTROL_AREF_EN_DISABLE		(0 << 5)
103 #define DMC_CONCONTROL_AREF_EN_ENABLE		(1 << 5)
104 #define DMC_CONCONTROL_EMPTY_DISABLE		(0 << 8)
105 #define DMC_CONCONTROL_EMPTY_ENABLE		(1 << 8)
106 #define DMC_CONCONTROL_RD_FETCH_DISABLE		(0x0 << 12)
107 #define DMC_CONCONTROL_TIMEOUT_LEVEL0		(0xFFF << 16)
108 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE	(0 << 28)
109 
110 #define DMC_CONCONTROL_VAL	0x1FFF2101
111 
112 #define DREX_CONCONTROL_VAL	DMC_CONCONTROL_VAL			\
113 				| DMC_CONCONTROL_AREF_EN_ENABLE		\
114 				| DMC_CONCONTROL_IO_PD_CON_ENABLE
115 
116 #define DMC_CONCONTROL_IO_PD_CON(x)		(x << 6)
117 
118 /* CLK_DIV_CPU1 */
119 #define HPM_RATIO               0x2
120 #define COPY_RATIO              0x0
121 
122 /* CLK_DIV_CPU1 = 0x00000003 */
123 #define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4)		\
124 				| (COPY_RATIO))
125 
126 /* CLK_SRC_CORE0 */
127 #define CLK_SRC_CORE0_VAL       0x00000000
128 
129 /* CLK_SRC_CORE1 */
130 #define CLK_SRC_CORE1_VAL       0x100
131 
132 /* CLK_DIV_CORE0 */
133 #define CLK_DIV_CORE0_VAL       0x00120000
134 
135 /* CLK_DIV_CORE1 */
136 #define CLK_DIV_CORE1_VAL       0x07070700
137 
138 /* CLK_DIV_SYSRGT */
139 #define CLK_DIV_SYSRGT_VAL      0x00000111
140 
141 /* CLK_DIV_ACP */
142 #define CLK_DIV_ACP_VAL         0x12
143 
144 /* CLK_DIV_SYSLFT */
145 #define CLK_DIV_SYSLFT_VAL      0x00000311
146 
147 #define MUX_APLL_SEL_MASK	(1 << 0)
148 #define MUX_MPLL_SEL_MASK	(1 << 8)
149 #define MPLL_SEL_MOUT_MPLLFOUT	(2 << 8)
150 #define MUX_CPLL_SEL_MASK	(1 << 8)
151 #define MUX_EPLL_SEL_MASK	(1 << 12)
152 #define MUX_VPLL_SEL_MASK	(1 << 16)
153 #define MUX_GPLL_SEL_MASK	(1 << 28)
154 #define MUX_BPLL_SEL_MASK	(1 << 0)
155 #define MUX_HPM_SEL_MASK	(1 << 20)
156 #define HPM_SEL_SCLK_MPLL	(1 << 21)
157 #define PLL_LOCKED		(1 << 29)
158 #define APLL_CON0_LOCKED	(1 << 29)
159 #define MPLL_CON0_LOCKED	(1 << 29)
160 #define BPLL_CON0_LOCKED	(1 << 29)
161 #define CPLL_CON0_LOCKED	(1 << 29)
162 #define EPLL_CON0_LOCKED	(1 << 29)
163 #define GPLL_CON0_LOCKED	(1 << 29)
164 #define VPLL_CON0_LOCKED	(1 << 29)
165 #define CLK_REG_DISABLE		0x0
166 #define TOP2_VAL		0x0110000
167 
168 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
169 #define SPI0_ISP_SEL		6
170 #define SPI1_ISP_SEL		6
171 #define SCLK_SRC_ISP_VAL	(SPI1_ISP_SEL << 4) \
172 				| (SPI0_ISP_SEL << 0)
173 
174 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
175 #define SPI0_ISP_RATIO		0xf
176 #define SPI1_ISP_RATIO		0xf
177 #define SCLK_DIV_ISP_VAL	(SPI1_ISP_RATIO << 12) \
178 				| (SPI0_ISP_RATIO << 0)
179 
180 /* CLK_DIV_FSYS2 */
181 #define MMC2_RATIO_MASK		0xf
182 #define MMC2_RATIO_VAL		0x3
183 #define MMC2_RATIO_OFFSET	0
184 
185 #define MMC2_PRE_RATIO_MASK	0xff
186 #define MMC2_PRE_RATIO_VAL	0x9
187 #define MMC2_PRE_RATIO_OFFSET	8
188 
189 #define MMC3_RATIO_MASK		0xf
190 #define MMC3_RATIO_VAL		0x1
191 #define MMC3_RATIO_OFFSET	16
192 
193 #define MMC3_PRE_RATIO_MASK	0xff
194 #define MMC3_PRE_RATIO_VAL	0x0
195 #define MMC3_PRE_RATIO_OFFSET	24
196 
197 /* CLK_SRC_LEX */
198 #define CLK_SRC_LEX_VAL         0x0
199 
200 /* CLK_DIV_LEX */
201 #define CLK_DIV_LEX_VAL         0x10
202 
203 /* CLK_DIV_R0X */
204 #define CLK_DIV_R0X_VAL         0x10
205 
206 /* CLK_DIV_L0X */
207 #define CLK_DIV_R1X_VAL         0x10
208 
209 /* CLK_DIV_ISP2 */
210 #define CLK_DIV_ISP2_VAL        0x1
211 
212 /* CLK_SRC_KFC */
213 #define SRC_KFC_HPM_SEL		(1 << 15)
214 
215 /* CLK_SRC_KFC */
216 #define CLK_SRC_KFC_VAL		0x00008001
217 
218 /* CLK_DIV_KFC */
219 #define CLK_DIV_KFC_VAL		0x03300110
220 
221 /* CLK_DIV2_RATIO */
222 #define CLK_DIV2_RATIO		0x10111150
223 
224 /* CLK_DIV4_RATIO */
225 #define CLK_DIV4_RATIO		0x00000003
226 
227 /* CLK_DIV_G2D */
228 #define CLK_DIV_G2D		0x00000010
229 
230 /*
231  * DIV_DISP1_0
232  * For DP, divisor should be 2
233  */
234 #define CLK_DIV_DISP1_0_FIMD1	(2 << 0)
235 
236 /* CLK_GATE_IP_DISP1 */
237 #define CLK_GATE_DP1_ALLOW	(1 << 4)
238 
239 /* AUDIO CLK SEL */
240 #define AUDIO0_SEL_EPLL		(0x6 << 28)
241 #define AUDIO0_RATIO		0x5
242 #define PCM0_RATIO		0x3
243 #define DIV_MAU_VAL		(PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
244 
245 /* CLK_SRC_CDREX */
246 #define MUX_MCLK_CDR_MSPLL	(1 << 4)
247 #define MUX_BPLL_SEL_FOUTBPLL   (1 << 0)
248 #define BPLL_SEL_MASK   0x7
249 #define FOUTBPLL        2
250 
251 #define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
252 #define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
253 
254 #define PHY_CON0_RESET_VAL	0x17020a40
255 #define P0_CMD_EN		(1 << 14)
256 #define BYTE_RDLVL_EN		(1 << 13)
257 #define CTRL_SHGATE		(1 << 8)
258 
259 #define PHY_CON1_RESET_VAL	0x09210100
260 #define RDLVL_PASS_ADJ_VAL	0x6
261 #define RDLVL_PASS_ADJ_OFFSET	16
262 #define CTRL_GATEDURADJ_MASK	(0xf << 20)
263 #define READ_LEVELLING_DDR3	0x0100
264 
265 #define PHY_CON2_RESET_VAL	0x00010004
266 #define INIT_DESKEW_EN		(1 << 6)
267 #define DLL_DESKEW_EN		(1 << 12)
268 #define RDLVL_GATE_EN		(1 << 24)
269 #define RDLVL_EN		(1 << 25)
270 #define RDLVL_INCR_ADJ		(0x1 << 16)
271 
272 /* DREX_PAUSE */
273 #define DREX_PAUSE_EN	(1 << 0)
274 
275 #define BYPASS_EN	(1 << 22)
276 
277 /* MEMMORY VAL */
278 #define PHY_CON0_VAL	0x17021A00
279 
280 #define PHY_CON12_RESET_VAL	0x10100070
281 #define PHY_CON12_VAL		0x10107F50
282 #define CTRL_START		(1 << 6)
283 #define CTRL_DLL_ON		(1 << 5)
284 #define CTRL_LOCK_COARSE_OFFSET	10
285 #define CTRL_LOCK_COARSE_MASK	(0x7F << CTRL_LOCK_COARSE_OFFSET)
286 #define CTRL_LOCK_COARSE(x)	(((x) & CTRL_LOCK_COARSE_MASK) >> \
287 				 CTRL_LOCK_COARSE_OFFSET)
288 #define CTRL_FORCE_MASK		(0x7F << 8)
289 #define CTRL_FINE_LOCKED	0x7
290 
291 #define CTRL_OFFSETD_RESET_VAL	0x8
292 #define CTRL_OFFSETD_VAL	0x7F
293 
294 #define CTRL_OFFSETR0		0x7F
295 #define CTRL_OFFSETR1		0x7F
296 #define CTRL_OFFSETR2		0x7F
297 #define CTRL_OFFSETR3		0x7F
298 #define PHY_CON4_VAL	(CTRL_OFFSETR0 << 0 | \
299 				CTRL_OFFSETR1 << 8 | \
300 				CTRL_OFFSETR2 << 16 | \
301 				CTRL_OFFSETR3 << 24)
302 #define PHY_CON4_RESET_VAL	0x08080808
303 
304 #define CTRL_OFFSETW0		0x7F
305 #define CTRL_OFFSETW1		0x7F
306 #define CTRL_OFFSETW2		0x7F
307 #define CTRL_OFFSETW3		0x7F
308 #define PHY_CON6_VAL	(CTRL_OFFSETW0 << 0 | \
309 				CTRL_OFFSETW1 << 8 | \
310 				CTRL_OFFSETW2 << 16 | \
311 				CTRL_OFFSETW3 << 24)
312 #define PHY_CON6_RESET_VAL	0x08080808
313 
314 #define PHY_CON14_RESET_VAL	0x001F0000
315 #define CTRL_PULLD_DQS		0xF
316 #define CTRL_PULLD_DQS_OFFSET	0
317 
318 /* ZQ Configurations */
319 #define PHY_CON16_RESET_VAL	0x08000304
320 
321 #define ZQ_CLK_EN		(1 << 27)
322 #define ZQ_CLK_DIV_EN		(1 << 18)
323 #define ZQ_MANUAL_STR		(1 << 1)
324 #define ZQ_DONE			(1 << 0)
325 #define ZQ_MODE_DDS_OFFSET	24
326 
327 #define CTRL_RDLVL_GATE_ENABLE	1
328 #define CTRL_RDLVL_GATE_DISABLE	0
329 #define CTRL_RDLVL_DATA_ENABLE	2
330 
331 /* Direct Command */
332 #define DIRECT_CMD_NOP			0x07000000
333 #define DIRECT_CMD_PALL			0x01000000
334 #define DIRECT_CMD_ZQINIT		0x0a000000
335 #define DIRECT_CMD_CHANNEL_SHIFT	28
336 #define DIRECT_CMD_CHIP_SHIFT		20
337 #define DIRECT_CMD_BANK_SHIFT		16
338 #define DIRECT_CMD_REFA		(5 << 24)
339 #define DIRECT_CMD_MRS1		0x71C00
340 #define DIRECT_CMD_MRS2		0x10BFC
341 #define DIRECT_CMD_MRS3		0x0050C
342 #define DIRECT_CMD_MRS4		0x00868
343 #define DIRECT_CMD_MRS5		0x00C04
344 
345 /* Drive Strength */
346 #define IMPEDANCE_48_OHM	4
347 #define IMPEDANCE_40_OHM	5
348 #define IMPEDANCE_34_OHM	6
349 #define IMPEDANCE_30_OHM	7
350 #define PHY_CON39_VAL_48_OHM	0x09240924
351 #define PHY_CON39_VAL_40_OHM	0x0B6D0B6D
352 #define PHY_CON39_VAL_34_OHM	0x0DB60DB6
353 #define PHY_CON39_VAL_30_OHM	0x0FFF0FFF
354 
355 #define CTRL_BSTLEN_OFFSET	8
356 #define CTRL_RDLAT_OFFSET	0
357 
358 #define CMD_DEFAULT_LPDDR3	0xF
359 #define CMD_DEFUALT_OFFSET	0
360 #define T_WRDATA_EN		0x7
361 #define T_WRDATA_EN_DDR3	0x8
362 #define T_WRDATA_EN_OFFSET	16
363 #define T_WRDATA_EN_MASK	0x1f
364 
365 #define PHY_CON31_VAL	0x0C183060
366 #define PHY_CON32_VAL	0x60C18306
367 #define PHY_CON33_VAL	0x00000030
368 
369 #define PHY_CON31_RESET_VAL	0x0
370 #define PHY_CON32_RESET_VAL	0x0
371 #define PHY_CON33_RESET_VAL	0x0
372 
373 #define SL_DLL_DYN_CON_EN	(1 << 1)
374 #define FP_RESYNC	(1 << 3)
375 #define CTRL_START	(1 << 6)
376 
377 #define DMC_AREF_EN		(1 << 5)
378 #define DMC_CONCONTROL_EMPTY	(1 << 8)
379 #define DFI_INIT_START		(1 << 28)
380 
381 #define DMC_MEMCONTROL_VAL	0x00312700
382 #define CLK_STOP_EN		(1 << 0)
383 #define DPWRDN_EN		(1 << 1)
384 #define DSREF_EN		(1 << 5)
385 
386 #define MEMBASECONFIG_CHIP_MASK_VAL	0x7E0
387 #define MEMBASECONFIG_CHIP_MASK_OFFSET	0
388 #define MEMBASECONFIG0_CHIP_BASE_VAL	0x20
389 #define MEMBASECONFIG1_CHIP_BASE_VAL	0x40
390 #define CHIP_BASE_OFFSET		16
391 
392 #define MEMCONFIG_VAL	0x1323
393 #define PRECHCONFIG_DEFAULT_VAL	0xFF000000
394 #define PWRDNCONFIG_DEFAULT_VAL	0xFFFF00FF
395 
396 #define TIMINGAREF_VAL	0x5d
397 #define TIMINGROW_VAL	0x345A8692
398 #define TIMINGDATA_VAL	0x3630065C
399 #define TIMINGPOWER_VAL	0x50380336
400 #define DFI_INIT_COMPLETE	(1 << 3)
401 
402 #define BRBRSVCONTROL_VAL	0x00000033
403 #define BRBRSVCONFIG_VAL	0x88778877
404 
405 /* Clock Gating Control (CGCONTROL) register */
406 #define MEMIF_CG_EN	(1 << 3) /* Memory interface clock gating */
407 #define SCG_CG_EN	(1 << 2) /* Scheduler clock gating */
408 #define BUSIF_WR_CG_EN	(1 << 1) /* Bus interface write channel clock gating */
409 #define BUSIF_RD_CG_EN	(1 << 0) /* Bus interface read channel clock gating */
410 #define DMC_INTERNAL_CG	(MEMIF_CG_EN | SCG_CG_EN | \
411 				 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
412 
413 /* DMC PHY Control0 register */
414 #define PHY_CONTROL0_RESET_VAL	0x0
415 #define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
416 #define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
417 #define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
418 #define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */
419 
420 /* Driver strength for CK, CKE, CS & CA */
421 #define IMP_OUTPUT_DRV_40_OHM	0x5
422 #define IMP_OUTPUT_DRV_30_OHM	0x7
423 #define DA_3_DS_OFFSET		25
424 #define DA_2_DS_OFFSET		22
425 #define DA_1_DS_OFFSET		19
426 #define DA_0_DS_OFFSET		16
427 #define CA_CK_DRVR_DS_OFFSET	9
428 #define CA_CKE_DRVR_DS_OFFSET	6
429 #define CA_CS_DRVR_DS_OFFSET	3
430 #define CA_ADR_DRVR_DS_OFFSET	0
431 
432 #define PHY_CON42_CTRL_BSTLEN_SHIFT	8
433 #define PHY_CON42_CTRL_RDLAT_SHIFT	0
434 
435 /*
436  * Definitions that differ with SoC's.
437  * Below is the part defining macros for Exynos5250.
438  * Else part introduces macros for Exynos5420.
439  */
440 #ifndef CONFIG_EXYNOS5420
441 
442 /* APLL_CON1 */
443 #define APLL_CON1_VAL	(0x00203800)
444 
445 /* MPLL_CON1 */
446 #define MPLL_CON1_VAL   (0x00203800)
447 
448 /* CPLL_CON1 */
449 #define CPLL_CON1_VAL	(0x00203800)
450 
451 /* DPLL_CON1 */
452 #define DPLL_CON1_VAL	(NOT_AVAILABLE)
453 
454 /* GPLL_CON1 */
455 #define GPLL_CON1_VAL	(0x00203800)
456 
457 /* EPLL_CON1, CON2 */
458 #define EPLL_CON1_VAL	0x00000000
459 #define EPLL_CON2_VAL	0x00000080
460 
461 /* VPLL_CON1, CON2 */
462 #define VPLL_CON1_VAL	0x00000000
463 #define VPLL_CON2_VAL	0x00000080
464 
465 /* RPLL_CON1, CON2 */
466 #define RPLL_CON1_VAL	NOT_AVAILABLE
467 #define RPLL_CON2_VAL	NOT_AVAILABLE
468 
469 /* BPLL_CON1 */
470 #define BPLL_CON1_VAL	0x00203800
471 
472 /* SPLL_CON1 */
473 #define SPLL_CON1_VAL	NOT_AVAILABLE
474 
475 /* IPLL_CON1 */
476 #define IPLL_CON1_VAL	NOT_AVAILABLE
477 
478 /* KPLL_CON1 */
479 #define KPLL_CON1_VAL	NOT_AVAILABLE
480 
481 /* CLK_SRC_ISP */
482 #define CLK_SRC_ISP_VAL		NOT_AVAILABLE
483 #define CLK_DIV_ISP0_VAL	0x31
484 #define CLK_DIV_ISP1_VAL	0x0
485 
486 /* CLK_FSYS */
487 #define CLK_SRC_FSYS0_VAL              0x66666
488 #define CLK_DIV_FSYS0_VAL	       0x0BB00000
489 #define CLK_DIV_FSYS1_VAL	       NOT_AVAILABLE
490 #define CLK_DIV_FSYS2_VAL	       NOT_AVAILABLE
491 
492 /* CLK_SRC_CPU */
493 /* 0 = MOUTAPLL,  1 = SCLKMPLL */
494 #define MUX_HPM_SEL             0
495 #define MUX_CPU_SEL             0
496 #define MUX_APLL_SEL            1
497 
498 #define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
499 				| (MUX_CPU_SEL << 16)  \
500 				| (MUX_APLL_SEL))
501 
502 /* CLK_SRC_CDREX */
503 #define CLK_SRC_CDREX_VAL       0x1
504 
505 /* CLK_DIV_CDREX */
506 #define CLK_DIV_CDREX0_VAL	NOT_AVAILABLE
507 #define CLK_DIV_CDREX1_VAL	NOT_AVAILABLE
508 
509 /* CLK_DIV_CPU0_VAL */
510 #define CLK_DIV_CPU0_VAL	NOT_AVAILABLE
511 
512 #define MCLK_CDREX2_RATIO       0x0
513 #define ACLK_EFCON_RATIO        0x1
514 #define MCLK_DPHY_RATIO		0x1
515 #define MCLK_CDREX_RATIO	0x1
516 #define ACLK_C2C_200_RATIO	0x1
517 #define C2C_CLK_400_RATIO	0x1
518 #define PCLK_CDREX_RATIO	0x1
519 #define ACLK_CDREX_RATIO	0x1
520 
521 #define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 24)        \
522 				| (C2C_CLK_400_RATIO << 6)	\
523 				| (PCLK_CDREX_RATIO << 4)	\
524 				| (ACLK_CDREX_RATIO))
525 
526 /* CLK_SRC_TOP0	*/
527 #define MUX_ACLK_300_GSCL_SEL           0x0
528 #define MUX_ACLK_300_GSCL_MID_SEL       0x0
529 #define MUX_ACLK_400_G3D_MID_SEL        0x0
530 #define MUX_ACLK_333_SEL	        0x0
531 #define MUX_ACLK_300_DISP1_SEL	        0x0
532 #define MUX_ACLK_300_DISP1_MID_SEL      0x0
533 #define MUX_ACLK_200_SEL	        0x0
534 #define MUX_ACLK_166_SEL	        0x0
535 #define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL  << 25)		\
536 				| (MUX_ACLK_300_GSCL_MID_SEL << 24)	\
537 				| (MUX_ACLK_400_G3D_MID_SEL << 20)	\
538 				| (MUX_ACLK_333_SEL << 16)		\
539 				| (MUX_ACLK_300_DISP1_SEL << 15)	\
540 				| (MUX_ACLK_300_DISP1_MID_SEL << 14)	\
541 				| (MUX_ACLK_200_SEL << 12)		\
542 				| (MUX_ACLK_166_SEL << 8))
543 
544 /* CLK_SRC_TOP1	*/
545 #define MUX_ACLK_400_G3D_SEL            0x1
546 #define MUX_ACLK_400_ISP_SEL            0x0
547 #define MUX_ACLK_400_IOP_SEL            0x0
548 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL    0x0
549 #define MUX_ACLK_300_GSCL_MID1_SEL      0x0
550 #define MUX_ACLK_300_DISP1_MID1_SEL     0x0
551 #define CLK_SRC_TOP1_VAL	((MUX_ACLK_400_G3D_SEL << 28)           \
552 				|(MUX_ACLK_400_ISP_SEL << 24)           \
553 				|(MUX_ACLK_400_IOP_SEL << 20)           \
554 				|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16)   \
555 				|(MUX_ACLK_300_GSCL_MID1_SEL << 12)     \
556 				|(MUX_ACLK_300_DISP1_MID1_SEL << 8))
557 
558 /* CLK_SRC_TOP2 */
559 #define MUX_GPLL_SEL                    0x1
560 #define MUX_BPLL_USER_SEL               0x0
561 #define MUX_MPLL_USER_SEL               0x0
562 #define MUX_VPLL_SEL                    0x1
563 #define MUX_EPLL_SEL                    0x1
564 #define MUX_CPLL_SEL                    0x1
565 #define VPLLSRC_SEL                     0x0
566 #define CLK_SRC_TOP2_VAL	((MUX_GPLL_SEL << 28)		\
567 				| (MUX_BPLL_USER_SEL << 24)	\
568 				| (MUX_MPLL_USER_SEL << 20)	\
569 				| (MUX_VPLL_SEL << 16)	        \
570 				| (MUX_EPLL_SEL << 12)	        \
571 				| (MUX_CPLL_SEL << 8)           \
572 				| (VPLLSRC_SEL))
573 /* CLK_SRC_TOP3 */
574 #define MUX_ACLK_333_SUB_SEL            0x1
575 #define MUX_ACLK_400_SUB_SEL            0x1
576 #define MUX_ACLK_266_ISP_SUB_SEL        0x1
577 #define MUX_ACLK_266_GPS_SUB_SEL        0x0
578 #define MUX_ACLK_300_GSCL_SUB_SEL       0x1
579 #define MUX_ACLK_266_GSCL_SUB_SEL       0x1
580 #define MUX_ACLK_300_DISP1_SUB_SEL      0x1
581 #define MUX_ACLK_200_DISP1_SUB_SEL      0x1
582 #define CLK_SRC_TOP3_VAL	((MUX_ACLK_333_SUB_SEL << 24)	        \
583 				| (MUX_ACLK_400_SUB_SEL << 20)	        \
584 				| (MUX_ACLK_266_ISP_SUB_SEL << 16)	\
585 				| (MUX_ACLK_266_GPS_SUB_SEL << 12)      \
586 				| (MUX_ACLK_300_GSCL_SUB_SEL << 10)     \
587 				| (MUX_ACLK_266_GSCL_SUB_SEL << 8)      \
588 				| (MUX_ACLK_300_DISP1_SUB_SEL << 6)     \
589 				| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
590 
591 #define CLK_SRC_TOP4_VAL	NOT_AVAILABLE
592 #define CLK_SRC_TOP5_VAL	NOT_AVAILABLE
593 #define CLK_SRC_TOP6_VAL	NOT_AVAILABLE
594 #define CLK_SRC_TOP7_VAL	NOT_AVAILABLE
595 
596 /* CLK_DIV_TOP0	*/
597 #define ACLK_300_DISP1_RATIO	0x2
598 #define ACLK_400_G3D_RATIO	0x0
599 #define ACLK_333_RATIO		0x0
600 #define ACLK_266_RATIO		0x2
601 #define ACLK_200_RATIO		0x3
602 #define ACLK_166_RATIO		0x1
603 #define ACLK_133_RATIO		0x1
604 #define ACLK_66_RATIO		0x5
605 
606 #define CLK_DIV_TOP0_VAL	((ACLK_300_DISP1_RATIO << 28)	\
607 				| (ACLK_400_G3D_RATIO << 24)	\
608 				| (ACLK_333_RATIO  << 20)	\
609 				| (ACLK_266_RATIO << 16)	\
610 				| (ACLK_200_RATIO << 12)	\
611 				| (ACLK_166_RATIO << 8)		\
612 				| (ACLK_133_RATIO << 4)		\
613 				| (ACLK_66_RATIO))
614 
615 /* CLK_DIV_TOP1	*/
616 #define ACLK_MIPI_HSI_TX_BASE_RATIO     0x3
617 #define ACLK_66_PRE_RATIO               0x1
618 #define ACLK_400_ISP_RATIO              0x1
619 #define ACLK_400_IOP_RATIO              0x1
620 #define ACLK_300_GSCL_RATIO             0x2
621 
622 #define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28)	\
623 				| (ACLK_66_PRE_RATIO << 24)		\
624 				| (ACLK_400_ISP_RATIO  << 20)		\
625 				| (ACLK_400_IOP_RATIO << 16)		\
626 				| (ACLK_300_GSCL_RATIO << 12))
627 
628 #define CLK_DIV_TOP2_VAL	NOT_AVAILABLE
629 
630 /* PLL Lock Value Factor */
631 #define PLL_LOCK_FACTOR		250
632 #define PLL_X_LOCK_FACTOR	3000
633 
634 /* CLK_SRC_PERIC0 */
635 #define PWM_SEL		6
636 #define UART3_SEL	6
637 #define UART2_SEL	6
638 #define UART1_SEL	6
639 #define UART0_SEL	6
640 /* SRC_CLOCK = SCLK_MPLL */
641 #define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24)        \
642 				| (UART3_SEL << 12)     \
643 				| (UART2_SEL << 8)       \
644 				| (UART1_SEL << 4)      \
645 				| (UART0_SEL))
646 
647 /* CLK_SRC_PERIC1 */
648 /* SRC_CLOCK = SCLK_MPLL */
649 #define SPI0_SEL		6
650 #define SPI1_SEL		6
651 #define SPI2_SEL		6
652 #define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 24) \
653 				| (SPI1_SEL << 20) \
654 				| (SPI0_SEL << 16))
655 
656 /* CLK_DIV_PERIL0	*/
657 #define UART5_RATIO	7
658 #define UART4_RATIO	7
659 #define UART3_RATIO	7
660 #define UART2_RATIO	7
661 #define UART1_RATIO	7
662 #define UART0_RATIO	7
663 
664 #define CLK_DIV_PERIC0_VAL	((UART3_RATIO << 12)    \
665 				| (UART2_RATIO << 8)    \
666 				| (UART1_RATIO << 4)    \
667 				| (UART0_RATIO))
668 /* CLK_DIV_PERIC1 */
669 #define SPI1_RATIO		0x7
670 #define SPI0_RATIO		0xf
671 #define SPI1_SUB_RATIO		0x0
672 #define SPI0_SUB_RATIO		0x0
673 #define CLK_DIV_PERIC1_VAL	((SPI1_SUB_RATIO << 24) \
674 				| ((SPI1_RATIO << 16) \
675 				| (SPI0_SUB_RATIO << 8) \
676 				| (SPI0_RATIO << 0)))
677 
678 /* CLK_DIV_PERIC2 */
679 #define SPI2_RATIO		0xf
680 #define SPI2_SUB_RATIO		0x0
681 #define CLK_DIV_PERIC2_VAL	((SPI2_SUB_RATIO << 8) \
682 				| (SPI2_RATIO << 0))
683 
684 /* CLK_DIV_PERIC3 */
685 #define PWM_RATIO		8
686 #define CLK_DIV_PERIC3_VAL	(PWM_RATIO << 0)
687 
688 
689 /* CLK_DIV_PERIC4 */
690 #define CLK_DIV_PERIC4_VAL	NOT_AVAILABLE
691 
692 /* CLK_SRC_DISP1_0 */
693 #define CLK_SRC_DISP1_0_VAL	0x6
694 #define CLK_DIV_DISP1_0_VAL	NOT_AVAILABLE
695 
696 #define APLL_FOUT		(1 << 0)
697 #define KPLL_FOUT		NOT_AVAILABLE
698 
699 #define CLK_DIV_CPERI1_VAL	NOT_AVAILABLE
700 
701 #else
702 
703 #define CPU_CONFIG_STATUS_OFFSET	0x80
704 #define CPU_RST_FLAG_VAL		0xFCBA0D10
705 #define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
706 
707 /* APLL_CON1 */
708 #define APLL_CON1_VAL	(0x0020F300)
709 
710 /* MPLL_CON1 */
711 #define MPLL_CON1_VAL   (0x0020F300)
712 
713 
714 /* CPLL_CON1 */
715 #define CPLL_CON1_VAL	0x0020f300
716 
717 /* DPLL_CON1 */
718 #define DPLL_CON1_VAL	(0x0020F300)
719 
720 /* GPLL_CON1 */
721 #define GPLL_CON1_VAL	(NOT_AVAILABLE)
722 
723 
724 /* EPLL_CON1, CON2 */
725 #define EPLL_CON1_VAL	0x00000000
726 #define EPLL_CON2_VAL	0x00000080
727 
728 /* VPLL_CON1, CON2 */
729 #define VPLL_CON1_VAL	0x0020f300
730 #define VPLL_CON2_VAL	NOT_AVAILABLE
731 
732 /* RPLL_CON1, CON2 */
733 #define RPLL_CON1_VAL	0x00000000
734 #define RPLL_CON2_VAL	0x00000080
735 
736 /* BPLL_CON1 */
737 #define BPLL_CON1_VAL	0x0020f300
738 
739 /* SPLL_CON1 */
740 #define SPLL_CON1_VAL	0x0020f300
741 
742 /* IPLL_CON1 */
743 #define IPLL_CON1_VAL	0x00000080
744 
745 /* KPLL_CON1 */
746 #define KPLL_CON1_VAL	0x200000
747 
748 /* CLK_SRC_ISP */
749 #define CLK_SRC_ISP_VAL		0x33366000
750 #define CLK_DIV_ISP0_VAL	0x13131300
751 #define CLK_DIV_ISP1_VAL	0xbb110202
752 
753 
754 /* CLK_FSYS */
755 #define CLK_SRC_FSYS0_VAL              0x33033300
756 #define CLK_DIV_FSYS0_VAL	       0x0
757 #define CLK_DIV_FSYS1_VAL	       0x04f13c4f
758 #define CLK_DIV_FSYS2_VAL	       0x041d0000
759 
760 /* CLK_SRC_CPU */
761 /* 0 = MOUTAPLL,  1 = SCLKMPLL */
762 #define MUX_HPM_SEL             1
763 #define MUX_CPU_SEL             0
764 #define MUX_APLL_SEL            1
765 
766 #define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
767 				| (MUX_CPU_SEL << 16)  \
768 				| (MUX_APLL_SEL))
769 
770 /* CLK_SRC_CDREX */
771 #define CLK_SRC_CDREX_VAL       0x00000011
772 
773 /* CLK_DIV_CDREX */
774 #define CLK_DIV_CDREX0_VAL	0x30010100
775 #define CLK_DIV_CDREX1_VAL	0x300
776 
777 #define CLK_DIV_CDREX_VAL       0x17010100
778 
779 /* CLK_DIV_CPU0_VAL */
780 #define CLK_DIV_CPU0_VAL	0x01440020
781 
782 /* CLK_SRC_TOP */
783 #define CLK_SRC_TOP0_VAL	0x12221222
784 #define CLK_SRC_TOP1_VAL	0x00100200
785 #define CLK_SRC_TOP2_VAL	0x11101000
786 #define CLK_SRC_TOP3_VAL	0x11111111
787 #define CLK_SRC_TOP4_VAL	0x11110111
788 #define CLK_SRC_TOP5_VAL	0x11111101
789 #define CLK_SRC_TOP6_VAL	0x11110111
790 #define CLK_SRC_TOP7_VAL	0x00022200
791 
792 /* CLK_DIV_TOP */
793 #define CLK_DIV_TOP0_VAL	0x23712311
794 #define CLK_DIV_TOP1_VAL	0x13100B00
795 #define CLK_DIV_TOP2_VAL	0x11101100
796 
797 /* PLL Lock Value Factor */
798 #define PLL_LOCK_FACTOR		200
799 #define PLL_X_LOCK_FACTOR	3000
800 
801 /* CLK_SRC_PERIC0 */
802 #define SPDIF_SEL	1
803 #define PWM_SEL		3
804 #define UART4_SEL	3
805 #define UART3_SEL	3
806 #define UART2_SEL	3
807 #define UART1_SEL	3
808 #define UART0_SEL	3
809 /* SRC_CLOCK = SCLK_RPLL */
810 #define CLK_SRC_PERIC0_VAL	((SPDIF_SEL << 28)	\
811 				| (PWM_SEL << 24)	\
812 				| (UART4_SEL << 20)	\
813 				| (UART3_SEL << 16)	\
814 				| (UART2_SEL << 12)	\
815 				| (UART1_SEL << 8)	\
816 				| (UART0_SEL << 4))
817 
818 /* CLK_SRC_PERIC1 */
819 /* SRC_CLOCK = SCLK_EPLL */
820 #define SPI0_SEL		6
821 #define SPI1_SEL		6
822 #define SPI2_SEL		6
823 #define AUDIO0_SEL		6
824 #define AUDIO1_SEL		6
825 #define AUDIO2_SEL		6
826 #define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 28)	\
827 				| (SPI1_SEL << 24)	\
828 				| (SPI0_SEL << 20)	\
829 				| (AUDIO2_SEL << 16)	\
830 				| (AUDIO2_SEL << 12)	\
831 				| (AUDIO2_SEL << 8))
832 
833 /* CLK_DIV_PERIC0 */
834 #define PWM_RATIO	8
835 #define UART4_RATIO	9
836 #define UART3_RATIO	9
837 #define UART2_RATIO	9
838 #define UART1_RATIO	9
839 #define UART0_RATIO	9
840 
841 #define CLK_DIV_PERIC0_VAL	((PWM_RATIO << 28)	\
842 				| (UART4_RATIO << 24)	\
843 				| (UART3_RATIO << 20)    \
844 				| (UART2_RATIO << 16)    \
845 				| (UART1_RATIO << 12)    \
846 				| (UART0_RATIO << 8))
847 /* CLK_DIV_PERIC1 */
848 #define SPI2_RATIO		0x1
849 #define SPI1_RATIO		0x1
850 #define SPI0_RATIO		0x1
851 #define CLK_DIV_PERIC1_VAL	((SPI2_RATIO << 28)	\
852 				| (SPI1_RATIO << 24)	\
853 				| (SPI0_RATIO << 20))
854 
855 /* CLK_DIV_PERIC2 */
856 #define PCM2_RATIO		0x3
857 #define PCM1_RATIO		0x3
858 #define CLK_DIV_PERIC2_VAL	((PCM2_RATIO << 24) \
859 				| (PCM1_RATIO << 16))
860 
861 /* CLK_DIV_PERIC3 */
862 #define AUDIO2_RATIO		0x5
863 #define AUDIO1_RATIO		0x5
864 #define AUDIO0_RATIO		0x5
865 #define CLK_DIV_PERIC3_VAL	((AUDIO2_RATIO << 28)	\
866 				| (AUDIO1_RATIO << 24)	\
867 				| (AUDIO0_RATIO << 20))
868 
869 /* CLK_DIV_PERIC4 */
870 #define SPI2_PRE_RATIO		0x2
871 #define SPI1_PRE_RATIO		0x2
872 #define SPI0_PRE_RATIO		0x2
873 #define CLK_DIV_PERIC4_VAL	((SPI2_PRE_RATIO << 24)	\
874 				| (SPI1_PRE_RATIO << 16) \
875 				| (SPI0_PRE_RATIO << 8))
876 
877 /* CLK_SRC_DISP1_0 */
878 #define CLK_SRC_DISP1_0_VAL	0x10666600
879 #define CLK_DIV_DISP1_0_VAL	0x01050211
880 
881 #define APLL_FOUT		(1 << 0)
882 #define KPLL_FOUT		(1 << 0)
883 
884 #define CLK_DIV_CPERI1_VAL	0x3f3f0000
885 #endif
886 
887 struct mem_timings;
888 
889 /* Errors that we can encourter in low-level setup */
890 enum {
891 	SETUP_ERR_OK,
892 	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
893 	SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
894 };
895 
896 /*
897  * Memory variant specific initialization code for DDR3
898  *
899  * @param mem          Memory timings for this memory type.
900  * @param reset         Reset DDR PHY during initialization.
901  * @return 0 if ok, SETUP_ERR_... if there is a problem
902  */
903 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
904 
905 /* Memory variant specific initialization code for LPDDR3 */
906 void lpddr3_mem_ctrl_init(void);
907 
908 /*
909  * Configure ZQ I/O interface
910  *
911  * @param mem		Memory timings for this memory type.
912  * @param phy0_con16	Register address for dmc_phy0->phy_con16
913  * @param phy1_con16	Register address for dmc_phy1->phy_con16
914  * @param phy0_con17	Register address for dmc_phy0->phy_con17
915  * @param phy1_con17	Register address for dmc_phy1->phy_con17
916  * @return 0 if ok, -1 on error
917  */
918 int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
919 			uint32_t *phy1_con16, uint32_t *phy0_con17,
920 			uint32_t *phy1_con17);
921 /*
922  * Send NOP and MRS/EMRS Direct commands
923  *
924  * @param mem		Memory timings for this memory type.
925  * @param directcmd	Register address for dmc_phy->directcmd
926  */
927 void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
928 
929 /*
930  * Send PALL Direct commands
931  *
932  * @param mem		Memory timings for this memory type.
933  * @param directcmd	Register address for dmc_phy->directcmd
934  */
935 void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
936 
937 /*
938  * Reset the DLL. This function is common between DDR3 and LPDDR2.
939  * However, the reset value is different. So we are passing a flag
940  * ddr_mode to distinguish between LPDDR2 and DDR3.
941  *
942  * @param phycontrol0	Register address for dmc_phy->phycontrol0
943  * @param ddr_mode	Type of DDR memory
944  */
945 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
946 #endif
947