1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 4 * 5 * Copyright (C) 2015, Freescale Semiconductor 6 * 7 * Mingkai Hu <Mingkai.hu@freescale.com> 8 */ 9 10/include/ "fsl-ls1043a.dtsi" 11 12/ { 13 model = "LS1043A QDS Board"; 14 aliases { 15 spi0 = &qspi; 16 spi1 = &dspi0; 17 }; 18}; 19 20&dspi0 { 21 bus-num = <0>; 22 status = "okay"; 23 24 dflash0: n25q128a { 25 #address-cells = <1>; 26 #size-cells = <1>; 27 compatible = "spi-flash"; 28 spi-max-frequency = <1000000>; /* input clock */ 29 spi-cpol; 30 spi-cpha; 31 reg = <0>; 32 }; 33 34 dflash1: sst25wf040b { 35 #address-cells = <1>; 36 #size-cells = <1>; 37 compatible = "spi-flash"; 38 spi-max-frequency = <3500000>; 39 spi-cpol; 40 spi-cpha; 41 reg = <1>; 42 }; 43 44 dflash2: en25s64 { 45 #address-cells = <1>; 46 #size-cells = <1>; 47 compatible = "spi-flash"; 48 spi-max-frequency = <3500000>; 49 spi-cpol; 50 spi-cpha; 51 reg = <2>; 52 }; 53}; 54 55&qspi { 56 bus-num = <0>; 57 status = "okay"; 58 59 qflash0: s25fl128s@0 { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 compatible = "spi-flash"; 63 spi-max-frequency = <20000000>; 64 reg = <0>; 65 }; 66}; 67 68&i2c0 { 69 status = "okay"; 70 pca9547@77 { 71 compatible = "philips,pca9547"; 72 reg = <0x77>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 i2c@0 { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 reg = <0x0>; 80 81 rtc@68 { 82 compatible = "dallas,ds3232"; 83 reg = <0x68>; 84 /* IRQ10_B */ 85 interrupts = <0 150 0x4>; 86 }; 87 }; 88 89 i2c@2 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 reg = <0x2>; 93 94 ina220@40 { 95 compatible = "ti,ina220"; 96 reg = <0x40>; 97 shunt-resistor = <1000>; 98 }; 99 100 ina220@41 { 101 compatible = "ti,ina220"; 102 reg = <0x41>; 103 shunt-resistor = <1000>; 104 }; 105 }; 106 107 i2c@3 { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 reg = <0x3>; 111 112 eeprom@56 { 113 compatible = "at24,24c512"; 114 reg = <0x56>; 115 }; 116 117 eeprom@57 { 118 compatible = "at24,24c512"; 119 reg = <0x57>; 120 }; 121 122 adt7461a@4c { 123 compatible = "adt7461a"; 124 reg = <0x4c>; 125 }; 126 }; 127 }; 128}; 129 130&ifc { 131 #address-cells = <2>; 132 #size-cells = <1>; 133 /* NOR, NAND Flashes and FPGA on board */ 134 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 135 0x1 0x0 0x0 0x7e800000 0x00010000 136 0x2 0x0 0x0 0x7fb00000 0x00000100>; 137 status = "okay"; 138 139 nor@0,0 { 140 #address-cells = <1>; 141 #size-cells = <1>; 142 compatible = "cfi-flash"; 143 reg = <0x0 0x0 0x8000000>; 144 bank-width = <2>; 145 device-width = <1>; 146 }; 147 148 nand@1,0 { 149 compatible = "fsl,ifc-nand"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 reg = <0x1 0x0 0x10000>; 153 }; 154 155 fpga: board-control@2,0 { 156 #address-cells = <1>; 157 #size-cells = <1>; 158 compatible = "simple-bus"; 159 reg = <0x2 0x0 0x0000100>; 160 bank-width = <1>; 161 device-width = <1>; 162 ranges = <0 2 0 0x100>; 163 }; 164}; 165 166&duart0 { 167 status = "okay"; 168}; 169 170&duart1 { 171 status = "okay"; 172}; 173 174&lpuart0 { 175 status = "okay"; 176}; 177