• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014 Gateworks Corporation
4  * Author: Tim Harvey <tharvey@gateworks.com>
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/crm_regs.h>
10 #include <asm/arch/mx6-ddr.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/mxc_i2c.h>
16 #include <environment.h>
17 #include <i2c.h>
18 #include <spl.h>
19 
20 #include "gsc.h"
21 #include "common.h"
22 
23 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
24 #define GSC_EEPROM_DDR_SIZE	0x2B	/* enum (512,1024,2048) MB */
25 #define GSC_EEPROM_DDR_WIDTH	0x2D	/* enum (32,64) bit */
26 
27 /* configure MX6Q/DUAL mmdc DDR io registers */
28 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
29 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
30 	.dram_sdclk_0 = 0x00020030,
31 	.dram_sdclk_1 = 0x00020030,
32 	.dram_cas = 0x00020030,
33 	.dram_ras = 0x00020030,
34 	.dram_reset = 0x00020030,
35 	/* SDCKE[0:1]: 100k pull-up */
36 	.dram_sdcke0 = 0x00003000,
37 	.dram_sdcke1 = 0x00003000,
38 	/* SDBA2: pull-up disabled */
39 	.dram_sdba2 = 0x00000000,
40 	/* SDODT[0:1]: 100k pull-up, 40 ohm */
41 	.dram_sdodt0 = 0x00003030,
42 	.dram_sdodt1 = 0x00003030,
43 	/* SDQS[0:7]: Differential input, 40 ohm */
44 	.dram_sdqs0 = 0x00000030,
45 	.dram_sdqs1 = 0x00000030,
46 	.dram_sdqs2 = 0x00000030,
47 	.dram_sdqs3 = 0x00000030,
48 	.dram_sdqs4 = 0x00000030,
49 	.dram_sdqs5 = 0x00000030,
50 	.dram_sdqs6 = 0x00000030,
51 	.dram_sdqs7 = 0x00000030,
52 
53 	/* DQM[0:7]: Differential input, 40 ohm */
54 	.dram_dqm0 = 0x00020030,
55 	.dram_dqm1 = 0x00020030,
56 	.dram_dqm2 = 0x00020030,
57 	.dram_dqm3 = 0x00020030,
58 	.dram_dqm4 = 0x00020030,
59 	.dram_dqm5 = 0x00020030,
60 	.dram_dqm6 = 0x00020030,
61 	.dram_dqm7 = 0x00020030,
62 };
63 
64 /* configure MX6Q/DUAL mmdc GRP io registers */
65 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
66 	/* DDR3 */
67 	.grp_ddr_type = 0x000c0000,
68 	.grp_ddrmode_ctl = 0x00020000,
69 	/* disable DDR pullups */
70 	.grp_ddrpke = 0x00000000,
71 	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
72 	.grp_addds = 0x00000030,
73 	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
74 	.grp_ctlds = 0x00000030,
75 	/* DATA[00:63]: Differential input, 40 ohm */
76 	.grp_ddrmode = 0x00020000,
77 	.grp_b0ds = 0x00000030,
78 	.grp_b1ds = 0x00000030,
79 	.grp_b2ds = 0x00000030,
80 	.grp_b3ds = 0x00000030,
81 	.grp_b4ds = 0x00000030,
82 	.grp_b5ds = 0x00000030,
83 	.grp_b6ds = 0x00000030,
84 	.grp_b7ds = 0x00000030,
85 };
86 
87 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
88 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
89 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
90 	.dram_sdclk_0 = 0x00020030,
91 	.dram_sdclk_1 = 0x00020030,
92 	.dram_cas = 0x00020030,
93 	.dram_ras = 0x00020030,
94 	.dram_reset = 0x00020030,
95 	/* SDCKE[0:1]: 100k pull-up */
96 	.dram_sdcke0 = 0x00003000,
97 	.dram_sdcke1 = 0x00003000,
98 	/* SDBA2: pull-up disabled */
99 	.dram_sdba2 = 0x00000000,
100 	/* SDODT[0:1]: 100k pull-up, 40 ohm */
101 	.dram_sdodt0 = 0x00003030,
102 	.dram_sdodt1 = 0x00003030,
103 	/* SDQS[0:7]: Differential input, 40 ohm */
104 	.dram_sdqs0 = 0x00000030,
105 	.dram_sdqs1 = 0x00000030,
106 	.dram_sdqs2 = 0x00000030,
107 	.dram_sdqs3 = 0x00000030,
108 	.dram_sdqs4 = 0x00000030,
109 	.dram_sdqs5 = 0x00000030,
110 	.dram_sdqs6 = 0x00000030,
111 	.dram_sdqs7 = 0x00000030,
112 
113 	/* DQM[0:7]: Differential input, 40 ohm */
114 	.dram_dqm0 = 0x00020030,
115 	.dram_dqm1 = 0x00020030,
116 	.dram_dqm2 = 0x00020030,
117 	.dram_dqm3 = 0x00020030,
118 	.dram_dqm4 = 0x00020030,
119 	.dram_dqm5 = 0x00020030,
120 	.dram_dqm6 = 0x00020030,
121 	.dram_dqm7 = 0x00020030,
122 };
123 
124 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
125 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
126 	/* DDR3 */
127 	.grp_ddr_type = 0x000c0000,
128 	/* SDQS[0:7]: Differential input, 40 ohm */
129 	.grp_ddrmode_ctl = 0x00020000,
130 	/* disable DDR pullups */
131 	.grp_ddrpke = 0x00000000,
132 	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
133 	.grp_addds = 0x00000030,
134 	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
135 	.grp_ctlds = 0x00000030,
136 	/* DATA[00:63]: Differential input, 40 ohm */
137 	.grp_ddrmode = 0x00020000,
138 	.grp_b0ds = 0x00000030,
139 	.grp_b1ds = 0x00000030,
140 	.grp_b2ds = 0x00000030,
141 	.grp_b3ds = 0x00000030,
142 	.grp_b4ds = 0x00000030,
143 	.grp_b5ds = 0x00000030,
144 	.grp_b6ds = 0x00000030,
145 	.grp_b7ds = 0x00000030,
146 };
147 
148 /* MT41K64M16JT-125 (1Gb density) */
149 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
150 	.mem_speed = 1600,
151 	.density = 1,
152 	.width = 16,
153 	.banks = 8,
154 	.rowaddr = 13,
155 	.coladdr = 10,
156 	.pagesz = 2,
157 	.trcd = 1375,
158 	.trcmin = 4875,
159 	.trasmin = 3500,
160 };
161 
162 /* MT41K128M16JT-125 (2Gb density) */
163 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
164 	.mem_speed = 1600,
165 	.density = 2,
166 	.width = 16,
167 	.banks = 8,
168 	.rowaddr = 14,
169 	.coladdr = 10,
170 	.pagesz = 2,
171 	.trcd = 1375,
172 	.trcmin = 4875,
173 	.trasmin = 3500,
174 };
175 
176 /* MT41K256M16HA-125 (4Gb density) */
177 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
178 	.mem_speed = 1600,
179 	.density = 4,
180 	.width = 16,
181 	.banks = 8,
182 	.rowaddr = 15,
183 	.coladdr = 10,
184 	.pagesz = 2,
185 	.trcd = 1375,
186 	.trcmin = 4875,
187 	.trasmin = 3500,
188 };
189 
190 /* MT41K512M16HA-125 (8Gb density) */
191 static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
192 	.mem_speed = 1600,
193 	.density = 8,
194 	.width = 16,
195 	.banks = 8,
196 	.rowaddr = 16,
197 	.coladdr = 10,
198 	.pagesz = 2,
199 	.trcd = 1375,
200 	.trcmin = 4875,
201 	.trasmin = 3500,
202 };
203 
204 /*
205  * calibration - these are the various CPU/DDR3 combinations we support
206  */
207 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
208 	/* write leveling calibration determine */
209 	.p0_mpwldectrl0 = 0x004C004E,
210 	.p0_mpwldectrl1 = 0x00440044,
211 	/* Read DQS Gating calibration */
212 	.p0_mpdgctrl0 = 0x42440247,
213 	.p0_mpdgctrl1 = 0x02310232,
214 	/* Read Calibration: DQS delay relative to DQ read access */
215 	.p0_mprddlctl = 0x45424746,
216 	/* Write Calibration: DQ/DM delay relative to DQS write access */
217 	.p0_mpwrdlctl = 0x33382C31,
218 };
219 
220 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
221 	/* write leveling calibration determine */
222 	.p0_mpwldectrl0 = 0x001B0016,
223 	.p0_mpwldectrl1 = 0x000C000E,
224 	/* Read DQS Gating calibration */
225 	.p0_mpdgctrl0 = 0x4324033A,
226 	.p0_mpdgctrl1 = 0x00000000,
227 	/* Read Calibration: DQS delay relative to DQ read access */
228 	.p0_mprddlctl = 0x40403438,
229 	/* Write Calibration: DQ/DM delay relative to DQS write access */
230 	.p0_mpwrdlctl = 0x40403D36,
231 };
232 
233 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
234 	/* write leveling calibration determine */
235 	.p0_mpwldectrl0 = 0x00420043,
236 	.p0_mpwldectrl1 = 0x0016001A,
237 	/* Read DQS Gating calibration */
238 	.p0_mpdgctrl0 = 0x4238023B,
239 	.p0_mpdgctrl1 = 0x00000000,
240 	/* Read Calibration: DQS delay relative to DQ read access */
241 	.p0_mprddlctl = 0x40404849,
242 	/* Write Calibration: DQ/DM delay relative to DQS write access */
243 	.p0_mpwrdlctl = 0x40402E2F,
244 };
245 
246 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
247 	/* write leveling calibration determine */
248 	.p0_mpwldectrl0 = 0x00190017,
249 	.p0_mpwldectrl1 = 0x00140026,
250 	/* Read DQS Gating calibration */
251 	.p0_mpdgctrl0 = 0x43380347,
252 	.p0_mpdgctrl1 = 0x433C034D,
253 	/* Read Calibration: DQS delay relative to DQ read access */
254 	.p0_mprddlctl = 0x3C313539,
255 	/* Write Calibration: DQ/DM delay relative to DQS write access */
256 	.p0_mpwrdlctl = 0x36393C39,
257 };
258 
259 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
260 	/* write leveling calibration determine */
261 	.p0_mpwldectrl0 = 0x003C003C,
262 	.p0_mpwldectrl1 = 0x001F002A,
263 	/* Read DQS Gating calibration */
264 	.p0_mpdgctrl0 = 0x42410244,
265 	.p0_mpdgctrl1 = 0x4234023A,
266 	/* Read Calibration: DQS delay relative to DQ read access */
267 	.p0_mprddlctl = 0x484A4C4B,
268 	/* Write Calibration: DQ/DM delay relative to DQS write access */
269 	.p0_mpwrdlctl = 0x33342B32,
270 };
271 
272 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
273 	/* write leveling calibration determine */
274 	.p0_mpwldectrl0 = 0x00190017,
275 	.p0_mpwldectrl1 = 0x00140026,
276 	.p1_mpwldectrl0 = 0x0021001C,
277 	.p1_mpwldectrl1 = 0x0011001D,
278 	/* Read DQS Gating calibration */
279 	.p0_mpdgctrl0 = 0x43380347,
280 	.p0_mpdgctrl1 = 0x433C034D,
281 	.p1_mpdgctrl0 = 0x032C0324,
282 	.p1_mpdgctrl1 = 0x03310232,
283 	/* Read Calibration: DQS delay relative to DQ read access */
284 	.p0_mprddlctl = 0x3C313539,
285 	.p1_mprddlctl = 0x37343141,
286 	/* Write Calibration: DQ/DM delay relative to DQS write access */
287 	.p0_mpwrdlctl = 0x36393C39,
288 	.p1_mpwrdlctl = 0x42344438,
289 };
290 
291 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
292 	/* write leveling calibration determine */
293 	.p0_mpwldectrl0 = 0x003C003C,
294 	.p0_mpwldectrl1 = 0x001F002A,
295 	.p1_mpwldectrl0 = 0x00330038,
296 	.p1_mpwldectrl1 = 0x0022003F,
297 	/* Read DQS Gating calibration */
298 	.p0_mpdgctrl0 = 0x42410244,
299 	.p0_mpdgctrl1 = 0x4234023A,
300 	.p1_mpdgctrl0 = 0x022D022D,
301 	.p1_mpdgctrl1 = 0x021C0228,
302 	/* Read Calibration: DQS delay relative to DQ read access */
303 	.p0_mprddlctl = 0x484A4C4B,
304 	.p1_mprddlctl = 0x4B4D4E4B,
305 	/* Write Calibration: DQ/DM delay relative to DQS write access */
306 	.p0_mpwrdlctl = 0x33342B32,
307 	.p1_mpwrdlctl = 0x3933332B,
308 };
309 
310 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
311 	/* write leveling calibration determine */
312 	.p0_mpwldectrl0 = 0x001E001A,
313 	.p0_mpwldectrl1 = 0x0026001F,
314 	/* Read DQS Gating calibration */
315 	.p0_mpdgctrl0 = 0x43370349,
316 	.p0_mpdgctrl1 = 0x032D0327,
317 	/* Read Calibration: DQS delay relative to DQ read access */
318 	.p0_mprddlctl = 0x3D303639,
319 	/* Write Calibration: DQ/DM delay relative to DQS write access */
320 	.p0_mpwrdlctl = 0x32363934,
321 };
322 
323 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
324 	/* write leveling calibration determine */
325 	.p0_mpwldectrl0 = 0X00480047,
326 	.p0_mpwldectrl1 = 0X003D003F,
327 	/* Read DQS Gating calibration */
328 	.p0_mpdgctrl0 = 0X423E0241,
329 	.p0_mpdgctrl1 = 0X022B022C,
330 	/* Read Calibration: DQS delay relative to DQ read access */
331 	.p0_mprddlctl = 0X49454A4A,
332 	/* Write Calibration: DQ/DM delay relative to DQS write access */
333 	.p0_mpwrdlctl = 0X2E372C32,
334 };
335 
336 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
337 	/* write leveling calibration determine */
338 	.p0_mpwldectrl0 = 0X00220021,
339 	.p0_mpwldectrl1 = 0X00200030,
340 	.p1_mpwldectrl0 = 0X002D0027,
341 	.p1_mpwldectrl1 = 0X00150026,
342 	/* Read DQS Gating calibration */
343 	.p0_mpdgctrl0 = 0x43330342,
344 	.p0_mpdgctrl1 = 0x0339034A,
345 	.p1_mpdgctrl0 = 0x032F0325,
346 	.p1_mpdgctrl1 = 0x032F022E,
347 	/* Read Calibration: DQS delay relative to DQ read access */
348 	.p0_mprddlctl = 0X3A2E3437,
349 	.p1_mprddlctl = 0X35312F3F,
350 	/* Write Calibration: DQ/DM delay relative to DQS write access */
351 	.p0_mpwrdlctl = 0X33363B37,
352 	.p1_mpwrdlctl = 0X40304239,
353 };
354 
355 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
356 	/* write leveling calibration determine */
357 	.p0_mpwldectrl0 = 0x0048004A,
358 	.p0_mpwldectrl1 = 0x003F004A,
359 	.p1_mpwldectrl0 = 0x001E0028,
360 	.p1_mpwldectrl1 = 0x002C0043,
361 	/* Read DQS Gating calibration */
362 	.p0_mpdgctrl0 = 0x02250219,
363 	.p0_mpdgctrl1 = 0x01790202,
364 	.p1_mpdgctrl0 = 0x02080208,
365 	.p1_mpdgctrl1 = 0x016C0175,
366 	/* Read Calibration: DQS delay relative to DQ read access */
367 	.p0_mprddlctl = 0x4A4C4D4C,
368 	.p1_mprddlctl = 0x494C4A48,
369 	/* Write Calibration: DQ/DM delay relative to DQS write access */
370 	.p0_mpwrdlctl = 0x403F3437,
371 	.p1_mpwrdlctl = 0x383A3930,
372 };
373 
374 static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
375 	/* write leveling calibration determine */
376 	.p0_mpwldectrl0 = 0x001F003F,
377 	.p0_mpwldectrl1 = 0x001F001F,
378 	.p1_mpwldectrl0 = 0x001F004E,
379 	.p1_mpwldectrl1 = 0x0059001F,
380 	/* Read DQS Gating calibration */
381 	.p0_mpdgctrl0   = 0x42220225,
382 	.p0_mpdgctrl1   = 0x0213021F,
383 	.p1_mpdgctrl0   = 0x022C0242,
384 	.p1_mpdgctrl1   = 0x022C0244,
385 	/* Read Calibration: DQS delay relative to DQ read access */
386 	.p0_mprddlctl   = 0x474A4C4A,
387 	.p1_mprddlctl   = 0x48494C45,
388 	/* Write Calibration: DQ/DM delay relative to DQS write access */
389 	.p0_mpwrdlctl   = 0x3F3F3F36,
390 	.p1_mpwrdlctl   = 0x3F36363F,
391 };
392 
393 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
394 	/* write leveling calibration determine */
395 	.p0_mpwldectrl0 = 0x002A0025,
396 	.p0_mpwldectrl1 = 0x003A002A,
397 	/* Read DQS Gating calibration */
398 	.p0_mpdgctrl0 = 0x43430356,
399 	.p0_mpdgctrl1 = 0x033C0335,
400 	/* Read Calibration: DQS delay relative to DQ read access */
401 	.p0_mprddlctl = 0x4B373F42,
402 	/* Write Calibration: DQ/DM delay relative to DQS write access */
403 	.p0_mpwrdlctl = 0x303E3C36,
404 };
405 
406 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
407 	/* write leveling calibration determine */
408 	.p0_mpwldectrl0 = 0x00230020,
409 	.p0_mpwldectrl1 = 0x002F002A,
410 	.p1_mpwldectrl0 = 0x001D0027,
411 	.p1_mpwldectrl1 = 0x00100023,
412 	/* Read DQS Gating calibration */
413 	.p0_mpdgctrl0 = 0x03250339,
414 	.p0_mpdgctrl1 = 0x031C0316,
415 	.p1_mpdgctrl0 = 0x03210331,
416 	.p1_mpdgctrl1 = 0x031C025A,
417 	/* Read Calibration: DQS delay relative to DQ read access */
418 	.p0_mprddlctl = 0x40373C40,
419 	.p1_mprddlctl = 0x3A373646,
420 	/* Write Calibration: DQ/DM delay relative to DQS write access */
421 	.p0_mpwrdlctl = 0x2E353933,
422 	.p1_mpwrdlctl = 0x3C2F3F35,
423 };
424 
spl_dram_init(int width,int size_mb,int board_model)425 static void spl_dram_init(int width, int size_mb, int board_model)
426 {
427 	struct mx6_ddr3_cfg *mem = NULL;
428 	struct mx6_mmdc_calibration *calib = NULL;
429 	struct mx6_ddr_sysinfo sysinfo = {
430 		/* width of data bus:0=16,1=32,2=64 */
431 		.dsize = width/32,
432 		/* config for full 4GB range so that get_mem_size() works */
433 		.cs_density = 32, /* 32Gb per CS */
434 		/* single chip select */
435 		.ncs = 1,
436 		.cs1_mirror = 0,
437 		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
438 #ifdef RTT_NOM_120OHM
439 		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
440 #else
441 		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
442 #endif
443 		.walat = 1,	/* Write additional latency */
444 		.ralat = 5,	/* Read additional latency */
445 		.mif3_mode = 3,	/* Command prediction working mode */
446 		.bi_on = 1,	/* Bank interleaving enabled */
447 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
448 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
449 		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
450 		.ddr_type = DDR_TYPE_DDR3,
451 		.refsel = 1,	/* Refresh cycles at 32KHz */
452 		.refr = 7,	/* 8 refresh commands per refresh cycle */
453 	};
454 
455 	/*
456 	 * MMDC Calibration requires the following data:
457 	 *   mx6_mmdc_calibration - board-specific calibration (routing delays)
458 	 *      these calibration values depend on board routing, SoC, and DDR
459 	 *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
460 	 *   mx6_ddr_cfg - chip specific timing/layout details
461 	 */
462 	if (width == 16 && size_mb == 128) {
463 		mem = &mt41k64m16jt_125;
464 		if (is_cpu_type(MXC_CPU_MX6Q))
465 			;
466 		else
467 			calib = &mx6sdl_64x16_mmdc_calib;
468 		debug("1gB density\n");
469 	} else if (width == 16 && size_mb == 256) {
470 		/* 1x 2Gb density chip - same calib as 2x 2Gb */
471 		mem = &mt41k128m16jt_125;
472 		if (is_cpu_type(MXC_CPU_MX6Q))
473 			calib = &mx6dq_128x32_mmdc_calib;
474 		else
475 			calib = &mx6sdl_128x32_mmdc_calib;
476 		debug("2gB density\n");
477 	} else if (width == 16 && size_mb == 512) {
478 		mem = &mt41k256m16ha_125;
479 		if (is_cpu_type(MXC_CPU_MX6Q))
480 			calib = &mx6dq_256x16_mmdc_calib;
481 		else
482 			calib = &mx6sdl_256x16_mmdc_calib;
483 		debug("4gB density\n");
484 	} else if (width == 32 && size_mb == 256) {
485 		/* Same calib as width==16, size==128 */
486 		mem = &mt41k64m16jt_125;
487 		if (is_cpu_type(MXC_CPU_MX6Q))
488 			;
489 		else
490 			calib = &mx6sdl_64x16_mmdc_calib;
491 		debug("1gB density\n");
492 	} else if (width == 32 && size_mb == 512) {
493 		mem = &mt41k128m16jt_125;
494 		if (is_cpu_type(MXC_CPU_MX6Q))
495 			calib = &mx6dq_128x32_mmdc_calib;
496 		else
497 			calib = &mx6sdl_128x32_mmdc_calib;
498 		debug("2gB density\n");
499 	}  else if (width == 32 && size_mb == 1024) {
500 		mem = &mt41k256m16ha_125;
501 		if (is_cpu_type(MXC_CPU_MX6Q))
502 			calib = &mx6dq_256x32_mmdc_calib;
503 		else
504 			calib = &mx6sdl_256x32_mmdc_calib;
505 		debug("4gB density\n");
506 	} else if (width == 32 && size_mb == 2048) {
507 		mem = &mt41k512m16ha_125;
508 		if (is_cpu_type(MXC_CPU_MX6Q))
509 			calib = &mx6dq_512x32_mmdc_calib;
510 		debug("8gB density\n");
511 	} else if (width == 64 && size_mb == 512) {
512 		mem = &mt41k64m16jt_125;
513 		debug("1gB density\n");
514 	} else if (width == 64 && size_mb == 1024) {
515 		mem = &mt41k128m16jt_125;
516 		if (is_cpu_type(MXC_CPU_MX6Q))
517 			calib = &mx6dq_128x64_mmdc_calib;
518 		else
519 			calib = &mx6sdl_128x64_mmdc_calib;
520 		debug("2gB density\n");
521 	} else if (width == 64 && size_mb == 2048) {
522 		mem = &mt41k256m16ha_125;
523 		if (is_cpu_type(MXC_CPU_MX6Q))
524 			calib = &mx6dq_256x64_mmdc_calib;
525 		else
526 			calib = &mx6sdl_256x64_mmdc_calib;
527 		debug("4gB density\n");
528 	} else if (width == 64 && size_mb == 4096) {
529 		switch(board_model) {
530 		case GW5903:
531 			/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
532 			mem = &mt41k256m16ha_125;
533 			debug("4gB density\n");
534 			if (!is_cpu_type(MXC_CPU_MX6Q)) {
535 				calib = &mx6sdl_256x64x2_mmdc_calib;
536 				sysinfo.ncs = 2;
537 				sysinfo.cs_density = 18; /* CS0_END=71 */
538 				sysinfo.cs1_mirror = 1; /* mirror enabled */
539 			}
540 			break;
541 		default:
542 			mem = &mt41k512m16ha_125;
543 			if (is_cpu_type(MXC_CPU_MX6Q))
544 				calib = &mx6dq_512x64_mmdc_calib;
545 			debug("8gB density\n");
546 			break;
547 		}
548 	}
549 
550 	if (!(mem && calib)) {
551 		puts("Error: Invalid Calibration/Board Configuration\n");
552 		printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
553 		printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
554 		printf("CPUTYPE: %s\n",
555 		       is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
556 		printf("SIZE_MB: %d\n", size_mb);
557 		printf("WIDTH  : %d\n", width);
558 		hang();
559 	}
560 
561 	if (is_cpu_type(MXC_CPU_MX6Q))
562 		mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
563 				 &mx6dq_grp_ioregs);
564 	else
565 		mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
566 				  &mx6sdl_grp_ioregs);
567 	mx6_dram_cfg(&sysinfo, calib, mem);
568 }
569 
ccgr_init(void)570 static void ccgr_init(void)
571 {
572 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
573 
574 	writel(0x00C03F3F, &ccm->CCGR0);
575 	writel(0x0030FC03, &ccm->CCGR1);
576 	writel(0x0FFFC000, &ccm->CCGR2);
577 	writel(0x3FF00000, &ccm->CCGR3);
578 	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
579 	writel(0x0F0000C3, &ccm->CCGR5);
580 	writel(0x000003FF, &ccm->CCGR6);
581 }
582 
583 /*
584  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
585  * - we have a stack and a place to store GD, both in SRAM
586  * - no variable global data is available
587  */
board_init_f(ulong dummy)588 void board_init_f(ulong dummy)
589 {
590 	struct ventana_board_info ventana_info;
591 	int board_model;
592 
593 	/* setup clock gating */
594 	ccgr_init();
595 
596 	/* setup AIPS and disable watchdog */
597 	arch_cpu_init();
598 
599 	/* setup AXI */
600 	gpr_init();
601 
602 	/* iomux and setup of i2c */
603 	setup_iomux_uart();
604 	setup_ventana_i2c();
605 
606 	/* setup GP timer */
607 	timer_init();
608 
609 	/* UART clocks enabled and gd valid - init serial console */
610 	preloader_console_init();
611 
612 	/* read/validate EEPROM info to determine board model and SDRAM cfg */
613 	board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
614 
615 	/* configure model-specific gpio */
616 	setup_iomux_gpio(board_model, &ventana_info);
617 
618 	/* provide some some default: 32bit 128MB */
619 	if (GW_UNKNOWN == board_model)
620 		hang();
621 
622 	/* configure MMDC for SDRAM width/size and per-model calibration */
623 	spl_dram_init(8 << ventana_info.sdram_width,
624 		      16 << ventana_info.sdram_size,
625 		      board_model);
626 }
627 
board_boot_order(u32 * spl_boot_list)628 void board_boot_order(u32 *spl_boot_list)
629 {
630 	spl_boot_list[0] = spl_boot_device();
631 	switch (spl_boot_list[0]) {
632 	case BOOT_DEVICE_NAND:
633 		spl_boot_list[1] = BOOT_DEVICE_MMC1;
634 		spl_boot_list[2] = BOOT_DEVICE_UART;
635 		break;
636 	case BOOT_DEVICE_MMC1:
637 		spl_boot_list[1] = BOOT_DEVICE_UART;
638 		break;
639 	}
640 }
641 
642 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
643 /* its our chance to print info about boot device */
spl_board_init(void)644 void spl_board_init(void)
645 {
646 	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
647 	u32 boot_device = spl_boot_device();
648 
649 	switch (boot_device) {
650 	case BOOT_DEVICE_MMC1:
651 		puts("Booting from MMC\n");
652 		break;
653 	case BOOT_DEVICE_NAND:
654 		puts("Booting from NAND\n");
655 		break;
656 	case BOOT_DEVICE_SATA:
657 		puts("Booting from SATA\n");
658 		break;
659 	default:
660 		puts("Unknown boot device\n");
661 	}
662 
663 	/* PMIC init */
664 	setup_pmic();
665 }
666 
667 #ifdef CONFIG_SPL_OS_BOOT
668 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
spl_start_uboot(void)669 int spl_start_uboot(void)
670 {
671 	unsigned char ret = 1;
672 
673 	debug("%s\n", __func__);
674 #ifdef CONFIG_SPL_ENV_SUPPORT
675 	env_init();
676 	env_load();
677 	debug("boot_os=%s\n", env_get("boot_os"));
678 	if (env_get_yesno("boot_os") == 1)
679 		ret = 0;
680 #else
681 	/* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
682 	i2c_set_bus_num(0);
683 	gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
684 #endif
685 	if (!ret)
686 		gsc_boot_wd_disable();
687 
688 	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
689 	return ret;
690 }
691 #endif
692