1/* 2 * Copyright (C) 2015 Amarula Solutions B.V. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * Or, alternatively 19 * 20 * b) Permission is hereby granted, free of charge, to any person 21 * obtaining a copy of this software and associated documentation 22 * files (the "Software"), to deal in the Software without 23 * restriction, including without limitation the rights to use 24 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following 27 * conditions: 28 * 29 * The above copyright notice and this permission notice shall be 30 * included in all copies or substantial portions of the Software. 31 * 32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42#include <dt-bindings/gpio/gpio.h> 43#include <dt-bindings/clock/imx6qdl-clock.h> 44 45/ { 46 aliases { 47 mmc1 = &usdhc3; 48 mmc2 = &usdhc4; 49 }; 50 51 memory { 52 reg = <0x10000000 0x80000000>; 53 }; 54}; 55 56&fec { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_enet>; 59 phy-handle = <ð_phy>; 60 phy-mode = "rgmii"; 61 status = "okay"; 62 63 mdio { 64 eth_phy: ethernet-phy { 65 rxc-skew-ps = <1140>; 66 txc-skew-ps = <1140>; 67 txen-skew-ps = <600>; 68 rxdv-skew-ps = <240>; 69 rxd0-skew-ps = <420>; 70 rxd1-skew-ps = <600>; 71 rxd2-skew-ps = <420>; 72 rxd3-skew-ps = <240>; 73 txd0-skew-ps = <60>; 74 txd1-skew-ps = <60>; 75 txd2-skew-ps = <60>; 76 txd3-skew-ps = <240>; 77 }; 78 }; 79}; 80 81&i2c1 { 82 clock-frequency = <100000>; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_i2c1>; 85 status = "okay"; 86}; 87 88&i2c2 { 89 clock-frequency = <100000>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_i2c2>; 92 status = "okay"; 93}; 94 95&i2c3 { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_i2c3>; 98 status = "okay"; 99}; 100 101&uart4 { 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_uart4>; 104 status = "okay"; 105}; 106 107&usdhc3 { 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_usdhc3>; 110 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 111 no-1-8-v; 112 status = "okay"; 113}; 114 115&usdhc4 { 116 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 117 pinctrl-0 = <&pinctrl_usdhc4>; 118 pinctrl-1 = <&pinctrl_usdhc4_100mhz>; 119 pinctrl-2 = <&pinctrl_usdhc4_200mhz>; 120 bus-witdh = <8>; 121 no-1-8-v; 122 non-removable; 123 status = "okay"; 124}; 125 126&iomuxc { 127 pinctrl_enet: enetgrp { 128 fsl,pins = < 129 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 130 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 131 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 132 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 133 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 134 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 135 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 136 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 137 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 138 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 139 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 140 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 141 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 142 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 143 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 144 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 145 >; 146 }; 147 148 pinctrl_i2c1: i2c1grp { 149 fsl,pins = < 150 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 151 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 152 >; 153 }; 154 155 pinctrl_i2c2: i2c2grp { 156 fsl,pins = < 157 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 158 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 159 >; 160 }; 161 162 pinctrl_i2c3: i2c3grp { 163 fsl,pins = < 164 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 165 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 166 >; 167 }; 168 169 pinctrl_uart4: uart4grp { 170 fsl,pins = < 171 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 172 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 173 >; 174 }; 175 176 pinctrl_usdhc3: usdhc3grp { 177 fsl,pins = < 178 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 179 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 180 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 181 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 182 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 183 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 184 >; 185 }; 186 187 pinctrl_usdhc4: usdhc4grp { 188 fsl,pins = < 189 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 190 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 191 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 192 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 193 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 194 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 195 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 196 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 197 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 198 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 199 >; 200 }; 201 202 pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { 203 fsl,pins = < 204 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 205 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 206 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 207 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 208 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 209 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 210 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 211 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 212 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 213 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 214 >; 215 }; 216 217 pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { 218 fsl,pins = < 219 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 220 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 221 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 222 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 223 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 224 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 225 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 226 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 227 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 228 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 229 >; 230 }; 231 232}; 233