1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5475 board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5475EVB_H 14 #define _M5475EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_HW_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27 #define CONFIG_SLTTMR 28 29 #define CONFIG_FSLDMAFEC 30 #ifdef CONFIG_FSLDMAFEC 31 # define CONFIG_MII 1 32 # define CONFIG_MII_INIT 1 33 # define CONFIG_HAS_ETH1 34 35 # define CONFIG_SYS_DMA_USE_INTSRAM 1 36 # define CONFIG_SYS_DISCOVER_PHY 37 # define CONFIG_SYS_RX_ETH_BUFFER 32 38 # define CONFIG_SYS_TX_ETH_BUFFER 48 39 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 40 41 # define CONFIG_SYS_FEC0_PINMUX 0 42 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 43 # define CONFIG_SYS_FEC1_PINMUX 0 44 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 45 46 # define MCFFEC_TOUT_LOOP 50000 47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 48 # ifndef CONFIG_SYS_DISCOVER_PHY 49 # define FECDUPLEX FULL 50 # define FECSPEED _100BASET 51 # else 52 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # endif 55 # endif /* CONFIG_SYS_DISCOVER_PHY */ 56 57 # define CONFIG_IPADDR 192.162.1.2 58 # define CONFIG_NETMASK 255.255.255.0 59 # define CONFIG_SERVERIP 192.162.1.1 60 # define CONFIG_GATEWAYIP 192.162.1.1 61 62 #endif 63 64 #ifdef CONFIG_CMD_USB 65 # define CONFIG_USB_OHCI_NEW 66 67 # define CONFIG_PCI_OHCI 68 69 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 70 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 71 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 72 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 73 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 74 #endif 75 76 /* I2C */ 77 #define CONFIG_SYS_I2C 78 #define CONFIG_SYS_I2C_FSL 79 #define CONFIG_SYS_FSL_I2C_SPEED 80000 80 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 81 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 82 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 83 84 /* PCI */ 85 #ifdef CONFIG_CMD_PCI 86 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 87 88 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 89 90 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 91 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 92 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 93 94 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 95 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 96 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 97 98 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 99 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 100 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 101 #endif 102 103 #define CONFIG_UDP_CHECKSUM 104 105 #ifdef CONFIG_MCFFEC 106 # define CONFIG_IPADDR 192.162.1.2 107 # define CONFIG_NETMASK 255.255.255.0 108 # define CONFIG_SERVERIP 192.162.1.1 109 # define CONFIG_GATEWAYIP 192.162.1.1 110 #endif /* FEC_ENET */ 111 112 #define CONFIG_HOSTNAME "M547xEVB" 113 #define CONFIG_EXTRA_ENV_SETTINGS \ 114 "netdev=eth0\0" \ 115 "loadaddr=10000\0" \ 116 "u-boot=u-boot.bin\0" \ 117 "load=tftp ${loadaddr) ${u-boot}\0" \ 118 "upd=run load; run prog\0" \ 119 "prog=prot off bank 1;" \ 120 "era ff800000 ff83ffff;" \ 121 "cp.b ${loadaddr} ff800000 ${filesize};"\ 122 "save\0" \ 123 "" 124 125 #define CONFIG_PRAM 512 /* 512 KB */ 126 127 #define CONFIG_SYS_LOAD_ADDR 0x00010000 128 129 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 130 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 131 132 #define CONFIG_SYS_MBAR 0xF0000000 133 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 134 #define CONFIG_SYS_INTSRAMSZ 0x8000 135 136 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 137 138 /* 139 * Low Level Configuration Settings 140 * (address mappings, register initial values, etc.) 141 * You should know what you are doing if you make changes here. 142 */ 143 /*----------------------------------------------------------------------- 144 * Definitions for initial stack pointer and data area (in DPRAM) 145 */ 146 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 147 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 148 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 149 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 150 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 151 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 152 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 155 /*----------------------------------------------------------------------- 156 * Start addresses for the final memory configuration 157 * (Set up by the startup code) 158 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 159 */ 160 #define CONFIG_SYS_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 162 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 163 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 164 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 165 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 166 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 167 #ifdef CONFIG_SYS_DRAMSZ1 168 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 169 #else 170 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 171 #endif 172 173 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 174 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 175 176 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 177 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 178 179 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 180 181 /* Reserve 256 kB for malloc() */ 182 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 183 /* 184 * For booting Linux, the board info and command line data 185 * have to be in the first 8 MB of memory, since this is 186 * the maximum mapped by the Linux kernel during initialization ?? 187 */ 188 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 189 190 /*----------------------------------------------------------------------- 191 * FLASH organization 192 */ 193 #define CONFIG_SYS_FLASH_CFI 194 #ifdef CONFIG_SYS_FLASH_CFI 195 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 196 # define CONFIG_FLASH_CFI_DRIVER 1 197 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 198 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 199 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 200 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 201 #ifdef CONFIG_SYS_NOR1SZ 202 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 203 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 204 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 205 #else 206 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 207 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 208 #endif 209 #endif 210 211 /* Configuration for environment 212 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 213 * First time runing may have env crc error warning if there is 214 * no correct environment on the flash. 215 */ 216 #define CONFIG_ENV_OFFSET 0x40000 217 #define CONFIG_ENV_SECT_SIZE 0x10000 218 219 /*----------------------------------------------------------------------- 220 * Cache Configuration 221 */ 222 #define CONFIG_SYS_CACHELINE_SIZE 16 223 224 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 225 CONFIG_SYS_INIT_RAM_SIZE - 8) 226 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 227 CONFIG_SYS_INIT_RAM_SIZE - 4) 228 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 229 CF_CACR_IDCM) 230 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 231 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 232 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 233 CF_ACR_EN | CF_ACR_SM_ALL) 234 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 235 CF_CACR_IEC | CF_CACR_ICINVA) 236 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 237 CF_CACR_DEC | CF_CACR_DDCM_P | \ 238 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 239 240 /*----------------------------------------------------------------------- 241 * Chipselect bank definitions 242 */ 243 /* 244 * CS0 - NOR Flash 1, 2, 4, or 8MB 245 * CS1 - NOR Flash 246 * CS2 - Available 247 * CS3 - Available 248 * CS4 - Available 249 * CS5 - Available 250 */ 251 #define CONFIG_SYS_CS0_BASE 0xFF800000 252 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 253 #define CONFIG_SYS_CS0_CTRL 0x00101980 254 255 #ifdef CONFIG_SYS_NOR1SZ 256 #define CONFIG_SYS_CS1_BASE 0xE0000000 257 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 258 #define CONFIG_SYS_CS1_CTRL 0x00101D80 259 #endif 260 261 #endif /* _M5475EVB_H */ 262