1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * mpc8349emds board configuration file 9 * 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x family */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 22 #define CONFIG_PCI_66M 23 #ifdef CONFIG_PCI_66M 24 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 25 #else 26 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 27 #endif 28 29 #ifdef CONFIG_PCISLAVE 30 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 31 #endif /* CONFIG_PCISLAVE */ 32 33 #ifndef CONFIG_SYS_CLK_FREQ 34 #ifdef CONFIG_PCI_66M 35 #define CONFIG_SYS_CLK_FREQ 66000000 36 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 37 #else 38 #define CONFIG_SYS_CLK_FREQ 33000000 39 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 40 #endif 41 #endif 42 43 #define CONFIG_SYS_IMMR 0xE0000000 44 45 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 46 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 47 #define CONFIG_SYS_MEMTEST_END 0x00100000 48 49 /* 50 * DDR Setup 51 */ 52 #define CONFIG_DDR_ECC /* support DDR ECC function */ 53 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 54 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 55 56 /* 57 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver 58 * unselect it to use old spd_sdram.c 59 */ 60 #define CONFIG_SYS_SPD_BUS_NUM 0 61 #define SPD_EEPROM_ADDRESS1 0x52 62 #define SPD_EEPROM_ADDRESS2 0x51 63 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 64 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 66 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 67 68 /* 69 * 32-bit data path mode. 70 * 71 * Please note that using this mode for devices with the real density of 64-bit 72 * effectively reduces the amount of available memory due to the effect of 73 * wrapping around while translating address to row/columns, for example in the 74 * 256MB module the upper 128MB get aliased with contents of the lower 75 * 128MB); normally this define should be used for devices with real 32-bit 76 * data path. 77 */ 78 #undef CONFIG_DDR_32BIT 79 80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 82 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 83 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 84 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 85 #undef CONFIG_DDR_2T_TIMING 86 87 /* 88 * DDRCDR - DDR Control Driver Register 89 */ 90 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 91 92 #if defined(CONFIG_SPD_EEPROM) 93 /* 94 * Determine DDR configuration from I2C interface. 95 */ 96 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 97 #else 98 /* 99 * Manually set up DDR parameters 100 */ 101 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 102 #if defined(CONFIG_DDR_II) 103 #define CONFIG_SYS_DDRCDR 0x80080001 104 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 105 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 106 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 107 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 108 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 109 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 110 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 111 #define CONFIG_SYS_DDR_MODE 0x47d00432 112 #define CONFIG_SYS_DDR_MODE2 0x8000c000 113 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 114 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 115 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 116 #else 117 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 118 | CSCONFIG_ROW_BIT_13 \ 119 | CSCONFIG_COL_BIT_10) 120 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 122 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 123 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 124 125 #if defined(CONFIG_DDR_32BIT) 126 /* set burst length to 8 for 32-bit data path */ 127 /* DLL,normal,seq,4/2.5, 8 burst len */ 128 #define CONFIG_SYS_DDR_MODE 0x00000023 129 #else 130 /* the default burst length is 4 - for 64-bit data path */ 131 /* DLL,normal,seq,4/2.5, 4 burst len */ 132 #define CONFIG_SYS_DDR_MODE 0x00000022 133 #endif 134 #endif 135 #endif 136 137 /* 138 * SDRAM on the Local Bus 139 */ 140 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 141 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 142 143 /* 144 * FLASH on the Local Bus 145 */ 146 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 147 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 148 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 149 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 150 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 151 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 152 153 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 154 | BR_PS_16 /* 16 bit port */ \ 155 | BR_MS_GPCM /* MSEL = GPCM */ \ 156 | BR_V) /* valid */ 157 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 158 | OR_UPM_XAM \ 159 | OR_GPCM_CSNT \ 160 | OR_GPCM_ACS_DIV2 \ 161 | OR_GPCM_XACS \ 162 | OR_GPCM_SCY_15 \ 163 | OR_GPCM_TRLX_SET \ 164 | OR_GPCM_EHTR_SET \ 165 | OR_GPCM_EAD) 166 167 /* window base at flash base */ 168 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 169 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 170 171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 172 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 173 174 #undef CONFIG_SYS_FLASH_CHECKSUM 175 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 177 178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 179 180 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 181 #define CONFIG_SYS_RAMBOOT 182 #else 183 #undef CONFIG_SYS_RAMBOOT 184 #endif 185 186 /* 187 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 188 */ 189 #define CONFIG_SYS_BCSR 0xE2400000 190 /* Access window base at BCSR base */ 191 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 192 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 193 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 194 | BR_PS_8 \ 195 | BR_MS_GPCM \ 196 | BR_V) 197 /* 0x00000801 */ 198 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 199 | OR_GPCM_XAM \ 200 | OR_GPCM_CSNT \ 201 | OR_GPCM_SCY_15 \ 202 | OR_GPCM_TRLX_CLEAR \ 203 | OR_GPCM_EHTR_CLEAR) 204 /* 0xFFFFE8F0 */ 205 206 #define CONFIG_SYS_INIT_RAM_LOCK 1 207 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 208 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 209 210 #define CONFIG_SYS_GBL_DATA_OFFSET \ 211 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 214 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 215 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 216 217 /* 218 * Local Bus LCRR and LBCR regs 219 * LCRR: DLL bypass, Clock divider is 4 220 * External Local Bus rate is 221 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 222 */ 223 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 224 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 225 #define CONFIG_SYS_LBC_LBCR 0x00000000 226 227 /* 228 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 229 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 230 */ 231 #undef CONFIG_SYS_LB_SDRAM 232 233 #ifdef CONFIG_SYS_LB_SDRAM 234 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 235 /* 236 * Base Register 2 and Option Register 2 configure SDRAM. 237 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 238 * 239 * For BR2, need: 240 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 241 * port-size = 32-bits = BR2[19:20] = 11 242 * no parity checking = BR2[21:22] = 00 243 * SDRAM for MSEL = BR2[24:26] = 011 244 * Valid = BR[31] = 1 245 * 246 * 0 4 8 12 16 20 24 28 247 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 248 */ 249 250 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 251 | BR_PS_32 /* 32-bit port */ \ 252 | BR_MS_SDRAM /* MSEL = SDRAM */ \ 253 | BR_V) /* Valid */ 254 /* 0xF0001861 */ 255 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 256 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 257 258 /* 259 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 260 * 261 * For OR2, need: 262 * 64MB mask for AM, OR2[0:7] = 1111 1100 263 * XAM, OR2[17:18] = 11 264 * 9 columns OR2[19-21] = 010 265 * 13 rows OR2[23-25] = 100 266 * EAD set for extra time OR[31] = 1 267 * 268 * 0 4 8 12 16 20 24 28 269 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 270 */ 271 272 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ 273 | OR_SDRAM_XAM \ 274 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 275 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 276 | OR_SDRAM_EAD) 277 /* 0xFC006901 */ 278 279 /* LB sdram refresh timer, about 6us */ 280 #define CONFIG_SYS_LBC_LSRT 0x32000000 281 /* LB refresh timer prescal, 266MHz/32 */ 282 #define CONFIG_SYS_LBC_MRTPR 0x20000000 283 284 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 285 | LSDMR_BSMA1516 \ 286 | LSDMR_RFCR8 \ 287 | LSDMR_PRETOACT6 \ 288 | LSDMR_ACTTORW3 \ 289 | LSDMR_BL8 \ 290 | LSDMR_WRC3 \ 291 | LSDMR_CL3) 292 293 /* 294 * SDRAM Controller configuration sequence. 295 */ 296 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 297 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 298 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 299 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 300 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 301 #endif 302 303 /* 304 * Serial Port 305 */ 306 #define CONFIG_SYS_NS16550_SERIAL 307 #define CONFIG_SYS_NS16550_REG_SIZE 1 308 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 309 310 #define CONFIG_SYS_BAUDRATE_TABLE \ 311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 312 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 315 316 /* I2C */ 317 #define CONFIG_SYS_I2C 318 #define CONFIG_SYS_I2C_FSL 319 #define CONFIG_SYS_FSL_I2C_SPEED 400000 320 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 321 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 322 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 323 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 324 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 325 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 326 327 /* SPI */ 328 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 329 330 /* GPIOs. Used as SPI chip selects */ 331 #define CONFIG_SYS_GPIO1_PRELIM 332 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 333 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 334 335 /* TSEC */ 336 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 337 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 338 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 339 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 340 341 /* USB */ 342 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 343 344 /* 345 * General PCI 346 * Addresses are mapped 1-1. 347 */ 348 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 349 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 350 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 351 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 352 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 353 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 354 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 355 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 356 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 357 358 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 359 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 360 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 361 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 362 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 363 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 364 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 365 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 366 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 367 368 #if defined(CONFIG_PCI) 369 370 #define PCI_ONE_PCI1 371 #if defined(PCI_64BIT) 372 #undef PCI_ALL_PCI1 373 #undef PCI_TWO_PCI1 374 #undef PCI_ONE_PCI1 375 #endif 376 377 #define CONFIG_83XX_PCI_STREAMING 378 379 #undef CONFIG_EEPRO100 380 #undef CONFIG_TULIP 381 382 #if !defined(CONFIG_PCI_PNP) 383 #define PCI_ENET0_IOADDR 0xFIXME 384 #define PCI_ENET0_MEMADDR 0xFIXME 385 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 386 #endif 387 388 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 389 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 390 391 #endif /* CONFIG_PCI */ 392 393 /* 394 * TSEC configuration 395 */ 396 397 #if defined(CONFIG_TSEC_ENET) 398 399 #define CONFIG_GMII 1 /* MII PHY management */ 400 #define CONFIG_TSEC1 1 401 #define CONFIG_TSEC1_NAME "TSEC0" 402 #define CONFIG_TSEC2 1 403 #define CONFIG_TSEC2_NAME "TSEC1" 404 #define TSEC1_PHY_ADDR 0 405 #define TSEC2_PHY_ADDR 1 406 #define TSEC1_PHYIDX 0 407 #define TSEC2_PHYIDX 0 408 #define TSEC1_FLAGS TSEC_GIGABIT 409 #define TSEC2_FLAGS TSEC_GIGABIT 410 411 /* Options are: TSEC[0-1] */ 412 #define CONFIG_ETHPRIME "TSEC0" 413 414 #endif /* CONFIG_TSEC_ENET */ 415 416 /* 417 * Configure on-board RTC 418 */ 419 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 420 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 421 422 /* 423 * Environment 424 */ 425 #ifndef CONFIG_SYS_RAMBOOT 426 #define CONFIG_ENV_ADDR \ 427 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 428 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 429 #define CONFIG_ENV_SIZE 0x2000 430 431 /* Address and size of Redundant Environment Sector */ 432 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 433 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 434 435 #else 436 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 437 #define CONFIG_ENV_SIZE 0x2000 438 #endif 439 440 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 441 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 442 443 /* 444 * BOOTP options 445 */ 446 #define CONFIG_BOOTP_BOOTFILESIZE 447 448 /* 449 * Command line configuration. 450 */ 451 452 #undef CONFIG_WATCHDOG /* watchdog disabled */ 453 454 /* 455 * Miscellaneous configurable options 456 */ 457 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 458 459 /* 460 * For booting Linux, the board info and command line data 461 * have to be in the first 256 MB of memory, since this is 462 * the maximum mapped by the Linux kernel during initialization. 463 */ 464 /* Initial Memory map for Linux*/ 465 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 466 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 467 468 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 469 470 #if 1 /*528/264*/ 471 #define CONFIG_SYS_HRCW_LOW (\ 472 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 473 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 474 HRCWL_CSB_TO_CLKIN |\ 475 HRCWL_VCO_1X2 |\ 476 HRCWL_CORE_TO_CSB_2X1) 477 #elif 0 /*396/132*/ 478 #define CONFIG_SYS_HRCW_LOW (\ 479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 480 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 481 HRCWL_CSB_TO_CLKIN |\ 482 HRCWL_VCO_1X4 |\ 483 HRCWL_CORE_TO_CSB_3X1) 484 #elif 0 /*264/132*/ 485 #define CONFIG_SYS_HRCW_LOW (\ 486 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 487 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 488 HRCWL_CSB_TO_CLKIN |\ 489 HRCWL_VCO_1X4 |\ 490 HRCWL_CORE_TO_CSB_2X1) 491 #elif 0 /*132/132*/ 492 #define CONFIG_SYS_HRCW_LOW (\ 493 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 494 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 495 HRCWL_CSB_TO_CLKIN |\ 496 HRCWL_VCO_1X4 |\ 497 HRCWL_CORE_TO_CSB_1X1) 498 #elif 0 /*264/264 */ 499 #define CONFIG_SYS_HRCW_LOW (\ 500 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 501 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 502 HRCWL_CSB_TO_CLKIN |\ 503 HRCWL_VCO_1X4 |\ 504 HRCWL_CORE_TO_CSB_1X1) 505 #endif 506 507 #ifdef CONFIG_PCISLAVE 508 #define CONFIG_SYS_HRCW_HIGH (\ 509 HRCWH_PCI_AGENT |\ 510 HRCWH_64_BIT_PCI |\ 511 HRCWH_PCI1_ARBITER_DISABLE |\ 512 HRCWH_PCI2_ARBITER_DISABLE |\ 513 HRCWH_CORE_ENABLE |\ 514 HRCWH_FROM_0X00000100 |\ 515 HRCWH_BOOTSEQ_DISABLE |\ 516 HRCWH_SW_WATCHDOG_DISABLE |\ 517 HRCWH_ROM_LOC_LOCAL_16BIT |\ 518 HRCWH_TSEC1M_IN_GMII |\ 519 HRCWH_TSEC2M_IN_GMII) 520 #else 521 #if defined(PCI_64BIT) 522 #define CONFIG_SYS_HRCW_HIGH (\ 523 HRCWH_PCI_HOST |\ 524 HRCWH_64_BIT_PCI |\ 525 HRCWH_PCI1_ARBITER_ENABLE |\ 526 HRCWH_PCI2_ARBITER_DISABLE |\ 527 HRCWH_CORE_ENABLE |\ 528 HRCWH_FROM_0X00000100 |\ 529 HRCWH_BOOTSEQ_DISABLE |\ 530 HRCWH_SW_WATCHDOG_DISABLE |\ 531 HRCWH_ROM_LOC_LOCAL_16BIT |\ 532 HRCWH_TSEC1M_IN_GMII |\ 533 HRCWH_TSEC2M_IN_GMII) 534 #else 535 #define CONFIG_SYS_HRCW_HIGH (\ 536 HRCWH_PCI_HOST |\ 537 HRCWH_32_BIT_PCI |\ 538 HRCWH_PCI1_ARBITER_ENABLE |\ 539 HRCWH_PCI2_ARBITER_ENABLE |\ 540 HRCWH_CORE_ENABLE |\ 541 HRCWH_FROM_0X00000100 |\ 542 HRCWH_BOOTSEQ_DISABLE |\ 543 HRCWH_SW_WATCHDOG_DISABLE |\ 544 HRCWH_ROM_LOC_LOCAL_16BIT |\ 545 HRCWH_TSEC1M_IN_GMII |\ 546 HRCWH_TSEC2M_IN_GMII) 547 #endif /* PCI_64BIT */ 548 #endif /* CONFIG_PCISLAVE */ 549 550 /* 551 * System performance 552 */ 553 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 554 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 555 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 556 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 557 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 558 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 559 560 /* System IO Config */ 561 #define CONFIG_SYS_SICRH 0 562 #define CONFIG_SYS_SICRL SICRL_LDP_A 563 564 #define CONFIG_SYS_HID0_INIT 0x000000000 565 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 566 | HID0_ENABLE_INSTRUCTION_CACHE) 567 568 /* #define CONFIG_SYS_HID0_FINAL (\ 569 HID0_ENABLE_INSTRUCTION_CACHE |\ 570 HID0_ENABLE_M_BIT |\ 571 HID0_ENABLE_ADDRESS_BROADCAST) */ 572 573 #define CONFIG_SYS_HID2 HID2_HBE 574 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 575 576 /* DDR @ 0x00000000 */ 577 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 578 | BATL_PP_RW \ 579 | BATL_MEMCOHERENCE) 580 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 581 | BATU_BL_256M \ 582 | BATU_VS \ 583 | BATU_VP) 584 585 /* PCI @ 0x80000000 */ 586 #ifdef CONFIG_PCI 587 #define CONFIG_PCI_INDIRECT_BRIDGE 588 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 589 | BATL_PP_RW \ 590 | BATL_MEMCOHERENCE) 591 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 592 | BATU_BL_256M \ 593 | BATU_VS \ 594 | BATU_VP) 595 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 596 | BATL_PP_RW \ 597 | BATL_CACHEINHIBIT \ 598 | BATL_GUARDEDSTORAGE) 599 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 600 | BATU_BL_256M \ 601 | BATU_VS \ 602 | BATU_VP) 603 #else 604 #define CONFIG_SYS_IBAT1L (0) 605 #define CONFIG_SYS_IBAT1U (0) 606 #define CONFIG_SYS_IBAT2L (0) 607 #define CONFIG_SYS_IBAT2U (0) 608 #endif 609 610 #ifdef CONFIG_MPC83XX_PCI2 611 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 612 | BATL_PP_RW \ 613 | BATL_MEMCOHERENCE) 614 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 615 | BATU_BL_256M \ 616 | BATU_VS \ 617 | BATU_VP) 618 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 619 | BATL_PP_RW \ 620 | BATL_CACHEINHIBIT \ 621 | BATL_GUARDEDSTORAGE) 622 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 623 | BATU_BL_256M \ 624 | BATU_VS \ 625 | BATU_VP) 626 #else 627 #define CONFIG_SYS_IBAT3L (0) 628 #define CONFIG_SYS_IBAT3U (0) 629 #define CONFIG_SYS_IBAT4L (0) 630 #define CONFIG_SYS_IBAT4U (0) 631 #endif 632 633 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 634 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 635 | BATL_PP_RW \ 636 | BATL_CACHEINHIBIT \ 637 | BATL_GUARDEDSTORAGE) 638 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 639 | BATU_BL_256M \ 640 | BATU_VS \ 641 | BATU_VP) 642 643 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 644 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 645 | BATL_PP_RW \ 646 | BATL_MEMCOHERENCE \ 647 | BATL_GUARDEDSTORAGE) 648 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 649 | BATU_BL_256M \ 650 | BATU_VS \ 651 | BATU_VP) 652 653 #define CONFIG_SYS_IBAT7L (0) 654 #define CONFIG_SYS_IBAT7U (0) 655 656 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 657 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 658 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 659 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 660 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 661 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 662 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 663 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 664 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 665 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 666 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 667 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 668 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 669 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 670 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 671 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 672 673 #if defined(CONFIG_CMD_KGDB) 674 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 675 #endif 676 677 /* 678 * Environment Configuration 679 */ 680 #define CONFIG_ENV_OVERWRITE 681 682 #if defined(CONFIG_TSEC_ENET) 683 #define CONFIG_HAS_ETH1 684 #define CONFIG_HAS_ETH0 685 #endif 686 687 #define CONFIG_HOSTNAME "mpc8349emds" 688 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 689 #define CONFIG_BOOTFILE "uImage" 690 691 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 692 693 #define CONFIG_PREBOOT "echo;" \ 694 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 695 "echo" 696 697 #define CONFIG_EXTRA_ENV_SETTINGS \ 698 "netdev=eth0\0" \ 699 "hostname=mpc8349emds\0" \ 700 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 701 "nfsroot=${serverip}:${rootpath}\0" \ 702 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 703 "addip=setenv bootargs ${bootargs} " \ 704 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 705 ":${hostname}:${netdev}:off panic=1\0" \ 706 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 707 "flash_nfs=run nfsargs addip addtty;" \ 708 "bootm ${kernel_addr}\0" \ 709 "flash_self=run ramargs addip addtty;" \ 710 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 711 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 712 "bootm\0" \ 713 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 714 "update=protect off fe000000 fe03ffff; " \ 715 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 716 "upd=run load update\0" \ 717 "fdtaddr=780000\0" \ 718 "fdtfile=mpc834x_mds.dtb\0" \ 719 "" 720 721 #define CONFIG_NFSBOOTCOMMAND \ 722 "setenv bootargs root=/dev/nfs rw " \ 723 "nfsroot=$serverip:$rootpath " \ 724 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 725 "$netdev:off " \ 726 "console=$consoledev,$baudrate $othbootargs;" \ 727 "tftp $loadaddr $bootfile;" \ 728 "tftp $fdtaddr $fdtfile;" \ 729 "bootm $loadaddr - $fdtaddr" 730 731 #define CONFIG_RAMBOOTCOMMAND \ 732 "setenv bootargs root=/dev/ram rw " \ 733 "console=$consoledev,$baudrate $othbootargs;" \ 734 "tftp $ramdiskaddr $ramdiskfile;" \ 735 "tftp $loadaddr $bootfile;" \ 736 "tftp $fdtaddr $fdtfile;" \ 737 "bootm $loadaddr $ramdiskaddr $fdtaddr" 738 739 #define CONFIG_BOOTCOMMAND "run flash_self" 740 741 #endif /* __CONFIG_H */ 742