1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 QDS board configuration file 8 */ 9 10 #ifndef __T1024QDS_H 11 #define __T1024QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_MP /* support multiple processors */ 16 #define CONFIG_ENABLE_36BIT_PHYS 17 18 #ifdef CONFIG_PHYS_64BIT 19 #define CONFIG_ADDR_MAP 1 20 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 21 #endif 22 23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 25 26 #define CONFIG_ENV_OVERWRITE 27 28 #define CONFIG_DEEP_SLEEP 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 35 #define CONFIG_SPL_PAD_TO 0x40000 36 #define CONFIG_SPL_MAX_SIZE 0x28000 37 #define RESET_VECTOR_OFFSET 0x27FFC 38 #define BOOT_PAGE_OFFSET 0x27000 39 #ifdef CONFIG_SPL_BUILD 40 #define CONFIG_SPL_SKIP_RELOCATE 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 43 #endif 44 45 #ifdef CONFIG_NAND 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 52 #define CONFIG_SPL_NAND_BOOT 53 #endif 54 55 #ifdef CONFIG_SPIFLASH 56 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 57 #define CONFIG_SPL_SPI_FLASH_MINIMAL 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 63 #ifndef CONFIG_SPL_BUILD 64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 65 #endif 66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 67 #define CONFIG_SPL_SPI_BOOT 68 #endif 69 70 #ifdef CONFIG_SDCARD 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 72 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 74 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 75 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 79 #endif 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 81 #define CONFIG_SPL_MMC_BOOT 82 #endif 83 84 #endif /* CONFIG_RAMBOOT_PBL */ 85 86 #ifndef CONFIG_RESET_VECTOR_ADDRESS 87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 88 #endif 89 90 #ifdef CONFIG_MTD_NOR_FLASH 91 #define CONFIG_FLASH_CFI_DRIVER 92 #define CONFIG_SYS_FLASH_CFI 93 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 94 #endif 95 96 /* PCIe Boot - Master */ 97 #define CONFIG_SRIO_PCIE_BOOT_MASTER 98 /* 99 * for slave u-boot IMAGE instored in master memory space, 100 * PHYS must be aligned based on the SIZE 101 */ 102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 104 #ifdef CONFIG_PHYS_64BIT 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 107 #else 108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 110 #endif 111 /* 112 * for slave UCODE and ENV instored in master memory space, 113 * PHYS must be aligned based on the SIZE 114 */ 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 118 #else 119 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 121 #endif 122 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 123 /* slave core release by master*/ 124 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 125 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 126 127 /* PCIe Boot - Slave */ 128 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 131 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 132 /* Set 1M boot space for PCIe boot */ 133 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 135 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 136 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 137 #endif 138 139 #if defined(CONFIG_SPIFLASH) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_SPI_BUS 0 142 #define CONFIG_ENV_SPI_CS 0 143 #define CONFIG_ENV_SPI_MAX_HZ 10000000 144 #define CONFIG_ENV_SPI_MODE 0 145 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 146 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 147 #define CONFIG_ENV_SECT_SIZE 0x10000 148 #elif defined(CONFIG_SDCARD) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_SYS_MMC_ENV_DEV 0 151 #define CONFIG_ENV_SIZE 0x2000 152 #define CONFIG_ENV_OFFSET (512 * 0x800) 153 #elif defined(CONFIG_NAND) 154 #define CONFIG_SYS_EXTRA_ENV_RELOC 155 #define CONFIG_ENV_SIZE 0x2000 156 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 157 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 158 #define CONFIG_ENV_ADDR 0xffe20000 159 #define CONFIG_ENV_SIZE 0x2000 160 #elif defined(CONFIG_ENV_IS_NOWHERE) 161 #define CONFIG_ENV_SIZE 0x2000 162 #else 163 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 166 #endif 167 168 #ifndef __ASSEMBLY__ 169 unsigned long get_board_sys_clk(void); 170 unsigned long get_board_ddr_clk(void); 171 #endif 172 173 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 174 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 175 176 /* 177 * These can be toggled for performance analysis, otherwise use default. 178 */ 179 #define CONFIG_SYS_CACHE_STASHING 180 #define CONFIG_BACKSIDE_L2_CACHE 181 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 182 #define CONFIG_BTB /* toggle branch predition */ 183 #define CONFIG_DDR_ECC 184 #ifdef CONFIG_DDR_ECC 185 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 186 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 187 #endif 188 189 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 190 #define CONFIG_SYS_MEMTEST_END 0x00400000 191 192 /* 193 * Config the L3 Cache as L3 SRAM 194 */ 195 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 196 #define CONFIG_SYS_L3_SIZE (256 << 10) 197 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 198 #ifdef CONFIG_RAMBOOT_PBL 199 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 200 #endif 201 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 202 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 203 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 204 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 205 206 #ifdef CONFIG_PHYS_64BIT 207 #define CONFIG_SYS_DCSRBAR 0xf0000000 208 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 209 #endif 210 211 /* EEPROM */ 212 #define CONFIG_ID_EEPROM 213 #define CONFIG_SYS_I2C_EEPROM_NXID 214 #define CONFIG_SYS_EEPROM_BUS_NUM 0 215 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 219 220 /* 221 * DDR Setup 222 */ 223 #define CONFIG_VERY_BIG_RAM 224 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 225 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 226 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 227 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 228 #define CONFIG_DDR_SPD 229 230 #define CONFIG_SYS_SPD_BUS_NUM 0 231 #define SPD_EEPROM_ADDRESS 0x51 232 233 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 234 235 /* 236 * IFC Definitions 237 */ 238 #define CONFIG_SYS_FLASH_BASE 0xe0000000 239 #ifdef CONFIG_PHYS_64BIT 240 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 241 #else 242 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 243 #endif 244 245 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 246 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 247 + 0x8000000) | \ 248 CSPR_PORT_SIZE_16 | \ 249 CSPR_MSEL_NOR | \ 250 CSPR_V) 251 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 252 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 253 CSPR_PORT_SIZE_16 | \ 254 CSPR_MSEL_NOR | \ 255 CSPR_V) 256 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 257 /* NOR Flash Timing Params */ 258 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 259 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 260 FTIM0_NOR_TEADC(0x5) | \ 261 FTIM0_NOR_TEAHC(0x5)) 262 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 263 FTIM1_NOR_TRAD_NOR(0x1A) |\ 264 FTIM1_NOR_TSEQRAD_NOR(0x13)) 265 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 266 FTIM2_NOR_TCH(0x4) | \ 267 FTIM2_NOR_TWPH(0x0E) | \ 268 FTIM2_NOR_TWP(0x1c)) 269 #define CONFIG_SYS_NOR_FTIM3 0x0 270 271 #define CONFIG_SYS_FLASH_QUIET_TEST 272 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 273 274 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 275 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 276 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 277 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 278 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 281 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 282 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 283 #define QIXIS_BASE 0xffdf0000 284 #ifdef CONFIG_PHYS_64BIT 285 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 286 #else 287 #define QIXIS_BASE_PHYS QIXIS_BASE 288 #endif 289 #define QIXIS_LBMAP_SWITCH 0x06 290 #define QIXIS_LBMAP_MASK 0x0f 291 #define QIXIS_LBMAP_SHIFT 0 292 #define QIXIS_LBMAP_DFLTBANK 0x00 293 #define QIXIS_LBMAP_ALTBANK 0x04 294 #define QIXIS_RST_CTL_RESET 0x31 295 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 296 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 297 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 298 #define QIXIS_RST_FORCE_MEM 0x01 299 300 #define CONFIG_SYS_CSPR3_EXT (0xf) 301 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 302 | CSPR_PORT_SIZE_8 \ 303 | CSPR_MSEL_GPCM \ 304 | CSPR_V) 305 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 306 #define CONFIG_SYS_CSOR3 0x0 307 /* QIXIS Timing parameters for IFC CS3 */ 308 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 309 FTIM0_GPCM_TEADC(0x0e) | \ 310 FTIM0_GPCM_TEAHC(0x0e)) 311 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 312 FTIM1_GPCM_TRAD(0x3f)) 313 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 314 FTIM2_GPCM_TCH(0x8) | \ 315 FTIM2_GPCM_TWP(0x1f)) 316 #define CONFIG_SYS_CS3_FTIM3 0x0 317 318 #define CONFIG_NAND_FSL_IFC 319 #define CONFIG_SYS_NAND_BASE 0xff800000 320 #ifdef CONFIG_PHYS_64BIT 321 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 322 #else 323 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 324 #endif 325 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 326 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 327 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 328 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 329 | CSPR_V) 330 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 331 332 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 333 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 334 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 335 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 336 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 337 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 338 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 339 340 #define CONFIG_SYS_NAND_ONFI_DETECTION 341 342 /* ONFI NAND Flash mode0 Timing Params */ 343 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 344 FTIM0_NAND_TWP(0x18) | \ 345 FTIM0_NAND_TWCHT(0x07) | \ 346 FTIM0_NAND_TWH(0x0a)) 347 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 348 FTIM1_NAND_TWBE(0x39) | \ 349 FTIM1_NAND_TRR(0x0e) | \ 350 FTIM1_NAND_TRP(0x18)) 351 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 352 FTIM2_NAND_TREH(0x0a) | \ 353 FTIM2_NAND_TWHRE(0x1e)) 354 #define CONFIG_SYS_NAND_FTIM3 0x0 355 356 #define CONFIG_SYS_NAND_DDR_LAW 11 357 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 358 #define CONFIG_SYS_MAX_NAND_DEVICE 1 359 360 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 361 362 #if defined(CONFIG_NAND) 363 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 364 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 365 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 366 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 367 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 368 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 369 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 370 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 371 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 372 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 373 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 380 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 381 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 382 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 383 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 384 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 385 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 386 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 387 #else 388 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 389 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 390 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 391 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 392 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 393 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 394 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 395 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 396 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 397 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 398 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 399 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 400 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 401 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 402 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 403 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 404 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 405 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 406 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 407 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 408 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 409 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 410 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 411 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 412 #endif 413 414 #ifdef CONFIG_SPL_BUILD 415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 416 #else 417 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 418 #endif 419 420 #if defined(CONFIG_RAMBOOT_PBL) 421 #define CONFIG_SYS_RAMBOOT 422 #endif 423 424 #define CONFIG_MISC_INIT_R 425 426 #define CONFIG_HWCONFIG 427 428 /* define to use L1 as initial stack */ 429 #define CONFIG_L1_INIT_RAM 430 #define CONFIG_SYS_INIT_RAM_LOCK 431 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 435 /* The assembler doesn't like typecast */ 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 437 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 438 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 439 #else 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 443 #endif 444 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 445 446 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 447 GENERATED_GBL_DATA_SIZE) 448 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 449 450 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 451 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 452 453 /* Serial Port */ 454 #define CONFIG_SYS_NS16550_SERIAL 455 #define CONFIG_SYS_NS16550_REG_SIZE 1 456 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 457 458 #define CONFIG_SYS_BAUDRATE_TABLE \ 459 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 460 461 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 462 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 463 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 464 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 465 466 /* Video */ 467 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 468 #define CONFIG_FSL_DIU_FB 469 #ifdef CONFIG_FSL_DIU_FB 470 #define CONFIG_FSL_DIU_CH7301 471 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 472 #define CONFIG_VIDEO_LOGO 473 #define CONFIG_VIDEO_BMP_LOGO 474 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 475 /* 476 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 477 * disable empty flash sector detection, which is I/O-intensive. 478 */ 479 #undef CONFIG_SYS_FLASH_EMPTY_INFO 480 #endif 481 #endif 482 483 /* I2C */ 484 #define CONFIG_SYS_I2C 485 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 486 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 487 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 488 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 489 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 490 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 491 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 492 493 #define I2C_MUX_PCA_ADDR 0x77 494 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 495 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 496 #define I2C_RETIMER_ADDR 0x18 497 498 /* I2C bus multiplexer */ 499 #define I2C_MUX_CH_DEFAULT 0x8 500 #define I2C_MUX_CH_DIU 0xC 501 #define I2C_MUX_CH5 0xD 502 #define I2C_MUX_CH7 0xF 503 504 /* LDI/DVI Encoder for display */ 505 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 506 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 507 508 /* 509 * RTC configuration 510 */ 511 #define RTC 512 #define CONFIG_RTC_DS3231 1 513 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 514 515 /* 516 * eSPI - Enhanced SPI 517 */ 518 #ifndef CONFIG_SPL_BUILD 519 #endif 520 #define CONFIG_SPI_FLASH_BAR 521 #define CONFIG_SF_DEFAULT_SPEED 10000000 522 #define CONFIG_SF_DEFAULT_MODE 0 523 524 /* 525 * General PCIe 526 * Memory space is mapped 1-1, but I/O space must start from 0. 527 */ 528 #define CONFIG_PCIE1 /* PCIE controller 1 */ 529 #define CONFIG_PCIE2 /* PCIE controller 2 */ 530 #define CONFIG_PCIE3 /* PCIE controller 3 */ 531 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 532 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 533 #define CONFIG_PCI_INDIRECT_BRIDGE 534 535 #ifdef CONFIG_PCI 536 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 537 #ifdef CONFIG_PCIE1 538 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 539 #ifdef CONFIG_PHYS_64BIT 540 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 542 #else 543 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 544 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 545 #endif 546 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 547 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 548 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 549 #ifdef CONFIG_PHYS_64BIT 550 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 551 #else 552 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 553 #endif 554 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 555 #endif 556 557 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 558 #ifdef CONFIG_PCIE2 559 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 560 #ifdef CONFIG_PHYS_64BIT 561 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 562 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 563 #else 564 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 565 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 566 #endif 567 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 569 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 570 #ifdef CONFIG_PHYS_64BIT 571 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 572 #else 573 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 574 #endif 575 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 576 #endif 577 578 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 579 #ifdef CONFIG_PCIE3 580 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 581 #ifdef CONFIG_PHYS_64BIT 582 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 584 #else 585 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 586 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 587 #endif 588 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 590 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 591 #ifdef CONFIG_PHYS_64BIT 592 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 593 #else 594 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 595 #endif 596 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 597 #endif 598 599 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 600 #endif /* CONFIG_PCI */ 601 602 /* 603 *SATA 604 */ 605 #define CONFIG_FSL_SATA_V2 606 #ifdef CONFIG_FSL_SATA_V2 607 #define CONFIG_SYS_SATA_MAX_DEVICE 1 608 #define CONFIG_SATA1 609 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 610 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 611 #define CONFIG_LBA48 612 #endif 613 614 /* 615 * USB 616 */ 617 #define CONFIG_HAS_FSL_DR_USB 618 619 #ifdef CONFIG_HAS_FSL_DR_USB 620 #define CONFIG_USB_EHCI_FSL 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 622 #endif 623 624 /* 625 * SDHC 626 */ 627 #ifdef CONFIG_MMC 628 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 629 #endif 630 631 /* Qman/Bman */ 632 #ifndef CONFIG_NOBQFMAN 633 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 634 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 635 #ifdef CONFIG_PHYS_64BIT 636 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 637 #else 638 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 639 #endif 640 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 641 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 642 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 643 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 644 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 645 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 646 CONFIG_SYS_BMAN_CENA_SIZE) 647 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 648 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 649 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 650 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 651 #ifdef CONFIG_PHYS_64BIT 652 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 653 #else 654 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 655 #endif 656 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 657 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 658 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 659 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 660 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 661 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 662 CONFIG_SYS_QMAN_CENA_SIZE) 663 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 664 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 665 666 #define CONFIG_SYS_DPAA_FMAN 667 668 #define CONFIG_QE 669 #define CONFIG_U_QE 670 /* Default address of microcode for the Linux FMan driver */ 671 #if defined(CONFIG_SPIFLASH) 672 /* 673 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 674 * env, so we got 0x110000. 675 */ 676 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 677 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 678 #define CONFIG_SYS_QE_FW_ADDR 0x130000 679 #elif defined(CONFIG_SDCARD) 680 /* 681 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 682 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 683 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 684 */ 685 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 686 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 687 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 688 #elif defined(CONFIG_NAND) 689 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 690 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 691 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 692 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 693 /* 694 * Slave has no ucode locally, it can fetch this from remote. When implementing 695 * in two corenet boards, slave's ucode could be stored in master's memory 696 * space, the address can be mapped from slave TLB->slave LAW-> 697 * slave SRIO or PCIE outbound window->master inbound window-> 698 * master LAW->the ucode address in master's memory space. 699 */ 700 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 701 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 702 #else 703 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 704 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 705 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 706 #endif 707 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 708 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 709 #endif /* CONFIG_NOBQFMAN */ 710 711 #ifdef CONFIG_SYS_DPAA_FMAN 712 #define CONFIG_FMAN_ENET 713 #define CONFIG_PHYLIB_10G 714 #define CONFIG_PHY_VITESSE 715 #define CONFIG_PHY_REALTEK 716 #define CONFIG_PHY_TERANETICS 717 #define RGMII_PHY1_ADDR 0x1 718 #define RGMII_PHY2_ADDR 0x2 719 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 720 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 721 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 722 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 723 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 724 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 725 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 726 #endif 727 728 #ifdef CONFIG_FMAN_ENET 729 #define CONFIG_MII /* MII PHY management */ 730 #define CONFIG_ETHPRIME "FM1@DTSEC4" 731 #endif 732 733 /* 734 * Dynamic MTD Partition support with mtdparts 735 */ 736 #ifdef CONFIG_MTD_NOR_FLASH 737 #define CONFIG_MTD_DEVICE 738 #define CONFIG_MTD_PARTITIONS 739 #define CONFIG_FLASH_CFI_MTD 740 #endif 741 742 /* 743 * Environment 744 */ 745 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 746 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 747 748 /* 749 * Miscellaneous configurable options 750 */ 751 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 752 753 /* 754 * For booting Linux, the board info and command line data 755 * have to be in the first 64 MB of memory, since this is 756 * the maximum mapped by the Linux kernel during initialization. 757 */ 758 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 759 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 760 761 #ifdef CONFIG_CMD_KGDB 762 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 763 #endif 764 765 /* 766 * Environment Configuration 767 */ 768 #define CONFIG_ROOTPATH "/opt/nfsroot" 769 #define CONFIG_BOOTFILE "uImage" 770 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 771 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 772 #define __USB_PHY_TYPE utmi 773 774 #define CONFIG_EXTRA_ENV_SETTINGS \ 775 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 776 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 777 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 778 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 779 "fdtfile=t1024qds/t1024qds.dtb\0" \ 780 "netdev=eth0\0" \ 781 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 782 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 783 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 784 "tftpflash=tftpboot $loadaddr $uboot && " \ 785 "protect off $ubootaddr +$filesize && " \ 786 "erase $ubootaddr +$filesize && " \ 787 "cp.b $loadaddr $ubootaddr $filesize && " \ 788 "protect on $ubootaddr +$filesize && " \ 789 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 790 "consoledev=ttyS0\0" \ 791 "ramdiskaddr=2000000\0" \ 792 "fdtaddr=d00000\0" \ 793 "bdev=sda3\0" 794 795 #define CONFIG_LINUX \ 796 "setenv bootargs root=/dev/ram rw " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "setenv ramdiskaddr 0x02000000;" \ 799 "setenv fdtaddr 0x00c00000;" \ 800 "setenv loadaddr 0x1000000;" \ 801 "bootm $loadaddr $ramdiskaddr $fdtaddr" 802 803 #define CONFIG_NFSBOOTCOMMAND \ 804 "setenv bootargs root=/dev/nfs rw " \ 805 "nfsroot=$serverip:$rootpath " \ 806 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 807 "console=$consoledev,$baudrate $othbootargs;" \ 808 "tftp $loadaddr $bootfile;" \ 809 "tftp $fdtaddr $fdtfile;" \ 810 "bootm $loadaddr - $fdtaddr" 811 812 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 813 814 #include <asm/fsl_secure_boot.h> 815 816 #endif /* __T1024QDS_H */ 817