1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) 4 */ 5 6 #ifndef __CONFIG_ZYNQMP_R5_H 7 #define __CONFIG_ZYNQMP_R5_H 8 9 #define CONFIG_EXTRA_ENV_SETTINGS 10 11 /* CPU clock */ 12 #define CONFIG_CPU_FREQ_HZ 500000000 13 14 /* Serial drivers */ 15 /* The following table includes the supported baudrates */ 16 #define CONFIG_SYS_BAUDRATE_TABLE \ 17 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 18 19 # define CONFIG_ENV_SIZE (128 << 10) 20 21 /* Allow to overwrite serial and ethaddr */ 22 #define CONFIG_ENV_OVERWRITE 23 24 /* Boot configuration */ 25 #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ 26 27 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 28 29 #define CONFIG_NR_DRAM_BANKS 1 30 31 #define CONFIG_SYS_MALLOC_LEN 0x1400000 32 33 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 34 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 36 CONFIG_SYS_INIT_RAM_SIZE - \ 37 GENERATED_GBL_DATA_SIZE) 38 39 /* Extend size of kernel image for uncompression */ 40 #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) 41 42 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 43 44 #define CONFIG_SKIP_LOWLEVEL_INIT 45 46 /* 0x0 - 0x40 is used for placing exception vectors */ 47 #define CONFIG_SYS_MEMTEST_START 0x40 48 #define CONFIG_SYS_MEMTEST_END 0x100 49 #define CONFIG_SYS_MEMTEST_SCRATCH 0 50 51 #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ 52