1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #ifndef IR3_SHADER_H_
30 #define IR3_SHADER_H_
31
32 #include "pipe/p_state.h"
33 #include "compiler/shader_enums.h"
34 #include "util/bitscan.h"
35
36 #include "ir3.h"
37 #include "disasm.h"
38
39 struct glsl_type;
40
41 /* driver param indices: */
42 enum ir3_driver_param {
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X = 0,
45 IR3_DP_NUM_WORK_GROUPS_Y = 1,
46 IR3_DP_NUM_WORK_GROUPS_Z = 2,
47 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
48 * glDispatchComputeIndirect() needs to load these from
49 * the info->indirect buffer. Keep that in mind when/if
50 * adding any addition CS driver params.
51 */
52 IR3_DP_CS_COUNT = 4, /* must be aligned to vec4 */
53
54 /* vertex shader driver params: */
55 IR3_DP_VTXID_BASE = 0,
56 IR3_DP_VTXCNT_MAX = 1,
57 /* user-clip-plane components, up to 8x vec4's: */
58 IR3_DP_UCP0_X = 4,
59 /* .... */
60 IR3_DP_UCP7_W = 35,
61 IR3_DP_VS_COUNT = 36 /* must be aligned to vec4 */
62 };
63
64 /**
65 * For consts needed to pass internal values to shader which may or may not
66 * be required, rather than allocating worst-case const space, we scan the
67 * shader and allocate consts as-needed:
68 *
69 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
70 * for a given SSBO
71 *
72 * + Image dimensions: needed to calculate pixel offset, but only for
73 * images that have a image_store intrinsic
74 */
75 struct ir3_driver_const_layout {
76 struct {
77 uint32_t mask; /* bitmask of SSBOs that have get_buffer_size */
78 uint32_t count; /* number of consts allocated */
79 /* one const allocated per SSBO which has get_buffer_size,
80 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
81 * consts:
82 */
83 uint32_t off[PIPE_MAX_SHADER_BUFFERS];
84 } ssbo_size;
85
86 struct {
87 uint32_t mask; /* bitmask of images that have image_store */
88 uint32_t count; /* number of consts allocated */
89 /* three const allocated per image which has image_store:
90 * + cpp (bytes per pixel)
91 * + pitch (y pitch)
92 * + array_pitch (z pitch)
93 */
94 uint32_t off[PIPE_MAX_SHADER_IMAGES];
95 } image_dims;
96 };
97
98 /* Configuration key used to identify a shader variant.. different
99 * shader variants can be used to implement features not supported
100 * in hw (two sided color), binning-pass vertex shader, etc.
101 */
102 struct ir3_shader_key {
103 union {
104 struct {
105 /*
106 * Combined Vertex/Fragment shader parameters:
107 */
108 unsigned ucp_enables : 8;
109
110 /* do we need to check {v,f}saturate_{s,t,r}? */
111 unsigned has_per_samp : 1;
112
113 /*
114 * Vertex shader variant parameters:
115 */
116 unsigned binning_pass : 1;
117 unsigned vclamp_color : 1;
118
119 /*
120 * Fragment shader variant parameters:
121 */
122 unsigned color_two_side : 1;
123 unsigned half_precision : 1;
124 /* used when shader needs to handle flat varyings (a4xx)
125 * for front/back color inputs to frag shader:
126 */
127 unsigned rasterflat : 1;
128 unsigned fclamp_color : 1;
129 };
130 uint32_t global;
131 };
132
133 /* bitmask of sampler which needs coords clamped for vertex
134 * shader:
135 */
136 uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
137
138 /* bitmask of sampler which needs coords clamped for frag
139 * shader:
140 */
141 uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
142
143 /* bitmask of samplers which need astc srgb workaround: */
144 uint16_t vastc_srgb, fastc_srgb;
145 };
146
147 static inline bool
ir3_shader_key_equal(struct ir3_shader_key * a,struct ir3_shader_key * b)148 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
149 {
150 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
151 if (a->has_per_samp || b->has_per_samp)
152 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
153 return a->global == b->global;
154 }
155
156 /* will the two keys produce different lowering for a fragment shader? */
157 static inline bool
ir3_shader_key_changes_fs(struct ir3_shader_key * key,struct ir3_shader_key * last_key)158 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
159 {
160 if (last_key->has_per_samp || key->has_per_samp) {
161 if ((last_key->fsaturate_s != key->fsaturate_s) ||
162 (last_key->fsaturate_t != key->fsaturate_t) ||
163 (last_key->fsaturate_r != key->fsaturate_r) ||
164 (last_key->fastc_srgb != key->fastc_srgb))
165 return true;
166 }
167
168 if (last_key->fclamp_color != key->fclamp_color)
169 return true;
170
171 if (last_key->color_two_side != key->color_two_side)
172 return true;
173
174 if (last_key->half_precision != key->half_precision)
175 return true;
176
177 if (last_key->rasterflat != key->rasterflat)
178 return true;
179
180 if (last_key->ucp_enables != key->ucp_enables)
181 return true;
182
183 return false;
184 }
185
186 /* will the two keys produce different lowering for a vertex shader? */
187 static inline bool
ir3_shader_key_changes_vs(struct ir3_shader_key * key,struct ir3_shader_key * last_key)188 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
189 {
190 if (last_key->has_per_samp || key->has_per_samp) {
191 if ((last_key->vsaturate_s != key->vsaturate_s) ||
192 (last_key->vsaturate_t != key->vsaturate_t) ||
193 (last_key->vsaturate_r != key->vsaturate_r) ||
194 (last_key->vastc_srgb != key->vastc_srgb))
195 return true;
196 }
197
198 if (last_key->vclamp_color != key->vclamp_color)
199 return true;
200
201 if (last_key->ucp_enables != key->ucp_enables)
202 return true;
203
204 return false;
205 }
206
207 struct ir3_shader_variant {
208 struct fd_bo *bo;
209
210 /* variant id (for debug) */
211 uint32_t id;
212
213 struct ir3_shader_key key;
214
215 struct ir3_driver_const_layout const_layout;
216 struct ir3_info info;
217 struct ir3 *ir;
218
219 /* the instructions length is in units of instruction groups
220 * (4 instructions for a3xx, 16 instructions for a4xx.. each
221 * instruction is 2 dwords):
222 */
223 unsigned instrlen;
224
225 /* the constants length is in units of vec4's, and is the sum of
226 * the uniforms and the built-in compiler constants
227 */
228 unsigned constlen;
229
230 /* number of uniforms (in vec4), not including built-in compiler
231 * constants, etc.
232 */
233 unsigned num_uniforms;
234
235 unsigned num_ubos;
236
237 /* About Linkage:
238 * + Let the frag shader determine the position/compmask for the
239 * varyings, since it is the place where we know if the varying
240 * is actually used, and if so, which components are used. So
241 * what the hw calls "outloc" is taken from the "inloc" of the
242 * frag shader.
243 * + From the vert shader, we only need the output regid
244 */
245
246 /* for frag shader, pos_regid holds the frag_pos, ie. what is passed
247 * to bary.f instructions
248 */
249 uint8_t pos_regid;
250 bool frag_coord, frag_face, color0_mrt;
251
252 /* NOTE: for input/outputs, slot is:
253 * gl_vert_attrib - for VS inputs
254 * gl_varying_slot - for VS output / FS input
255 * gl_frag_result - for FS output
256 */
257
258 /* varyings/outputs: */
259 unsigned outputs_count;
260 struct {
261 uint8_t slot;
262 uint8_t regid;
263 } outputs[16 + 2]; /* +POSITION +PSIZE */
264 bool writes_pos, writes_psize;
265
266 /* attributes (VS) / varyings (FS):
267 * Note that sysval's should come *after* normal inputs.
268 */
269 unsigned inputs_count;
270 struct {
271 uint8_t slot;
272 uint8_t regid;
273 uint8_t compmask;
274 uint8_t ncomp;
275 /* location of input (ie. offset passed to bary.f, etc). This
276 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
277 * have the OUTLOCn value offset by 8, presumably to account
278 * for gl_Position/gl_PointSize)
279 */
280 uint8_t inloc;
281 /* vertex shader specific: */
282 bool sysval : 1; /* slot is a gl_system_value */
283 /* fragment shader specific: */
284 bool bary : 1; /* fetched varying (vs one loaded into reg) */
285 bool rasterflat : 1; /* special handling for emit->rasterflat */
286 enum glsl_interp_mode interpolate;
287 } inputs[16 + 2]; /* +POSITION +FACE */
288
289 /* sum of input components (scalar). For frag shaders, it only counts
290 * the varying inputs:
291 */
292 unsigned total_in;
293
294 /* For frag shaders, the total number of inputs (not scalar,
295 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
296 */
297 unsigned varying_in;
298
299 /* do we have one or more texture sample instructions: */
300 bool has_samp;
301
302 /* do we have one or more SSBO instructions: */
303 bool has_ssbo;
304
305 /* do we have kill instructions: */
306 bool has_kill;
307
308 /* Layout of constant registers, each section (in vec4). Pointer size
309 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
310 * UBO and stream-out consts.
311 */
312 struct {
313 /* user const start at zero */
314 unsigned ubo;
315 /* NOTE that a3xx might need a section for SSBO addresses too */
316 unsigned ssbo_sizes;
317 unsigned image_dims;
318 unsigned driver_param;
319 unsigned tfbo;
320 unsigned immediate;
321 } constbase;
322
323 unsigned immediates_count;
324 struct {
325 uint32_t val[4];
326 } immediates[64];
327
328 /* for astc srgb workaround, the number/base of additional
329 * alpha tex states we need, and index of original tex states
330 */
331 struct {
332 unsigned base, count;
333 unsigned orig_idx[16];
334 } astc_srgb;
335
336 /* shader variants form a linked list: */
337 struct ir3_shader_variant *next;
338
339 /* replicated here to avoid passing extra ptrs everywhere: */
340 enum shader_t type;
341 struct ir3_shader *shader;
342 };
343
344 typedef struct nir_shader nir_shader;
345
346 struct ir3_shader {
347 enum shader_t type;
348
349 /* shader id (for debug): */
350 uint32_t id;
351 uint32_t variant_count;
352
353 /* so we know when we can disable TGSI related hacks: */
354 bool from_tgsi;
355
356 struct ir3_compiler *compiler;
357
358 nir_shader *nir;
359 struct pipe_stream_output_info stream_output;
360
361 struct ir3_shader_variant *variants;
362 };
363
364 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
365
366 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
367 const struct pipe_shader_state *cso, enum shader_t type,
368 struct pipe_debug_callback *debug);
369 struct ir3_shader *
370 ir3_shader_create_compute(struct ir3_compiler *compiler,
371 const struct pipe_compute_state *cso,
372 struct pipe_debug_callback *debug);
373 void ir3_shader_destroy(struct ir3_shader *shader);
374 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
375 struct ir3_shader_key key, struct pipe_debug_callback *debug);
376 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
377 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
378
379 struct fd_ringbuffer;
380 struct fd_context;
381 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
382 struct fd_context *ctx, const struct pipe_draw_info *info);
383 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
384 struct fd_context *ctx);
385 void ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
386 struct fd_context *ctx, const struct pipe_grid_info *info);
387
388 int
389 ir3_glsl_type_size(const struct glsl_type *type);
390
391 static inline const char *
ir3_shader_stage(struct ir3_shader * shader)392 ir3_shader_stage(struct ir3_shader *shader)
393 {
394 switch (shader->type) {
395 case SHADER_VERTEX: return "VERT";
396 case SHADER_FRAGMENT: return "FRAG";
397 case SHADER_COMPUTE: return "CL";
398 default:
399 unreachable("invalid type");
400 return NULL;
401 }
402 }
403
404 /*
405 * Helper/util:
406 */
407
408 #include "pipe/p_shader_tokens.h"
409
410 static inline int
ir3_find_output(const struct ir3_shader_variant * so,gl_varying_slot slot)411 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
412 {
413 int j;
414
415 for (j = 0; j < so->outputs_count; j++)
416 if (so->outputs[j].slot == slot)
417 return j;
418
419 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
420 * in the vertex shader.. but the fragment shader doesn't know this
421 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
422 * at link time if there is no matching OUT.BCOLOR[n], we must map
423 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
424 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
425 */
426 if (slot == VARYING_SLOT_BFC0) {
427 slot = VARYING_SLOT_COL0;
428 } else if (slot == VARYING_SLOT_BFC1) {
429 slot = VARYING_SLOT_COL1;
430 } else if (slot == VARYING_SLOT_COL0) {
431 slot = VARYING_SLOT_BFC0;
432 } else if (slot == VARYING_SLOT_COL1) {
433 slot = VARYING_SLOT_BFC1;
434 } else {
435 return 0;
436 }
437
438 for (j = 0; j < so->outputs_count; j++)
439 if (so->outputs[j].slot == slot)
440 return j;
441
442 debug_assert(0);
443
444 return 0;
445 }
446
447 static inline int
ir3_next_varying(const struct ir3_shader_variant * so,int i)448 ir3_next_varying(const struct ir3_shader_variant *so, int i)
449 {
450 while (++i < so->inputs_count)
451 if (so->inputs[i].compmask && so->inputs[i].bary)
452 break;
453 return i;
454 }
455
456 struct ir3_shader_linkage {
457 uint8_t max_loc;
458 uint8_t cnt;
459 struct {
460 uint8_t regid;
461 uint8_t compmask;
462 uint8_t loc;
463 } var[32];
464 };
465
466 static inline void
ir3_link_add(struct ir3_shader_linkage * l,uint8_t regid,uint8_t compmask,uint8_t loc)467 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
468 {
469 int i = l->cnt++;
470
471 debug_assert(i < ARRAY_SIZE(l->var));
472
473 l->var[i].regid = regid;
474 l->var[i].compmask = compmask;
475 l->var[i].loc = loc;
476 l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
477 }
478
479 static inline void
ir3_link_shaders(struct ir3_shader_linkage * l,const struct ir3_shader_variant * vs,const struct ir3_shader_variant * fs)480 ir3_link_shaders(struct ir3_shader_linkage *l,
481 const struct ir3_shader_variant *vs,
482 const struct ir3_shader_variant *fs)
483 {
484 int j = -1, k;
485
486 while (l->cnt < ARRAY_SIZE(l->var)) {
487 j = ir3_next_varying(fs, j);
488
489 if (j >= fs->inputs_count)
490 break;
491
492 if (fs->inputs[j].inloc >= fs->total_in)
493 continue;
494
495 k = ir3_find_output(vs, fs->inputs[j].slot);
496
497 ir3_link_add(l, vs->outputs[k].regid,
498 fs->inputs[j].compmask, fs->inputs[j].inloc);
499 }
500 }
501
502 static inline uint32_t
ir3_find_output_regid(const struct ir3_shader_variant * so,unsigned slot)503 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
504 {
505 int j;
506 for (j = 0; j < so->outputs_count; j++)
507 if (so->outputs[j].slot == slot)
508 return so->outputs[j].regid;
509 return regid(63, 0);
510 }
511
512 static inline uint32_t
ir3_find_sysval_regid(const struct ir3_shader_variant * so,unsigned slot)513 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
514 {
515 int j;
516 for (j = 0; j < so->inputs_count; j++)
517 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
518 return so->inputs[j].regid;
519 return regid(63, 0);
520 }
521
522 #endif /* IR3_SHADER_H_ */
523