1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gen4.h"
25 #include "isl_priv.h"
26
27 bool
isl_gen4_choose_msaa_layout(const struct isl_device * dev,const struct isl_surf_init_info * info,enum isl_tiling tiling,enum isl_msaa_layout * msaa_layout)28 isl_gen4_choose_msaa_layout(const struct isl_device *dev,
29 const struct isl_surf_init_info *info,
30 enum isl_tiling tiling,
31 enum isl_msaa_layout *msaa_layout)
32 {
33 /* Gen4 and Gen5 do not support MSAA */
34 assert(info->samples >= 1);
35
36 *msaa_layout = ISL_MSAA_LAYOUT_NONE;
37 return true;
38 }
39
40 void
isl_gen4_filter_tiling(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,isl_tiling_flags_t * flags)41 isl_gen4_filter_tiling(const struct isl_device *dev,
42 const struct isl_surf_init_info *restrict info,
43 isl_tiling_flags_t *flags)
44 {
45 /* Gen4-5 only support linear, X, and Y-tiling. */
46 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT);
47
48 if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
49 assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev));
50
51 /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
52 *
53 * "The Depth Buffer, if tiled, must use Y-Major tiling"
54 */
55 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT);
56 }
57
58 if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
59 ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
60 ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
61 assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
62 isl_finishme("%s:%s: handle rotated display surfaces",
63 __FILE__, __func__);
64 }
65
66 if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
67 ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
68 assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
69 isl_finishme("%s:%s: handle flipped display surfaces",
70 __FILE__, __func__);
71 }
72
73 if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
74 /* Before Skylake, the display engine does not accept Y */
75 *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
76 }
77
78 assert(info->samples == 1);
79
80 /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
81 *
82 * "NOTE: 128BPE Format Color buffer ( render target ) MUST be either
83 * TileX or Linear."
84 *
85 * This is required all the way up to Sandy Bridge.
86 */
87 if (isl_format_get_layout(info->format)->bpb >= 128)
88 *flags &= ~ISL_TILING_Y0_BIT;
89 }
90
91 void
isl_gen4_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)92 isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
93 const struct isl_surf_init_info *restrict info,
94 enum isl_tiling tiling,
95 enum isl_dim_layout dim_layout,
96 enum isl_msaa_layout msaa_layout,
97 struct isl_extent3d *image_align_el)
98 {
99 assert(info->samples == 1);
100 assert(msaa_layout == ISL_MSAA_LAYOUT_NONE);
101 assert(!isl_tiling_is_std_y(tiling));
102
103 /* Note that neither the surface's horizontal nor vertical image alignment
104 * is programmable on gen4 nor gen5.
105 *
106 * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4
107 * Alignment Unit Size:
108 *
109 * Note that the compressed formats are padded to a full compression
110 * cell.
111 *
112 * +------------------------+--------+--------+
113 * | format | halign | valign |
114 * +------------------------+--------+--------+
115 * | YUV 4:2:2 formats | 4 | 2 |
116 * | uncompressed formats | 4 | 2 |
117 * +------------------------+--------+--------+
118 */
119
120 if (isl_format_is_compressed(info->format)) {
121 *image_align_el = isl_extent3d(1, 1, 1);
122 return;
123 }
124
125 *image_align_el = isl_extent3d(4, 2, 1);
126 }
127