1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
31 {
32 return addr + delta;
33 }
34
35 #include "genxml/gen_macros.h"
36 #include "genxml/genX_pack.h"
37
38 #include "isl_priv.h"
39
40 #if GEN_GEN >= 8
41 static const uint8_t isl_to_gen_halign[] = {
42 [4] = HALIGN4,
43 [8] = HALIGN8,
44 [16] = HALIGN16,
45 };
46 #elif GEN_GEN >= 7
47 static const uint8_t isl_to_gen_halign[] = {
48 [4] = HALIGN_4,
49 [8] = HALIGN_8,
50 };
51 #endif
52
53 #if GEN_GEN >= 8
54 static const uint8_t isl_to_gen_valign[] = {
55 [4] = VALIGN4,
56 [8] = VALIGN8,
57 [16] = VALIGN16,
58 };
59 #elif GEN_GEN >= 6
60 static const uint8_t isl_to_gen_valign[] = {
61 [2] = VALIGN_2,
62 [4] = VALIGN_4,
63 };
64 #endif
65
66 #if GEN_GEN >= 8
67 static const uint8_t isl_to_gen_tiling[] = {
68 [ISL_TILING_LINEAR] = LINEAR,
69 [ISL_TILING_X] = XMAJOR,
70 [ISL_TILING_Y0] = YMAJOR,
71 [ISL_TILING_Yf] = YMAJOR,
72 [ISL_TILING_Ys] = YMAJOR,
73 [ISL_TILING_W] = WMAJOR,
74 };
75 #endif
76
77 #if GEN_GEN >= 7
78 static const uint32_t isl_to_gen_multisample_layout[] = {
79 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
80 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL,
81 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS,
82 };
83 #endif
84
85 #if GEN_GEN >= 9
86 static const uint32_t isl_to_gen_aux_mode[] = {
87 [ISL_AUX_USAGE_NONE] = AUX_NONE,
88 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
89 [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
90 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
91 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
92 };
93 #elif GEN_GEN >= 8
94 static const uint32_t isl_to_gen_aux_mode[] = {
95 [ISL_AUX_USAGE_NONE] = AUX_NONE,
96 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
97 [ISL_AUX_USAGE_MCS] = AUX_MCS,
98 [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
99 };
100 #endif
101
102 static uint8_t
get_surftype(enum isl_surf_dim dim,isl_surf_usage_flags_t usage)103 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
104 {
105 switch (dim) {
106 default:
107 unreachable("bad isl_surf_dim");
108 case ISL_SURF_DIM_1D:
109 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
110 return SURFTYPE_1D;
111 case ISL_SURF_DIM_2D:
112 if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
113 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
114 /* We need SURFTYPE_CUBE to make cube sampling work */
115 return SURFTYPE_CUBE;
116 } else {
117 /* Everything else (render and storage) treat cubes as plain
118 * 2D array textures
119 */
120 return SURFTYPE_2D;
121 }
122 case ISL_SURF_DIM_3D:
123 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
124 return SURFTYPE_3D;
125 }
126 }
127
128 /**
129 * Get the horizontal and vertical alignment in the units expected by the
130 * hardware. Note that this does NOT give you the actual hardware enum values
131 * but an index into the isl_to_gen_[hv]align arrays above.
132 */
133 UNUSED static struct isl_extent3d
get_image_alignment(const struct isl_surf * surf)134 get_image_alignment(const struct isl_surf *surf)
135 {
136 if (GEN_GEN >= 9) {
137 if (isl_tiling_is_std_y(surf->tiling) ||
138 surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
139 /* The hardware ignores the alignment values. Anyway, the surface's
140 * true alignment is likely outside the enum range of HALIGN* and
141 * VALIGN*.
142 */
143 return isl_extent3d(4, 4, 1);
144 } else {
145 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
146 * of surface elements (not pixels nor samples). For compressed formats,
147 * a "surface element" is defined as a compression block. For example,
148 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
149 * format (ETC2 has a block height of 4), then the vertical alignment is
150 * 4 compression blocks or, equivalently, 16 pixels.
151 */
152 return isl_surf_get_image_alignment_el(surf);
153 }
154 } else {
155 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
156 * units of surface samples. For example, if SurfaceVerticalAlignment
157 * is VALIGN_4 and the surface is singlesampled, then for any surface
158 * format (compressed or not) the vertical alignment is
159 * 4 pixels.
160 */
161 return isl_surf_get_image_alignment_sa(surf);
162 }
163 }
164
165 #if GEN_GEN >= 8
166 static uint32_t
get_qpitch(const struct isl_surf * surf)167 get_qpitch(const struct isl_surf *surf)
168 {
169 switch (surf->dim_layout) {
170 default:
171 unreachable("Bad isl_surf_dim");
172 case ISL_DIM_LAYOUT_GEN4_2D:
173 if (GEN_GEN >= 9) {
174 if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
175 /* This is rather annoying and completely undocumented. It
176 * appears that the hardware has a bug (or undocumented feature)
177 * regarding stencil buffers most likely related to the way
178 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
179 * stencil buffer normally, and use texelFetch on it, the z or
180 * array index will get implicitly multiplied by 2 for no obvious
181 * reason. The fix appears to be to divide qpitch by 2 for
182 * W-tiled surfaces.
183 */
184 return isl_surf_get_array_pitch_el_rows(surf) / 2;
185 } else {
186 return isl_surf_get_array_pitch_el_rows(surf);
187 }
188 } else {
189 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
190 *
191 * "This field must be set to an integer multiple of the Surface
192 * Vertical Alignment. For compressed textures (BC*, FXT1,
193 * ETC*, and EAC* Surface Formats), this field is in units of
194 * rows in the uncompressed surface, and must be set to an
195 * integer multiple of the vertical alignment parameter "j"
196 * defined in the Common Surface Formats section."
197 */
198 return isl_surf_get_array_pitch_sa_rows(surf);
199 }
200 case ISL_DIM_LAYOUT_GEN9_1D:
201 /* QPitch is usually expressed as rows of surface elements (where
202 * a surface element is an compression block or a single surface
203 * sample). Skylake 1D is an outlier.
204 *
205 * From the Skylake BSpec >> Memory Views >> Common Surface
206 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
207 *
208 * Surface QPitch specifies the distance in pixels between array
209 * slices.
210 */
211 return isl_surf_get_array_pitch_el(surf);
212 case ISL_DIM_LAYOUT_GEN4_3D:
213 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
214 * different pitch at each LOD. Also, the QPitch field is ignored for
215 * these surfaces. From the Broadwell PRM documentation for QPitch:
216 *
217 * This field specifies the distance in rows between array slices. It
218 * is used only in the following cases:
219 * - Surface Array is enabled OR
220 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
221 * Surface Storage Format set to MSFMT_MSS OR
222 * - Surface Type is SURFTYPE_CUBE
223 *
224 * None of the three conditions above can possibly apply to a 3D surface
225 * so it is safe to just set QPitch to 0.
226 */
227 return 0;
228 }
229 }
230 #endif /* GEN_GEN >= 8 */
231
232 void
isl_genX(surf_fill_state_s)233 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
234 const struct isl_surf_fill_state_info *restrict info)
235 {
236 struct GENX(RENDER_SURFACE_STATE) s = { 0 };
237
238 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
239
240 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
241 assert(isl_format_supports_rendering(dev->info, info->view->format));
242 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
243 assert(isl_format_supports_sampling(dev->info, info->view->format));
244
245 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
246 *
247 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
248 * format if the Surface Type is SURFTYPE_1D
249 */
250 if (info->surf->dim == ISL_SURF_DIM_1D)
251 assert(!isl_format_is_compressed(info->view->format));
252
253 if (isl_format_is_compressed(info->surf->format)) {
254 /* You're not allowed to make a view of a compressed format with any
255 * format other than the surface format. None of the userspace APIs
256 * allow for this directly and doing so would mess up a number of
257 * surface parameters such as Width, Height, and alignments. Ideally,
258 * we'd like to assert that the two formats match. However, we have an
259 * S3TC workaround that requires us to do reinterpretation. So assert
260 * that they're at least the same bpb and block size.
261 */
262 MAYBE_UNUSED const struct isl_format_layout *surf_fmtl =
263 isl_format_get_layout(info->surf->format);
264 MAYBE_UNUSED const struct isl_format_layout *view_fmtl =
265 isl_format_get_layout(info->surf->format);
266 assert(surf_fmtl->bpb == view_fmtl->bpb);
267 assert(surf_fmtl->bw == view_fmtl->bw);
268 assert(surf_fmtl->bh == view_fmtl->bh);
269 }
270
271 s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->view->format;
272
273 #if GEN_GEN <= 5
274 s.ColorBufferComponentWriteDisables = info->write_disables;
275 #else
276 assert(info->write_disables == 0);
277 #endif
278
279 #if GEN_IS_HASWELL
280 s.IntegerSurfaceFormat =
281 isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
282 #endif
283
284 assert(info->surf->logical_level0_px.width > 0 &&
285 info->surf->logical_level0_px.height > 0);
286
287 s.Width = info->surf->logical_level0_px.width - 1;
288 s.Height = info->surf->logical_level0_px.height - 1;
289
290 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
291 * (Surface Arrays For all surfaces other than separate stencil buffer):
292 *
293 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
294 * calculated in the equation above , for every other odd Surface Height
295 * starting from 1 i.e. 1,5,9,13"
296 *
297 * Since this Qpitch errata only impacts the sampler, we have to adjust the
298 * input for the rendering surface to achieve the same qpitch. For the
299 * affected heights, we increment the height by 1 for the rendering
300 * surface.
301 */
302 if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
303 info->surf->samples > 1 &&
304 (info->surf->logical_level0_px.height % 4) == 1)
305 s.Height++;
306
307 switch (s.SurfaceType) {
308 case SURFTYPE_1D:
309 case SURFTYPE_2D:
310 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
311 *
312 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
313 * must be set to zero if this surface is used with sampling engine
314 * messages."
315 *
316 * This restriction appears to exist only on Ivy Bridge.
317 */
318 if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
319 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
320 info->surf->samples > 1)
321 assert(info->view->base_array_layer == 0);
322
323 s.MinimumArrayElement = info->view->base_array_layer;
324
325 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
326 *
327 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
328 * by one for each increase from zero of Minimum Array Element. For
329 * example, if Minimum Array Element is set to 1024 on a 2D surface,
330 * the range of this field is reduced to [0,1023].
331 *
332 * In other words, 'Depth' is the number of array layers.
333 */
334 s.Depth = info->view->array_len - 1;
335
336 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
337 *
338 * For Render Target and Typed Dataport 1D and 2D Surfaces:
339 * This field must be set to the same value as the Depth field.
340 */
341 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
342 ISL_SURF_USAGE_STORAGE_BIT))
343 s.RenderTargetViewExtent = s.Depth;
344 break;
345 case SURFTYPE_CUBE:
346 s.MinimumArrayElement = info->view->base_array_layer;
347 /* Same as SURFTYPE_2D, but divided by 6 */
348 s.Depth = info->view->array_len / 6 - 1;
349 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
350 ISL_SURF_USAGE_STORAGE_BIT))
351 s.RenderTargetViewExtent = s.Depth;
352 break;
353 case SURFTYPE_3D:
354 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
355 *
356 * If the volume texture is MIP-mapped, this field specifies the
357 * depth of the base MIP level.
358 */
359 s.Depth = info->surf->logical_level0_px.depth - 1;
360
361 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
362 *
363 * For Render Target and Typed Dataport 3D Surfaces: This field
364 * indicates the extent of the accessible 'R' coordinates minus 1 on
365 * the LOD currently being rendered to.
366 *
367 * The docs specify that this only matters for render targets and
368 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
369 * Depth field has more bits than RenderTargetViewExtent so we can have
370 * textures with more levels than we can render to. In order to prevent
371 * assert-failures in the packing function below, we only set the field
372 * when it's actually going to be used by the hardware.
373 *
374 * Similaraly, the MinimumArrayElement field is ignored by all hardware
375 * prior to Sky Lake when texturing and we want it set to 0 anyway.
376 * Since it's already initialized to 0, we can just leave it alone for
377 * texture surfaces.
378 */
379 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
380 ISL_SURF_USAGE_STORAGE_BIT)) {
381 s.MinimumArrayElement = info->view->base_array_layer;
382 s.RenderTargetViewExtent = info->view->array_len - 1;
383 }
384 break;
385 default:
386 unreachable("bad SurfaceType");
387 }
388
389 #if GEN_GEN >= 7
390 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
391 #endif
392
393 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
394 /* For render target surfaces, the hardware interprets field
395 * MIPCount/LOD as LOD. The Broadwell PRM says:
396 *
397 * MIPCountLOD defines the LOD that will be rendered into.
398 * SurfaceMinLOD is ignored.
399 */
400 s.MIPCountLOD = info->view->base_level;
401 s.SurfaceMinLOD = 0;
402 } else {
403 /* For non render target surfaces, the hardware interprets field
404 * MIPCount/LOD as MIPCount. The range of levels accessible by the
405 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
406 */
407 s.SurfaceMinLOD = info->view->base_level;
408 s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
409 }
410
411 #if GEN_GEN >= 9
412 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
413 * Start LOD" to 15 to prevent the hardware from trying to use them.
414 */
415 s.TiledResourceMode = NONE;
416 s.MipTailStartLOD = 15;
417 #endif
418
419 #if GEN_GEN >= 6
420 const struct isl_extent3d image_align = get_image_alignment(info->surf);
421 s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
422 #if GEN_GEN >= 7
423 s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
424 #endif
425 #endif
426
427 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
428 /* For gen9 1-D textures, surface pitch is ignored */
429 s.SurfacePitch = 0;
430 } else {
431 s.SurfacePitch = info->surf->row_pitch - 1;
432 }
433
434 #if GEN_GEN >= 8
435 s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
436 #elif GEN_GEN == 7
437 s.SurfaceArraySpacing = info->surf->array_pitch_span ==
438 ISL_ARRAY_PITCH_SPAN_COMPACT;
439 #endif
440
441 #if GEN_GEN >= 8
442 s.TileMode = isl_to_gen_tiling[info->surf->tiling];
443 #else
444 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
445 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
446 TILEWALK_XMAJOR,
447 #endif
448
449 #if GEN_GEN >= 8
450 s.RenderCacheReadWriteMode = WriteOnlyCache;
451 #else
452 s.RenderCacheReadWriteMode = 0;
453 #endif
454
455 s.CubeFaceEnablePositiveZ = 1;
456 s.CubeFaceEnableNegativeZ = 1;
457 s.CubeFaceEnablePositiveY = 1;
458 s.CubeFaceEnableNegativeY = 1;
459 s.CubeFaceEnablePositiveX = 1;
460 s.CubeFaceEnableNegativeX = 1;
461
462 #if GEN_GEN >= 6
463 s.NumberofMultisamples = ffs(info->surf->samples) - 1;
464 #if GEN_GEN >= 7
465 s.MultisampledSurfaceStorageFormat =
466 isl_to_gen_multisample_layout[info->surf->msaa_layout];
467 #endif
468 #endif
469
470 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
471 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
472 /* From the Sky Lake PRM Vol. 2d,
473 * RENDER_SURFACE_STATE::Shader Channel Select Red
474 *
475 * "For Render Target, Red, Green and Blue Shader Channel Selects
476 * MUST be such that only valid components can be swapped i.e. only
477 * change the order of components in the pixel. Any other values for
478 * these Shader Channel Select fields are not valid for Render
479 * Targets. This also means that there MUST not be multiple shader
480 * channels mapped to the same RT channel."
481 */
482 assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
483 info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
484 info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
485 assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
486 info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
487 info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
488 assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
489 info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
490 info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
491 assert(info->view->swizzle.r != info->view->swizzle.g);
492 assert(info->view->swizzle.r != info->view->swizzle.b);
493 assert(info->view->swizzle.g != info->view->swizzle.b);
494
495 /* From the Sky Lake PRM Vol. 2d,
496 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
497 *
498 * "For Render Target, this field MUST be programmed to
499 * value = SCS_ALPHA."
500 */
501 assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
502 }
503 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
504 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
505 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
506 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
507 #endif
508
509 s.SurfaceBaseAddress = info->address;
510
511 #if GEN_GEN >= 6
512 s.MOCS = info->mocs;
513 #endif
514
515 #if GEN_GEN > 4 || GEN_IS_G4X
516 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
517 /* There are fairly strict rules about when the offsets can be used.
518 * These are mostly taken from the Sky Lake PRM documentation for
519 * RENDER_SURFACE_STATE.
520 */
521 assert(info->surf->tiling != ISL_TILING_LINEAR);
522 assert(info->surf->dim == ISL_SURF_DIM_2D);
523 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
524 assert(info->surf->levels == 1);
525 assert(info->surf->logical_level0_px.array_len == 1);
526 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
527
528 if (GEN_GEN >= 8) {
529 /* Broadwell added more rules. */
530 assert(info->surf->samples == 1);
531 if (isl_format_get_layout(info->view->format)->bpb == 8)
532 assert(info->x_offset_sa % 16 == 0);
533 if (isl_format_get_layout(info->view->format)->bpb == 16)
534 assert(info->x_offset_sa % 8 == 0);
535 }
536
537 #if GEN_GEN >= 7
538 s.SurfaceArray = false;
539 #endif
540 }
541
542 const unsigned x_div = 4;
543 const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
544 assert(info->x_offset_sa % x_div == 0);
545 assert(info->y_offset_sa % y_div == 0);
546 s.XOffset = info->x_offset_sa / x_div;
547 s.YOffset = info->y_offset_sa / y_div;
548 #else
549 assert(info->x_offset_sa == 0);
550 assert(info->y_offset_sa == 0);
551 #endif
552
553 #if GEN_GEN >= 7
554 if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
555 /* The docs don't appear to say anything whatsoever about compression
556 * and the data port. Testing seems to indicate that the data port
557 * completely ignores the AuxiliarySurfaceMode field.
558 */
559 assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
560
561 struct isl_tile_info tile_info;
562 isl_surf_get_tile_info(info->aux_surf, &tile_info);
563 uint32_t pitch_in_tiles =
564 info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
565
566 s.AuxiliarySurfaceBaseAddress = info->aux_address;
567 s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
568
569 #if GEN_GEN >= 8
570 assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
571 /* Auxiliary surfaces in ISL have compressed formats but the hardware
572 * doesn't expect our definition of the compression, it expects qpitch
573 * in units of samples on the main surface.
574 */
575 s.AuxiliarySurfaceQPitch =
576 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
577
578 if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
579 /* The number of samples must be 1 */
580 assert(info->surf->samples == 1);
581
582 /* The dimension must not be 3D */
583 assert(info->surf->dim != ISL_SURF_DIM_3D);
584
585 /* The format must be one of the following: */
586 switch (info->view->format) {
587 case ISL_FORMAT_R32_FLOAT:
588 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
589 case ISL_FORMAT_R16_UNORM:
590 break;
591 default:
592 assert(!"Incompatible HiZ Sampling format");
593 break;
594 }
595 }
596
597 s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
598 #else
599 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
600 info->aux_usage == ISL_AUX_USAGE_CCS_D);
601 s.MCSEnable = true;
602 #endif
603 }
604 #endif
605
606 #if GEN_GEN >= 8
607 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
608 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
609 *
610 * This bit must be set for the following surface types: BC2_UNORM
611 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
612 */
613 if (GEN_GEN >= 9 || dev->info->is_cherryview) {
614 switch (info->view->format) {
615 case ISL_FORMAT_BC2_UNORM:
616 case ISL_FORMAT_BC3_UNORM:
617 case ISL_FORMAT_BC5_UNORM:
618 case ISL_FORMAT_BC5_SNORM:
619 case ISL_FORMAT_BC7_UNORM:
620 s.SamplerL2BypassModeDisable = true;
621 break;
622 default:
623 /* From the SKL PRM, Programming Note under Sampler Output Channel
624 * Mapping:
625 *
626 * If a surface has an associated HiZ Auxilliary surface, the
627 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
628 * must be set.
629 */
630 if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
631 s.SamplerL2BypassModeDisable = true;
632 break;
633 }
634 }
635 #endif
636
637 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
638 #if GEN_GEN >= 9
639 s.RedClearColor = info->clear_color.u32[0];
640 s.GreenClearColor = info->clear_color.u32[1];
641 s.BlueClearColor = info->clear_color.u32[2];
642 s.AlphaClearColor = info->clear_color.u32[3];
643 #elif GEN_GEN >= 7
644 /* Prior to Sky Lake, we only have one bit for the clear color which
645 * gives us 0 or 1 in whatever the surface's format happens to be.
646 */
647 if (isl_format_has_int_channel(info->view->format)) {
648 for (unsigned i = 0; i < 4; i++) {
649 assert(info->clear_color.u32[i] == 0 ||
650 info->clear_color.u32[i] == 1);
651 }
652 s.RedClearColor = info->clear_color.u32[0] != 0;
653 s.GreenClearColor = info->clear_color.u32[1] != 0;
654 s.BlueClearColor = info->clear_color.u32[2] != 0;
655 s.AlphaClearColor = info->clear_color.u32[3] != 0;
656 } else {
657 for (unsigned i = 0; i < 4; i++) {
658 assert(info->clear_color.f32[i] == 0.0f ||
659 info->clear_color.f32[i] == 1.0f);
660 }
661 s.RedClearColor = info->clear_color.f32[0] != 0.0f;
662 s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
663 s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
664 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
665 }
666 #endif
667 }
668
669 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
670 }
671
672 void
isl_genX(buffer_fill_state_s)673 isl_genX(buffer_fill_state_s)(void *state,
674 const struct isl_buffer_fill_state_info *restrict info)
675 {
676 uint32_t num_elements = info->size / info->stride;
677
678 if (GEN_GEN >= 7) {
679 /* From the IVB PRM, SURFACE_STATE::Height,
680 *
681 * For typed buffer and structured buffer surfaces, the number
682 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
683 * surfaces, the number of entries in the buffer is the number of bytes
684 * which can range from 1 to 2^30.
685 */
686 if (info->format == ISL_FORMAT_RAW) {
687 assert(num_elements <= (1ull << 30));
688 assert(num_elements > 0);
689 } else {
690 assert(num_elements <= (1ull << 27));
691 }
692 } else {
693 assert(num_elements <= (1ull << 27));
694 }
695
696 struct GENX(RENDER_SURFACE_STATE) s = { 0, };
697
698 s.SurfaceType = SURFTYPE_BUFFER;
699 s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->format;
700
701 #if GEN_GEN >= 6
702 s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
703 #if GEN_GEN >= 7
704 s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
705 s.SurfaceArray = false;
706 #endif
707 #endif
708
709 #if GEN_GEN >= 7
710 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
711 s.Width = (num_elements - 1) & 0x7f;
712 s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
713 #else
714 s.Height = ((num_elements - 1) >> 7) & 0x1fff;
715 s.Width = (num_elements - 1) & 0x7f;
716 s.Depth = ((num_elements - 1) >> 20) & 0x7f;
717 #endif
718
719 s.SurfacePitch = info->stride - 1;
720
721 #if GEN_GEN >= 6
722 s.NumberofMultisamples = MULTISAMPLECOUNT_1;
723 #endif
724
725 #if (GEN_GEN >= 8)
726 s.TileMode = LINEAR;
727 #else
728 s.TiledSurface = false;
729 #endif
730
731 #if (GEN_GEN >= 8)
732 s.RenderCacheReadWriteMode = WriteOnlyCache;
733 #else
734 s.RenderCacheReadWriteMode = 0;
735 #endif
736
737 s.SurfaceBaseAddress = info->address;
738 #if GEN_GEN >= 6
739 s.MOCS = info->mocs;
740 #endif
741
742 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
743 s.ShaderChannelSelectRed = SCS_RED;
744 s.ShaderChannelSelectGreen = SCS_GREEN;
745 s.ShaderChannelSelectBlue = SCS_BLUE;
746 s.ShaderChannelSelectAlpha = SCS_ALPHA;
747 #endif
748
749 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
750 }
751
752 void
isl_genX(null_fill_state)753 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
754 {
755 struct GENX(RENDER_SURFACE_STATE) s = {
756 .SurfaceType = SURFTYPE_NULL,
757 .SurfaceFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_B8G8R8A8_UNORM,
758 #if GEN_GEN >= 7
759 .SurfaceArray = size.depth > 0,
760 #endif
761 #if GEN_GEN >= 8
762 .TileMode = YMAJOR,
763 #else
764 .TiledSurface = true,
765 .TileWalk = TILEWALK_YMAJOR,
766 #endif
767 .Width = size.width - 1,
768 .Height = size.height - 1,
769 .Depth = size.depth - 1,
770 .RenderTargetViewExtent = size.depth - 1,
771 #if GEN_GEN <= 5
772 .ColorBufferComponentWriteDisables = 0xf,
773 #endif
774 };
775 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
776 }
777