1/* 2 * Copyright 2013-2014 Texas Instruments, Inc. 3 * 4 * Keystone 2 Kepler/Hawking SoC clock nodes 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11clocks { 12 armpllclk: armpllclk@2620370 { 13 #clock-cells = <0>; 14 compatible = "ti,keystone,pll-clock"; 15 clocks = <&refclkarm>; 16 clock-output-names = "arm-pll-clk"; 17 reg = <0x02620370 4>; 18 reg-names = "control"; 19 }; 20 21 mainpllclk: mainpllclk@2310110 { 22 #clock-cells = <0>; 23 compatible = "ti,keystone,main-pll-clock"; 24 clocks = <&refclksys>; 25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 26 reg-names = "control", "multiplier", "post-divider"; 27 }; 28 29 papllclk: papllclk@2620358 { 30 #clock-cells = <0>; 31 compatible = "ti,keystone,pll-clock"; 32 clocks = <&refclkpass>; 33 clock-output-names = "papllclk"; 34 reg = <0x02620358 4>; 35 reg-names = "control"; 36 }; 37 38 ddr3apllclk: ddr3apllclk@2620360 { 39 #clock-cells = <0>; 40 compatible = "ti,keystone,pll-clock"; 41 clocks = <&refclkddr3a>; 42 clock-output-names = "ddr-3a-pll-clk"; 43 reg = <0x02620360 4>; 44 reg-names = "control"; 45 }; 46 47 ddr3bpllclk: ddr3bpllclk@2620368 { 48 #clock-cells = <0>; 49 compatible = "ti,keystone,pll-clock"; 50 clocks = <&refclkddr3b>; 51 clock-output-names = "ddr-3b-pll-clk"; 52 reg = <0x02620368 4>; 53 reg-names = "control"; 54 }; 55 56 clktsip: clktsip { 57 #clock-cells = <0>; 58 compatible = "ti,keystone,psc-clock"; 59 clocks = <&chipclk16>; 60 clock-output-names = "tsip"; 61 reg = <0x02350000 0xb00>, <0x02350000 0x400>; 62 reg-names = "control", "domain"; 63 domain-id = <0>; 64 }; 65 66 clksrio: clksrio { 67 #clock-cells = <0>; 68 compatible = "ti,keystone,psc-clock"; 69 clocks = <&chipclk1rstiso13>; 70 clock-output-names = "srio"; 71 reg = <0x0235002c 0xb00>, <0x02350010 0x400>; 72 reg-names = "control", "domain"; 73 domain-id = <4>; 74 }; 75 76 clkhyperlink0: clkhyperlink0 { 77 #clock-cells = <0>; 78 compatible = "ti,keystone,psc-clock"; 79 clocks = <&chipclk12>; 80 clock-output-names = "hyperlink-0"; 81 reg = <0x02350030 0xb00>, <0x02350014 0x400>; 82 reg-names = "control", "domain"; 83 domain-id = <5>; 84 }; 85 86 clkgem1: clkgem1 { 87 #clock-cells = <0>; 88 compatible = "ti,keystone,psc-clock"; 89 clocks = <&chipclk1>; 90 clock-output-names = "gem1"; 91 reg = <0x02350040 0xb00>, <0x02350024 0x400>; 92 reg-names = "control", "domain"; 93 domain-id = <9>; 94 }; 95 96 clkgem2: clkgem2 { 97 #clock-cells = <0>; 98 compatible = "ti,keystone,psc-clock"; 99 clocks = <&chipclk1>; 100 clock-output-names = "gem2"; 101 reg = <0x02350044 0xb00>, <0x02350028 0x400>; 102 reg-names = "control", "domain"; 103 domain-id = <10>; 104 }; 105 106 clkgem3: clkgem3 { 107 #clock-cells = <0>; 108 compatible = "ti,keystone,psc-clock"; 109 clocks = <&chipclk1>; 110 clock-output-names = "gem3"; 111 reg = <0x02350048 0xb00>, <0x0235002c 0x400>; 112 reg-names = "control", "domain"; 113 domain-id = <11>; 114 }; 115 116 clkgem4: clkgem4 { 117 #clock-cells = <0>; 118 compatible = "ti,keystone,psc-clock"; 119 clocks = <&chipclk1>; 120 clock-output-names = "gem4"; 121 reg = <0x0235004c 0xb00>, <0x02350030 0x400>; 122 reg-names = "control", "domain"; 123 domain-id = <12>; 124 }; 125 126 clkgem5: clkgem5 { 127 #clock-cells = <0>; 128 compatible = "ti,keystone,psc-clock"; 129 clocks = <&chipclk1>; 130 clock-output-names = "gem5"; 131 reg = <0x02350050 0xb00>, <0x02350034 0x400>; 132 reg-names = "control", "domain"; 133 domain-id = <13>; 134 }; 135 136 clkgem6: clkgem6 { 137 #clock-cells = <0>; 138 compatible = "ti,keystone,psc-clock"; 139 clocks = <&chipclk1>; 140 clock-output-names = "gem6"; 141 reg = <0x02350054 0xb00>, <0x02350038 0x400>; 142 reg-names = "control", "domain"; 143 domain-id = <14>; 144 }; 145 146 clkgem7: clkgem7 { 147 #clock-cells = <0>; 148 compatible = "ti,keystone,psc-clock"; 149 clocks = <&chipclk1>; 150 clock-output-names = "gem7"; 151 reg = <0x02350058 0xb00>, <0x0235003c 0x400>; 152 reg-names = "control", "domain"; 153 domain-id = <15>; 154 }; 155 156 clkddr31: clkddr31 { 157 #clock-cells = <0>; 158 compatible = "ti,keystone,psc-clock"; 159 clocks = <&chipclk13>; 160 clock-output-names = "ddr3-1"; 161 reg = <0x02350060 0xb00>, <0x02350040 0x400>; 162 reg-names = "control", "domain"; 163 domain-id = <16>; 164 }; 165 166 clktac: clktac { 167 #clock-cells = <0>; 168 compatible = "ti,keystone,psc-clock"; 169 clocks = <&chipclk13>; 170 clock-output-names = "tac"; 171 reg = <0x02350064 0xb00>, <0x02350044 0x400>; 172 reg-names = "control", "domain"; 173 domain-id = <17>; 174 }; 175 176 clkrac01: clkrac01 { 177 #clock-cells = <0>; 178 compatible = "ti,keystone,psc-clock"; 179 clocks = <&chipclk13>; 180 clock-output-names = "rac-01"; 181 reg = <0x02350068 0xb00>, <0x02350044 0x400>; 182 reg-names = "control", "domain"; 183 domain-id = <17>; 184 }; 185 186 clkrac23: clkrac23 { 187 #clock-cells = <0>; 188 compatible = "ti,keystone,psc-clock"; 189 clocks = <&chipclk13>; 190 clock-output-names = "rac-23"; 191 reg = <0x0235006c 0xb00>, <0x02350048 0x400>; 192 reg-names = "control", "domain"; 193 domain-id = <18>; 194 }; 195 196 clkfftc0: clkfftc0 { 197 #clock-cells = <0>; 198 compatible = "ti,keystone,psc-clock"; 199 clocks = <&chipclk13>; 200 clock-output-names = "fftc-0"; 201 reg = <0x02350070 0xb00>, <0x0235004c 0x400>; 202 reg-names = "control", "domain"; 203 domain-id = <19>; 204 }; 205 206 clkfftc1: clkfftc1 { 207 #clock-cells = <0>; 208 compatible = "ti,keystone,psc-clock"; 209 clocks = <&chipclk13>; 210 clock-output-names = "fftc-1"; 211 reg = <0x02350074 0xb00>, <0x0235004c 0x400>; 212 reg-names = "control", "domain"; 213 domain-id = <19>; 214 }; 215 216 clkfftc2: clkfftc2 { 217 #clock-cells = <0>; 218 compatible = "ti,keystone,psc-clock"; 219 clocks = <&chipclk13>; 220 clock-output-names = "fftc-2"; 221 reg = <0x02350078 0xb00>, <0x02350050 0x400>; 222 reg-names = "control", "domain"; 223 domain-id = <20>; 224 }; 225 226 clkfftc3: clkfftc3 { 227 #clock-cells = <0>; 228 compatible = "ti,keystone,psc-clock"; 229 clocks = <&chipclk13>; 230 clock-output-names = "fftc-3"; 231 reg = <0x0235007c 0xb00>, <0x02350050 0x400>; 232 reg-names = "control", "domain"; 233 domain-id = <20>; 234 }; 235 236 clkfftc4: clkfftc4 { 237 #clock-cells = <0>; 238 compatible = "ti,keystone,psc-clock"; 239 clocks = <&chipclk13>; 240 clock-output-names = "fftc-4"; 241 reg = <0x02350080 0xb00>, <0x02350050 0x400>; 242 reg-names = "control", "domain"; 243 domain-id = <20>; 244 }; 245 246 clkfftc5: clkfftc5 { 247 #clock-cells = <0>; 248 compatible = "ti,keystone,psc-clock"; 249 clocks = <&chipclk13>; 250 clock-output-names = "fftc-5"; 251 reg = <0x02350084 0xb00>, <0x02350050 0x400>; 252 reg-names = "control", "domain"; 253 domain-id = <20>; 254 }; 255 256 clkaif: clkaif { 257 #clock-cells = <0>; 258 compatible = "ti,keystone,psc-clock"; 259 clocks = <&chipclk13>; 260 clock-output-names = "aif"; 261 reg = <0x02350088 0xb00>, <0x02350054 0x400>; 262 reg-names = "control", "domain"; 263 domain-id = <21>; 264 }; 265 266 clktcp3d0: clktcp3d0 { 267 #clock-cells = <0>; 268 compatible = "ti,keystone,psc-clock"; 269 clocks = <&chipclk13>; 270 clock-output-names = "tcp3d-0"; 271 reg = <0x0235008c 0xb00>, <0x02350058 0x400>; 272 reg-names = "control", "domain"; 273 domain-id = <22>; 274 }; 275 276 clktcp3d1: clktcp3d1 { 277 #clock-cells = <0>; 278 compatible = "ti,keystone,psc-clock"; 279 clocks = <&chipclk13>; 280 clock-output-names = "tcp3d-1"; 281 reg = <0x02350090 0xb00>, <0x02350058 0x400>; 282 reg-names = "control", "domain"; 283 domain-id = <22>; 284 }; 285 286 clktcp3d2: clktcp3d2 { 287 #clock-cells = <0>; 288 compatible = "ti,keystone,psc-clock"; 289 clocks = <&chipclk13>; 290 clock-output-names = "tcp3d-2"; 291 reg = <0x02350094 0xb00>, <0x0235005c 0x400>; 292 reg-names = "control", "domain"; 293 domain-id = <23>; 294 }; 295 296 clktcp3d3: clktcp3d3 { 297 #clock-cells = <0>; 298 compatible = "ti,keystone,psc-clock"; 299 clocks = <&chipclk13>; 300 clock-output-names = "tcp3d-3"; 301 reg = <0x02350098 0xb00>, <0x0235005c 0x400>; 302 reg-names = "control", "domain"; 303 domain-id = <23>; 304 }; 305 306 clkvcp0: clkvcp0 { 307 #clock-cells = <0>; 308 compatible = "ti,keystone,psc-clock"; 309 clocks = <&chipclk13>; 310 clock-output-names = "vcp-0"; 311 reg = <0x0235009c 0xb00>, <0x02350060 0x400>; 312 reg-names = "control", "domain"; 313 domain-id = <24>; 314 }; 315 316 clkvcp1: clkvcp1 { 317 #clock-cells = <0>; 318 compatible = "ti,keystone,psc-clock"; 319 clocks = <&chipclk13>; 320 clock-output-names = "vcp-1"; 321 reg = <0x023500a0 0xb00>, <0x02350060 0x400>; 322 reg-names = "control", "domain"; 323 domain-id = <24>; 324 }; 325 326 clkvcp2: clkvcp2 { 327 #clock-cells = <0>; 328 compatible = "ti,keystone,psc-clock"; 329 clocks = <&chipclk13>; 330 clock-output-names = "vcp-2"; 331 reg = <0x023500a4 0xb00>, <0x02350060 0x400>; 332 reg-names = "control", "domain"; 333 domain-id = <24>; 334 }; 335 336 clkvcp3: clkvcp3 { 337 #clock-cells = <0>; 338 compatible = "ti,keystone,psc-clock"; 339 clocks = <&chipclk13>; 340 clock-output-names = "vcp-3"; 341 reg = <0x023500a8 0xb00>, <0x02350060 0x400>; 342 reg-names = "control", "domain"; 343 domain-id = <24>; 344 }; 345 346 clkvcp4: clkvcp4 { 347 #clock-cells = <0>; 348 compatible = "ti,keystone,psc-clock"; 349 clocks = <&chipclk13>; 350 clock-output-names = "vcp-4"; 351 reg = <0x023500ac 0xb00>, <0x02350064 0x400>; 352 reg-names = "control", "domain"; 353 domain-id = <25>; 354 }; 355 356 clkvcp5: clkvcp5 { 357 #clock-cells = <0>; 358 compatible = "ti,keystone,psc-clock"; 359 clocks = <&chipclk13>; 360 clock-output-names = "vcp-5"; 361 reg = <0x023500b0 0xb00>, <0x02350064 0x400>; 362 reg-names = "control", "domain"; 363 domain-id = <25>; 364 }; 365 366 clkvcp6: clkvcp6 { 367 #clock-cells = <0>; 368 compatible = "ti,keystone,psc-clock"; 369 clocks = <&chipclk13>; 370 clock-output-names = "vcp-6"; 371 reg = <0x023500b4 0xb00>, <0x02350064 0x400>; 372 reg-names = "control", "domain"; 373 domain-id = <25>; 374 }; 375 376 clkvcp7: clkvcp7 { 377 #clock-cells = <0>; 378 compatible = "ti,keystone,psc-clock"; 379 clocks = <&chipclk13>; 380 clock-output-names = "vcp-7"; 381 reg = <0x023500b8 0xb00>, <0x02350064 0x400>; 382 reg-names = "control", "domain"; 383 domain-id = <25>; 384 }; 385 386 clkbcp: clkbcp { 387 #clock-cells = <0>; 388 compatible = "ti,keystone,psc-clock"; 389 clocks = <&chipclk13>; 390 clock-output-names = "bcp"; 391 reg = <0x023500bc 0xb00>, <0x02350068 0x400>; 392 reg-names = "control", "domain"; 393 domain-id = <26>; 394 }; 395 396 clkdxb: clkdxb { 397 #clock-cells = <0>; 398 compatible = "ti,keystone,psc-clock"; 399 clocks = <&chipclk13>; 400 clock-output-names = "dxb"; 401 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; 402 reg-names = "control", "domain"; 403 domain-id = <27>; 404 }; 405 406 clkhyperlink1: clkhyperlink1 { 407 #clock-cells = <0>; 408 compatible = "ti,keystone,psc-clock"; 409 clocks = <&chipclk12>; 410 clock-output-names = "hyperlink-1"; 411 reg = <0x023500c4 0xb00>, <0x02350070 0x400>; 412 reg-names = "control", "domain"; 413 domain-id = <28>; 414 }; 415 416 clkxge: clkxge { 417 #clock-cells = <0>; 418 compatible = "ti,keystone,psc-clock"; 419 clocks = <&chipclk13>; 420 clock-output-names = "xge"; 421 reg = <0x023500c8 0xb00>, <0x02350074 0x400>; 422 reg-names = "control", "domain"; 423 domain-id = <29>; 424 }; 425}; 426