1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cortex_a35.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* --------------------------------------------- 15 * Disable L1 data cache and unified L2 cache 16 * --------------------------------------------- 17 */ 18func cortex_a35_disable_dcache 19 mrs x1, sctlr_el3 20 bic x1, x1, #SCTLR_C_BIT 21 msr sctlr_el3, x1 22 isb 23 ret 24endfunc cortex_a35_disable_dcache 25 26 /* --------------------------------------------- 27 * Disable intra-cluster coherency 28 * --------------------------------------------- 29 */ 30func cortex_a35_disable_smp 31 mrs x0, CORTEX_A35_CPUECTLR_EL1 32 bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT 33 msr CORTEX_A35_CPUECTLR_EL1, x0 34 isb 35 dsb sy 36 ret 37endfunc cortex_a35_disable_smp 38 39 /* ------------------------------------------------- 40 * The CPU Ops reset function for Cortex-A35. 41 * Clobbers: x0 42 * ------------------------------------------------- 43 */ 44func cortex_a35_reset_func 45 /* --------------------------------------------- 46 * Enable the SMP bit. 47 * --------------------------------------------- 48 */ 49 mrs x0, CORTEX_A35_CPUECTLR_EL1 50 orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT 51 msr CORTEX_A35_CPUECTLR_EL1, x0 52 isb 53 ret 54endfunc cortex_a35_reset_func 55 56func cortex_a35_core_pwr_dwn 57 mov x18, x30 58 59 /* --------------------------------------------- 60 * Turn off caches. 61 * --------------------------------------------- 62 */ 63 bl cortex_a35_disable_dcache 64 65 /* --------------------------------------------- 66 * Flush L1 caches. 67 * --------------------------------------------- 68 */ 69 mov x0, #DCCISW 70 bl dcsw_op_level1 71 72 /* --------------------------------------------- 73 * Come out of intra cluster coherency 74 * --------------------------------------------- 75 */ 76 mov x30, x18 77 b cortex_a35_disable_smp 78endfunc cortex_a35_core_pwr_dwn 79 80func cortex_a35_cluster_pwr_dwn 81 mov x18, x30 82 83 /* --------------------------------------------- 84 * Turn off caches. 85 * --------------------------------------------- 86 */ 87 bl cortex_a35_disable_dcache 88 89 /* --------------------------------------------- 90 * Flush L1 caches. 91 * --------------------------------------------- 92 */ 93 mov x0, #DCCISW 94 bl dcsw_op_level1 95 96 /* --------------------------------------------- 97 * Disable the optional ACP. 98 * --------------------------------------------- 99 */ 100 bl plat_disable_acp 101 102 /* --------------------------------------------- 103 * Flush L2 caches. 104 * --------------------------------------------- 105 */ 106 mov x0, #DCCISW 107 bl dcsw_op_level2 108 109 /* --------------------------------------------- 110 * Come out of intra cluster coherency 111 * --------------------------------------------- 112 */ 113 mov x30, x18 114 b cortex_a35_disable_smp 115endfunc cortex_a35_cluster_pwr_dwn 116 117 /* --------------------------------------------- 118 * This function provides cortex_a35 specific 119 * register information for crash reporting. 120 * It needs to return with x6 pointing to 121 * a list of register names in ascii and 122 * x8 - x15 having values of registers to be 123 * reported. 124 * --------------------------------------------- 125 */ 126.section .rodata.cortex_a35_regs, "aS" 127cortex_a35_regs: /* The ascii list of register names to be reported */ 128 .asciz "cpuectlr_el1", "" 129 130func cortex_a35_cpu_reg_dump 131 adr x6, cortex_a35_regs 132 mrs x8, CORTEX_A35_CPUECTLR_EL1 133 ret 134endfunc cortex_a35_cpu_reg_dump 135 136declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 137 cortex_a35_reset_func, \ 138 cortex_a35_core_pwr_dwn, \ 139 cortex_a35_cluster_pwr_dwn 140