1/* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100 /* ------------------------------------------------- 101 * The CPU Ops reset function for Cortex-A72. 102 * ------------------------------------------------- 103 */ 104func cortex_a72_reset_func 105 mov x19, x30 106 bl cpu_get_rev_var 107 mov x18, x0 108 109#if ERRATA_A72_859971 110 mov x0, x18 111 bl errata_a72_859971_wa 112#endif 113 /* --------------------------------------------- 114 * Enable the SMP bit. 115 * --------------------------------------------- 116 */ 117 mrs x0, CORTEX_A72_ECTLR_EL1 118 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 119 msr CORTEX_A72_ECTLR_EL1, x0 120 isb 121 ret x19 122endfunc cortex_a72_reset_func 123 124 /* ---------------------------------------------------- 125 * The CPU Ops core power down function for Cortex-A72. 126 * ---------------------------------------------------- 127 */ 128func cortex_a72_core_pwr_dwn 129 mov x18, x30 130 131 /* --------------------------------------------- 132 * Turn off caches. 133 * --------------------------------------------- 134 */ 135 bl cortex_a72_disable_dcache 136 137 /* --------------------------------------------- 138 * Disable the L2 prefetches. 139 * --------------------------------------------- 140 */ 141 bl cortex_a72_disable_l2_prefetch 142 143 /* --------------------------------------------- 144 * Disable the load-store hardware prefetcher. 145 * --------------------------------------------- 146 */ 147 bl cortex_a72_disable_hw_prefetcher 148 149 /* --------------------------------------------- 150 * Flush L1 caches. 151 * --------------------------------------------- 152 */ 153 mov x0, #DCCISW 154 bl dcsw_op_level1 155 156 /* --------------------------------------------- 157 * Come out of intra cluster coherency 158 * --------------------------------------------- 159 */ 160 bl cortex_a72_disable_smp 161 162 /* --------------------------------------------- 163 * Force the debug interfaces to be quiescent 164 * --------------------------------------------- 165 */ 166 mov x30, x18 167 b cortex_a72_disable_ext_debug 168endfunc cortex_a72_core_pwr_dwn 169 170 /* ------------------------------------------------------- 171 * The CPU Ops cluster power down function for Cortex-A72. 172 * ------------------------------------------------------- 173 */ 174func cortex_a72_cluster_pwr_dwn 175 mov x18, x30 176 177 /* --------------------------------------------- 178 * Turn off caches. 179 * --------------------------------------------- 180 */ 181 bl cortex_a72_disable_dcache 182 183 /* --------------------------------------------- 184 * Disable the L2 prefetches. 185 * --------------------------------------------- 186 */ 187 bl cortex_a72_disable_l2_prefetch 188 189 /* --------------------------------------------- 190 * Disable the load-store hardware prefetcher. 191 * --------------------------------------------- 192 */ 193 bl cortex_a72_disable_hw_prefetcher 194 195#if !SKIP_A72_L1_FLUSH_PWR_DWN 196 /* --------------------------------------------- 197 * Flush L1 caches. 198 * --------------------------------------------- 199 */ 200 mov x0, #DCCISW 201 bl dcsw_op_level1 202#endif 203 204 /* --------------------------------------------- 205 * Disable the optional ACP. 206 * --------------------------------------------- 207 */ 208 bl plat_disable_acp 209 210 /* ------------------------------------------------- 211 * Flush the L2 caches. 212 * ------------------------------------------------- 213 */ 214 mov x0, #DCCISW 215 bl dcsw_op_level2 216 217 /* --------------------------------------------- 218 * Come out of intra cluster coherency 219 * --------------------------------------------- 220 */ 221 bl cortex_a72_disable_smp 222 223 /* --------------------------------------------- 224 * Force the debug interfaces to be quiescent 225 * --------------------------------------------- 226 */ 227 mov x30, x18 228 b cortex_a72_disable_ext_debug 229endfunc cortex_a72_cluster_pwr_dwn 230 231#if REPORT_ERRATA 232/* 233 * Errata printing function for Cortex A72. Must follow AAPCS. 234 */ 235func cortex_a72_errata_report 236 stp x8, x30, [sp, #-16]! 237 238 bl cpu_get_rev_var 239 mov x8, x0 240 241 /* 242 * Report all errata. The revision-variant information is passed to 243 * checking functions of each errata. 244 */ 245 report_errata ERRATA_A72_859971, cortex_a72, 859971 246 247 ldp x8, x30, [sp], #16 248 ret 249endfunc cortex_a72_errata_report 250#endif 251 252 /* --------------------------------------------- 253 * This function provides cortex_a72 specific 254 * register information for crash reporting. 255 * It needs to return with x6 pointing to 256 * a list of register names in ascii and 257 * x8 - x15 having values of registers to be 258 * reported. 259 * --------------------------------------------- 260 */ 261.section .rodata.cortex_a72_regs, "aS" 262cortex_a72_regs: /* The ascii list of register names to be reported */ 263 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 264 265func cortex_a72_cpu_reg_dump 266 adr x6, cortex_a72_regs 267 mrs x8, CORTEX_A72_ECTLR_EL1 268 mrs x9, CORTEX_A72_MERRSR_EL1 269 mrs x10, CORTEX_A72_L2MERRSR_EL1 270 ret 271endfunc cortex_a72_cpu_reg_dump 272 273 274declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 275 cortex_a72_reset_func, \ 276 cortex_a72_core_pwr_dwn, \ 277 cortex_a72_cluster_pwr_dwn 278