1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4declare i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64, i32, i64) #0 5 6; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8: 7; GCN: v_mqsad_pk_u16_u8 v[0:1], v[4:5], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] 8; GCN-DAG: v_mov_b32_e32 v5, v1 9; GCN-DAG: v_mov_b32_e32 v4, v0 10define amdgpu_kernel void @v_mqsad_pk_u16_u8(i64 addrspace(1)* %out, i64 %src) { 11 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[4:5]},v"(i64 %src) #0 12 %tmp1 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0 13 %tmp2 = call i64 asm ";; force constraint", "=v,{v[4:5]}"(i64 %tmp1) #0 14 store i64 %tmp2, i64 addrspace(1)* %out, align 4 15 ret void 16} 17 18; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8_non_immediate: 19; GCN: v_mqsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7] 20; GCN-DAG: v_mov_b32_e32 v3, v1 21; GCN-DAG: v_mov_b32_e32 v2, v0 22define amdgpu_kernel void @v_mqsad_pk_u16_u8_non_immediate(i64 addrspace(1)* %out, i64 %src, i32 %a, i64 %b) { 23 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0 24 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0 25 %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0 26 %tmp3 = call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %tmp, i32 %tmp1, i64 %tmp2) #0 27 %tmp4 = call i64 asm ";; force constraint", "=v,{v[2:3]}"(i64 %tmp3) #0 28 store i64 %tmp4, i64 addrspace(1)* %out, align 4 29 ret void 30} 31 32attributes #0 = { nounwind readnone } 33