1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s 2 3declare i32 @llvm.amdgcn.readlane(i32, i32) #0 4 5; CHECK-LABEL: {{^}}test_readlane_sreg: 6; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} 7define amdgpu_kernel void @test_readlane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 { 8 %readlane = call i32 @llvm.amdgcn.readlane(i32 %src0, i32 %src1) 9 store i32 %readlane, i32 addrspace(1)* %out, align 4 10 ret void 11} 12 13; CHECK-LABEL: {{^}}test_readlane_imm_sreg: 14; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], 32 15; CHECK: v_readlane_b32 s{{[0-9]+}}, [[VVAL]], s{{[0-9]+}} 16define amdgpu_kernel void @test_readlane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 { 17 %readlane = call i32 @llvm.amdgcn.readlane(i32 32, i32 %src1) 18 store i32 %readlane, i32 addrspace(1)* %out, align 4 19 ret void 20} 21 22; CHECK-LABEL: {{^}}test_readlane_vregs: 23; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}} 24; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, [[LANE]] 25define amdgpu_kernel void @test_readlane_vregs(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 { 26 %tid = call i32 @llvm.amdgcn.workitem.id.x() 27 %gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid 28 %args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in 29 %value = extractelement <2 x i32> %args, i32 0 30 %lane = extractelement <2 x i32> %args, i32 1 31 %readlane = call i32 @llvm.amdgcn.readlane(i32 %value, i32 %lane) 32 store i32 %readlane, i32 addrspace(1)* %out, align 4 33 ret void 34} 35 36; TODO: m0 should be folded. 37; CHECK-LABEL: {{^}}test_readlane_m0_sreg: 38; CHECK: s_mov_b32 m0, -1 39; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0 40; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], [[COPY_M0]] 41; CHECK: v_readlane_b32 s{{[0-9]+}}, [[VVAL]], s{{[0-9]+}} 42define amdgpu_kernel void @test_readlane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 { 43 %m0 = call i32 asm "s_mov_b32 m0, -1", "={M0}"() 44 %readlane = call i32 @llvm.amdgcn.readlane(i32 %m0, i32 %src1) 45 store i32 %readlane, i32 addrspace(1)* %out, align 4 46 ret void 47} 48 49; CHECK-LABEL: {{^}}test_readlane_imm: 50; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 32 51define amdgpu_kernel void @test_readlane_imm(i32 addrspace(1)* %out, i32 %src0) #1 { 52 %readlane = call i32 @llvm.amdgcn.readlane(i32 %src0, i32 32) #0 53 store i32 %readlane, i32 addrspace(1)* %out, align 4 54 ret void 55} 56 57declare i32 @llvm.amdgcn.workitem.id.x() #2 58 59attributes #0 = { nounwind readnone convergent } 60attributes #1 = { nounwind } 61attributes #2 = { nounwind readnone } 62