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1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4declare half @llvm.floor.f16(half %a)
5declare <2 x half> @llvm.floor.v2f16(<2 x half> %a)
6
7; GCN-LABEL: {{^}}floor_f16
8; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
9; SI:  v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
10; SI:  v_floor_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
11; SI:  v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
12; VI:  v_floor_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]]
13; GCN: buffer_store_short v[[R_F16]]
14; GCN: s_endpgm
15define amdgpu_kernel void @floor_f16(
16    half addrspace(1)* %r,
17    half addrspace(1)* %a) {
18entry:
19  %a.val = load half, half addrspace(1)* %a
20  %r.val = call half @llvm.floor.f16(half %a.val)
21  store half %r.val, half addrspace(1)* %r
22  ret void
23}
24
25; GCN-LABEL: {{^}}floor_v2f16
26; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
27; SI-DAG:  v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
28; SI-DAG:  v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
29; SI-DAG:  v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
30; SI-DAG:  v_floor_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
31; SI-DAG:  v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
32; SI-DAG:  v_floor_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
33; SI-DAG:  v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
34; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
35; SI-NOT: and
36; SI:  v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
37
38; VI-DAG: v_floor_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_V2_F16]]
39; VI-DAG: v_floor_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
40; VI-NOT: and
41; VI:     v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
42
43; GCN: buffer_store_dword v[[R_V2_F16]]
44; GCN: s_endpgm
45define amdgpu_kernel void @floor_v2f16(
46    <2 x half> addrspace(1)* %r,
47    <2 x half> addrspace(1)* %a) {
48entry:
49  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
50  %r.val = call <2 x half> @llvm.floor.v2f16(<2 x half> %a.val)
51  store <2 x half> %r.val, <2 x half> addrspace(1)* %r
52  ret void
53}
54