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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 NXP
4  * Copyright (C) 2014 Freescale Semiconductor
5  */
6 
7 #ifndef __LS2_COMMON_H
8 #define __LS2_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_MP
13 #define CONFIG_GICV3
14 #define CONFIG_FSL_TZPC_BP147
15 
16 #include <asm/arch/stream_id_lsch3.h>
17 #include <asm/arch/config.h>
18 
19 /* Link Definitions */
20 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
21 
22 /* We need architecture specific misc initializations */
23 
24 /* Link Definitions */
25 #ifndef CONFIG_QSPI_BOOT
26 #else
27 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
28 #define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
29 #define CONFIG_ENV_SECT_SIZE		0x40000
30 #endif
31 
32 #define CONFIG_SKIP_LOWLEVEL_INIT
33 
34 #ifndef CONFIG_SPL
35 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
36 #endif
37 #ifndef CONFIG_SYS_FSL_DDR4
38 #define CONFIG_SYS_DDR_RAW_TIMING
39 #endif
40 
41 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
42 
43 #define CONFIG_VERY_BIG_RAM
44 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
46 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
48 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
49 
50 /*
51  * SMP Definitinos
52  */
53 #define CPU_RELEASE_ADDR		secondary_boot_func
54 
55 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
56 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
57 #define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
58 /*
59  * DDR controller use 0 as the base address for binding.
60  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
61  */
62 #define CONFIG_SYS_DP_DDR_BASE_PHY	0
63 #define CONFIG_DP_DDR_CTRL		2
64 #define CONFIG_DP_DDR_NUM_CTRLS		1
65 #endif
66 
67 /* Generic Timer Definitions */
68 /*
69  * This is not an accurate number. It is used in start.S. The frequency
70  * will be udpated later when get_bus_freq(0) is available.
71  */
72 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
73 
74 /* Size of malloc() pool */
75 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
76 
77 /* I2C */
78 #define CONFIG_SYS_I2C
79 
80 /* Serial Port */
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE     1
83 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
84 
85 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
86 
87 /* IFC */
88 #define CONFIG_FSL_IFC
89 
90 /*
91  * During booting, IFC is mapped at the region of 0x30000000.
92  * But this region is limited to 256MB. To accommodate NOR, promjet
93  * and FPGA. This region is divided as below:
94  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
95  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
96  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
97  *
98  * To accommodate bigger NOR flash and other devices, we will map IFC
99  * chip selects to as below:
100  * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
101  * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
102  * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
103  * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
104  * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
105  *
106  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
107  * CONFIG_SYS_FLASH_BASE has the final address (core view)
108  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
109  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
110  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
111  */
112 
113 #define CONFIG_SYS_FLASH_BASE			0x580000000ULL
114 #define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
115 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
116 
117 #define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
118 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
119 
120 #ifndef __ASSEMBLY__
121 unsigned long long get_qixis_addr(void);
122 #endif
123 #define QIXIS_BASE				get_qixis_addr()
124 #define QIXIS_BASE_PHYS				0x20000000
125 #define QIXIS_BASE_PHYS_EARLY			0xC000000
126 #define QIXIS_STAT_PRES1			0xb
127 #define QIXIS_SDID_MASK				0x07
128 #define QIXIS_ESDHC_NO_ADAPTER			0x7
129 
130 #define CONFIG_SYS_NAND_BASE			0x530000000ULL
131 #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
132 
133 /* MC firmware */
134 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
135 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
136 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
137 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
138 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
139 /* For LS2085A */
140 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
141 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
142 
143 /* Define phy_reset function to boot the MC based on mcinitcmd.
144  * This happens late enough to properly fixup u-boot env MAC addresses.
145  */
146 #define CONFIG_RESET_PHY_R
147 
148 /*
149  * Carve out a DDR region which will not be used by u-boot/Linux
150  *
151  * It will be used by MC and Debug Server. The MC region must be
152  * 512MB aligned, so the min size to hide is 512MB.
153  */
154 #ifdef CONFIG_FSL_MC_ENET
155 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(512UL * 1024 * 1024)
156 #endif
157 
158 /* Command line configuration */
159 
160 /* Miscellaneous configurable options */
161 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
162 
163 /* Physical Memory Map */
164 /* fixme: these need to be checked against the board */
165 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
166 
167 #define CONFIG_NR_DRAM_BANKS		3
168 
169 #define CONFIG_HWCONFIG
170 #define HWCONFIG_BUFFER_SIZE		128
171 
172 /* Allow to overwrite serial and ethaddr */
173 #define CONFIG_ENV_OVERWRITE
174 
175 /* Initial environment variables */
176 #define CONFIG_EXTRA_ENV_SETTINGS		\
177 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
178 	"loadaddr=0x80100000\0"			\
179 	"kernel_addr=0x100000\0"		\
180 	"ramdisk_addr=0x800000\0"		\
181 	"ramdisk_size=0x2000000\0"		\
182 	"fdt_high=0xa0000000\0"			\
183 	"initrd_high=0xffffffffffffffff\0"	\
184 	"kernel_start=0x581000000\0"		\
185 	"kernel_load=0xa0000000\0"		\
186 	"kernel_size=0x2800000\0"		\
187 	"console=ttyAMA0,38400n8\0"		\
188 	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
189 	" 0x580e00000 \0"
190 
191 #ifdef CONFIG_SD_BOOT
192 #define CONFIG_BOOTCOMMAND	"mmc read 0x80200000 0x6800 0x800;"\
193 				" fsl_mc apply dpl 0x80200000 &&" \
194 				" mmc read $kernel_load $kernel_start" \
195 				" $kernel_size && bootm $kernel_load"
196 #else
197 #define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580d00000 &&" \
198 				" cp.b $kernel_start $kernel_load" \
199 				" $kernel_size && bootm $kernel_load"
200 #endif
201 
202 /* Monitor Command Prompt */
203 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
204 #define CONFIG_SYS_MAXARGS		64	/* max command args */
205 
206 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
207 #define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
208 #define CONFIG_SPL_MAX_SIZE		0x16000
209 #define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
210 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
211 #define CONFIG_SPL_TEXT_BASE		0x1800a000
212 
213 #ifdef CONFIG_NAND_BOOT
214 #define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
215 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
216 #endif
217 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
218 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
219 #define CONFIG_SYS_MONITOR_LEN		(1024 * 1024)
220 
221 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
222 
223 #include <asm/arch/soc.h>
224 
225 #endif /* __LS2_COMMON_H */
226