1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_ 18 #define ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_ 19 20 #include <iosfwd> 21 22 #include <android-base/logging.h> 23 24 #include "arch/mips/registers_mips.h" 25 #include "base/globals.h" 26 #include "base/macros.h" 27 28 namespace art { 29 namespace mips { 30 31 // Values for double-precision floating point registers. 32 enum DRegister { 33 D0 = 0, 34 D1 = 1, 35 D2 = 2, 36 D3 = 3, 37 D4 = 4, 38 D5 = 5, 39 D6 = 6, 40 D7 = 7, 41 D8 = 8, 42 D9 = 9, 43 D10 = 10, 44 D11 = 11, 45 D12 = 12, 46 D13 = 13, 47 D14 = 14, 48 D15 = 15, 49 kNumberOfDRegisters = 16, 50 kNumberOfOverlappingDRegisters = 16, 51 kNoDRegister = -1, 52 }; 53 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 54 55 // Constants used for the decoding or encoding of the individual fields of instructions. 56 enum InstructionFields { 57 kOpcodeShift = 26, 58 kOpcodeBits = 6, 59 kRsShift = 21, 60 kRsBits = 5, 61 kRtShift = 16, 62 kRtBits = 5, 63 kRdShift = 11, 64 kRdBits = 5, 65 kShamtShift = 6, 66 kShamtBits = 5, 67 kFunctShift = 0, 68 kFunctBits = 6, 69 70 kFmtShift = 21, 71 kFmtBits = 5, 72 kFtShift = 16, 73 kFtBits = 5, 74 kFsShift = 11, 75 kFsBits = 5, 76 kFdShift = 6, 77 kFdBits = 5, 78 79 kMsaOperationShift = 23, 80 kMsaELMOperationShift = 22, 81 kMsa2ROperationShift = 18, 82 kMsa2RFOperationShift = 17, 83 kDfShift = 21, 84 kDfMShift = 16, 85 kDf2RShift = 16, 86 kDfNShift = 16, 87 kWtShift = 16, 88 kWtBits = 5, 89 kWsShift = 11, 90 kWsBits = 5, 91 kWdShift = 6, 92 kWdBits = 5, 93 kS10Shift = 16, 94 kI10Shift = 11, 95 kS10MinorShift = 2, 96 97 kBranchOffsetMask = 0x0000ffff, 98 kJumpOffsetMask = 0x03ffffff, 99 100 kMsaMajorOpcode = 0x1e, 101 kMsaDfMByteMask = 0x70, 102 kMsaDfMHalfwordMask = 0x60, 103 kMsaDfMWordMask = 0x40, 104 kMsaDfMDoublewordMask = 0x00, 105 kMsaDfNByteMask = 0x00, 106 kMsaDfNHalfwordMask = 0x20, 107 kMsaDfNWordMask = 0x30, 108 kMsaDfNDoublewordMask = 0x38, 109 kMsaS10Mask = 0x3ff, 110 }; 111 112 enum ScaleFactor { 113 TIMES_1 = 0, 114 TIMES_2 = 1, 115 TIMES_4 = 2, 116 TIMES_8 = 3 117 }; 118 119 class Instr { 120 public: 121 static const uint32_t kBreakPointInstruction = 0x0000000D; 122 IsBreakPoint()123 bool IsBreakPoint() { 124 return ((*reinterpret_cast<const uint32_t*>(this)) & 0xFC0000CF) == kBreakPointInstruction; 125 } 126 127 // Instructions are read out of a code stream. The only way to get a 128 // reference to an instruction is to convert a pointer. There is no way 129 // to allocate or create instances of class Instr. 130 // Use the At(pc) function to create references to Instr. At(uintptr_t pc)131 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); } 132 133 private: 134 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 135 }; 136 137 } // namespace mips 138 } // namespace art 139 140 #endif // ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_ 141