1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Freescale Semiconductor, Inc. 4 * Jason Liu <r64343@freescale.com> 5 * 6 * Configuration settings for Freescale MX53 low cost board. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO 13 14 #include <asm/arch/imx-regs.h> 15 16 #define CONFIG_CMDLINE_TAG 17 #define CONFIG_SETUP_MEMORY_TAGS 18 #define CONFIG_INITRD_TAG 19 20 #define CONFIG_SYS_FSL_CLK 21 22 /* Size of malloc() pool */ 23 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 24 25 #define CONFIG_REVISION_TAG 26 27 #define CONFIG_MXC_UART 28 #define CONFIG_MXC_UART_BASE UART1_BASE 29 30 /* MMC Configs */ 31 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 32 #define CONFIG_SYS_FSL_ESDHC_NUM 2 33 34 /* Eth Configs */ 35 #define CONFIG_MII 36 37 #define CONFIG_FEC_MXC 38 #define IMX_FEC_BASE FEC_BASE_ADDR 39 #define CONFIG_FEC_MXC_PHYADDR 0x1F 40 41 /* USB Configs */ 42 #define CONFIG_USB_EHCI_MX5 43 #define CONFIG_MXC_USB_PORT 1 44 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 45 #define CONFIG_MXC_USB_FLAGS 0 46 47 /* I2C Configs */ 48 #define CONFIG_SYS_I2C 49 #define CONFIG_SYS_I2C_MXC 50 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 51 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 52 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 53 54 /* PMIC Controller */ 55 #define CONFIG_POWER 56 #define CONFIG_POWER_I2C 57 #define CONFIG_DIALOG_POWER 58 #define CONFIG_POWER_FSL 59 #define CONFIG_POWER_FSL_MC13892 60 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 61 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 62 63 /* allow to overwrite serial and ethaddr */ 64 #define CONFIG_ENV_OVERWRITE 65 66 /* Command definition */ 67 68 69 #define CONFIG_ETHPRIME "FEC0" 70 71 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ 72 73 #define CONFIG_EXTRA_ENV_SETTINGS \ 74 "script=boot.scr\0" \ 75 "image=zImage\0" \ 76 "fdt_addr=0x71000000\0" \ 77 "boot_fdt=try\0" \ 78 "ip_dyn=yes\0" \ 79 "mmcdev=0\0" \ 80 "mmcpart=1\0" \ 81 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 82 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ 83 "loadbootscript=" \ 84 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 85 "bootscript=echo Running bootscript from mmc ...; " \ 86 "source\0" \ 87 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 88 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 89 "mmcboot=echo Booting from mmc ...; " \ 90 "run mmcargs; " \ 91 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 92 "if run loadfdt; then " \ 93 "bootz ${loadaddr} - ${fdt_addr}; " \ 94 "else " \ 95 "if test ${boot_fdt} = try; then " \ 96 "bootz; " \ 97 "else " \ 98 "echo WARN: Cannot load the DT; " \ 99 "fi; " \ 100 "fi; " \ 101 "else " \ 102 "bootz; " \ 103 "fi;\0" \ 104 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ 105 "root=/dev/nfs " \ 106 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 107 "netboot=echo Booting from net ...; " \ 108 "run netargs; " \ 109 "if test ${ip_dyn} = yes; then " \ 110 "setenv get_cmd dhcp; " \ 111 "else " \ 112 "setenv get_cmd tftp; " \ 113 "fi; " \ 114 "${get_cmd} ${image}; " \ 115 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 116 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 117 "bootz ${loadaddr} - ${fdt_addr}; " \ 118 "else " \ 119 "if test ${boot_fdt} = try; then " \ 120 "bootz; " \ 121 "else " \ 122 "echo ERROR: Cannot load the DT; " \ 123 "exit; " \ 124 "fi; " \ 125 "fi; " \ 126 "else " \ 127 "bootz; " \ 128 "fi;\0" 129 130 #define CONFIG_BOOTCOMMAND \ 131 "mmc dev ${mmcdev}; if mmc rescan; then " \ 132 "if run loadbootscript; then " \ 133 "run bootscript; " \ 134 "else " \ 135 "if run loadimage; then " \ 136 "run mmcboot; " \ 137 "else run netboot; " \ 138 "fi; " \ 139 "fi; " \ 140 "else run netboot; fi" 141 142 #define CONFIG_ARP_TIMEOUT 200UL 143 144 /* Miscellaneous configurable options */ 145 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 146 147 #define CONFIG_SYS_MEMTEST_START 0x70000000 148 #define CONFIG_SYS_MEMTEST_END 0x70010000 149 150 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 151 152 /* Physical Memory Map */ 153 #define CONFIG_NR_DRAM_BANKS 2 154 #define PHYS_SDRAM_1 CSD0_BASE_ADDR 155 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) 156 #define PHYS_SDRAM_2 CSD1_BASE_ADDR 157 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) 158 #define PHYS_SDRAM_SIZE (gd->ram_size) 159 160 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 161 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 162 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 163 164 #define CONFIG_SYS_INIT_SP_OFFSET \ 165 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 166 #define CONFIG_SYS_INIT_SP_ADDR \ 167 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 168 169 /* environment organization */ 170 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 171 #define CONFIG_ENV_SIZE (8 * 1024) 172 #define CONFIG_SYS_MMC_ENV_DEV 0 173 174 #ifdef CONFIG_CMD_SATA 175 #define CONFIG_SYS_SATA_MAX_DEVICE 1 176 #define CONFIG_DWC_AHSATA_PORT_ID 0 177 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR 178 #define CONFIG_LBA48 179 #endif 180 181 /* Framebuffer and LCD */ 182 #define CONFIG_PREBOOT 183 #define CONFIG_VIDEO_IPUV3 184 #define CONFIG_VIDEO_BMP_RLE8 185 #define CONFIG_SPLASH_SCREEN 186 #define CONFIG_BMP_16BPP 187 #define CONFIG_VIDEO_LOGO 188 189 #endif /* __CONFIG_H */ 190