1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PL011_H__ 8 #define __PL011_H__ 9 10 /* PL011 Registers */ 11 #define UARTDR 0x000 12 #define UARTRSR 0x004 13 #define UARTECR 0x004 14 #define UARTFR 0x018 15 #define UARTIMSC 0x038 16 #define UARTRIS 0x03C 17 #define UARTICR 0x044 18 19 /* PL011 registers (out of the SBSA specification) */ 20 #if !PL011_GENERIC_UART 21 #define UARTILPR 0x020 22 #define UARTIBRD 0x024 23 #define UARTFBRD 0x028 24 #define UARTLCR_H 0x02C 25 #define UARTCR 0x030 26 #define UARTIFLS 0x034 27 #define UARTMIS 0x040 28 #define UARTDMACR 0x048 29 #endif /* !PL011_GENERIC_UART */ 30 31 /* Data status bits */ 32 #define UART_DATA_ERROR_MASK 0x0F00 33 34 /* Status reg bits */ 35 #define UART_STATUS_ERROR_MASK 0x0F 36 37 /* Flag reg bits */ 38 #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ 39 #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ 40 #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ 41 #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ 42 #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ 43 #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ 44 #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ 45 #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ 46 #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ 47 48 #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ 49 #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ 50 #define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */ 51 52 /* Control reg bits */ 53 #if !PL011_GENERIC_UART 54 #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ 55 #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ 56 #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ 57 #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ 58 #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ 59 #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ 60 #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ 61 #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ 62 63 #if !defined(PL011_LINE_CONTROL) 64 /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ 65 #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) 66 #endif 67 68 /* Line Control Register Bits */ 69 #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ 70 #define PL011_UARTLCR_H_WLEN_8 (3 << 5) 71 #define PL011_UARTLCR_H_WLEN_7 (2 << 5) 72 #define PL011_UARTLCR_H_WLEN_6 (1 << 5) 73 #define PL011_UARTLCR_H_WLEN_5 (0 << 5) 74 #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ 75 #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ 76 #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ 77 #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ 78 #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ 79 80 #endif /* !PL011_GENERIC_UART */ 81 82 #endif /* __PL011_H__ */ 83