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1#!/usr/bin/env python
2
3# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
4
5from __future__ import print_function
6from capstone import *
7from capstone.arm import *
8from xprint import to_hex, to_x, to_x_32
9
10
11ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
12ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
13THUMB_CODE = b"\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84"
14THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
15THUMB_MCLASS = b"\xef\xf3\x02\x80"
16ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
17
18all_tests = (
19        (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
20        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "Thumb", None),
21        (CS_ARCH_ARM, CS_MODE_THUMB, ARM_CODE2, "Thumb-mixed", None),
22        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2 & register named with numbers", CS_OPT_SYNTAX_NOREGNAME),
23        (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", 0),
24        (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", 0),
25        )
26
27
28def print_insn_detail(insn):
29    # print address, mnemonic and operands
30    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
31
32    # "data" instruction generated by SKIPDATA option has no detail
33    if insn.id == 0:
34        return
35
36    if len(insn.operands) > 0:
37        print("\top_count: %u" % len(insn.operands))
38        c = 0
39        for i in insn.operands:
40            if i.type == ARM_OP_REG:
41                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
42            if i.type == ARM_OP_IMM:
43                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
44            if i.type == ARM_OP_PIMM:
45                print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm))
46            if i.type == ARM_OP_CIMM:
47                print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
48            if i.type == ARM_OP_FP:
49                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
50            if i.type == ARM_OP_SYSREG:
51                print("\t\toperands[%u].type: SYSREG = %u" % (c, i.reg))
52            if i.type == ARM_OP_SETEND:
53                if i.setend == ARM_SETEND_BE:
54                    print("\t\toperands[%u].type: SETEND = be" % c)
55                else:
56                    print("\t\toperands[%u].type: SETEND = le" % c)
57            if i.type == ARM_OP_MEM:
58                print("\t\toperands[%u].type: MEM" % c)
59                if i.mem.base != 0:
60                    print("\t\t\toperands[%u].mem.base: REG = %s" \
61                        % (c, insn.reg_name(i.mem.base)))
62                if i.mem.index != 0:
63                    print("\t\t\toperands[%u].mem.index: REG = %s" \
64                        % (c, insn.reg_name(i.mem.index)))
65                if i.mem.scale != 1:
66                    print("\t\t\toperands[%u].mem.scale: %u" \
67                        % (c, i.mem.scale))
68                if i.mem.disp != 0:
69                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
70                        % (c, to_x_32(i.mem.disp)))
71
72            if i.shift.type != ARM_SFT_INVALID and i.shift.value:
73                print("\t\t\tShift: %u = %u" \
74                    % (i.shift.type, i.shift.value))
75            if i.vector_index != -1:
76                print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index))
77            if i.subtracted:
78                print("\t\t\toperands[%u].subtracted = True" %c)
79
80            c += 1
81
82    if insn.update_flags:
83        print("\tUpdate-flags: True")
84    if insn.writeback:
85        print("\tWrite-back: True")
86    if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
87        print("\tCode condition: %u" % insn.cc)
88    if insn.cps_mode:
89        print("\tCPSI-mode: %u" %(insn.cps_mode))
90    if insn.cps_flag:
91        print("\tCPSI-flag: %u" %(insn.cps_flag))
92    if insn.vector_data:
93        print("\tVector-data: %u" %(insn.vector_data))
94    if insn.vector_size:
95        print("\tVector-size: %u" %(insn.vector_size))
96    if insn.usermode:
97        print("\tUser-mode: True")
98    if insn.mem_barrier:
99        print("\tMemory-barrier: %u" %(insn.mem_barrier))
100
101
102# ## Test class Cs
103def test_class():
104
105    for (arch, mode, code, comment, syntax) in all_tests:
106        print("*" * 16)
107        print("Platform: %s" % comment)
108        print("Code: %s" % to_hex(code))
109        print("Disasm:")
110
111        try:
112            md = Cs(arch, mode)
113            if syntax:
114                md.syntax = syntax
115            md.detail = True
116            for insn in md.disasm(code, 0x80001000):
117                print_insn_detail(insn)
118                print ()
119            print ("0x%x:\n" % (insn.address + insn.size))
120        except CsError as e:
121            print("ERROR: %s" % e)
122
123
124if __name__ == '__main__':
125    test_class()
126