1 /*********************************************************************** 2 Copyright (c) 2017 Google Inc. 3 Redistribution and use in source and binary forms, with or without 4 modification, are permitted provided that the following conditions 5 are met: 6 - Redistributions of source code must retain the above copyright notice, 7 this list of conditions and the following disclaimer. 8 - Redistributions in binary form must reproduce the above copyright 9 notice, this list of conditions and the following disclaimer in the 10 documentation and/or other materials provided with the distribution. 11 - Neither the name of Internet Society, IETF or IETF Trust, nor the 12 names of specific contributors, may be used to endorse or promote 13 products derived from this software without specific prior written 14 permission. 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 POSSIBILITY OF SUCH DAMAGE. 26 ***********************************************************************/ 27 28 #ifndef SILK_NSQ_DEL_DEC_ARM_H 29 #define SILK_NSQ_DEL_DEC_ARM_H 30 31 #include "celt/arm/armcpu.h" 32 33 #if defined(OPUS_ARM_MAY_HAVE_NEON_INTR) 34 void silk_NSQ_del_dec_neon( 35 const silk_encoder_state *psEncC, silk_nsq_state *NSQ, 36 SideInfoIndices *psIndices, const opus_int16 x16[], opus_int8 pulses[], 37 const opus_int16 PredCoef_Q12[2 * MAX_LPC_ORDER], 38 const opus_int16 LTPCoef_Q14[LTP_ORDER * MAX_NB_SUBFR], 39 const opus_int16 AR_Q13[MAX_NB_SUBFR * MAX_SHAPE_LPC_ORDER], 40 const opus_int HarmShapeGain_Q14[MAX_NB_SUBFR], 41 const opus_int Tilt_Q14[MAX_NB_SUBFR], 42 const opus_int32 LF_shp_Q14[MAX_NB_SUBFR], 43 const opus_int32 Gains_Q16[MAX_NB_SUBFR], 44 const opus_int pitchL[MAX_NB_SUBFR], const opus_int Lambda_Q10, 45 const opus_int LTP_scale_Q14); 46 47 #if !defined(OPUS_HAVE_RTCD) 48 #define OVERRIDE_silk_NSQ_del_dec (1) 49 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ 50 LTPCoef_Q14, AR_Q13, HarmShapeGain_Q14, Tilt_Q14, \ 51 LF_shp_Q14, Gains_Q16, pitchL, Lambda_Q10, \ 52 LTP_scale_Q14, arch) \ 53 ((void)(arch), \ 54 PRESUME_NEON(silk_NSQ_del_dec)( \ 55 psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, \ 56 AR_Q13, HarmShapeGain_Q14, Tilt_Q14, LF_shp_Q14, Gains_Q16, pitchL, \ 57 Lambda_Q10, LTP_scale_Q14)) 58 #endif 59 #endif 60 61 #if !defined(OVERRIDE_silk_NSQ_del_dec) 62 /*Is run-time CPU detection enabled on this platform?*/ 63 #if defined(OPUS_HAVE_RTCD) && (defined(OPUS_ARM_MAY_HAVE_NEON_INTR) && \ 64 !defined(OPUS_ARM_PRESUME_NEON_INTR)) 65 extern void (*const SILK_NSQ_DEL_DEC_IMPL[OPUS_ARCHMASK + 1])( 66 const silk_encoder_state *psEncC, silk_nsq_state *NSQ, 67 SideInfoIndices *psIndices, const opus_int16 x16[], opus_int8 pulses[], 68 const opus_int16 PredCoef_Q12[2 * MAX_LPC_ORDER], 69 const opus_int16 LTPCoef_Q14[LTP_ORDER * MAX_NB_SUBFR], 70 const opus_int16 AR_Q13[MAX_NB_SUBFR * MAX_SHAPE_LPC_ORDER], 71 const opus_int HarmShapeGain_Q14[MAX_NB_SUBFR], 72 const opus_int Tilt_Q14[MAX_NB_SUBFR], 73 const opus_int32 LF_shp_Q14[MAX_NB_SUBFR], 74 const opus_int32 Gains_Q16[MAX_NB_SUBFR], 75 const opus_int pitchL[MAX_NB_SUBFR], const opus_int Lambda_Q10, 76 const opus_int LTP_scale_Q14); 77 #define OVERRIDE_silk_NSQ_del_dec (1) 78 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ 79 LTPCoef_Q14, AR_Q13, HarmShapeGain_Q14, Tilt_Q14, \ 80 LF_shp_Q14, Gains_Q16, pitchL, Lambda_Q10, \ 81 LTP_scale_Q14, arch) \ 82 ((*SILK_NSQ_DEL_DEC_IMPL[(arch)&OPUS_ARCHMASK])( \ 83 psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, \ 84 AR_Q13, HarmShapeGain_Q14, Tilt_Q14, LF_shp_Q14, Gains_Q16, pitchL, \ 85 Lambda_Q10, LTP_scale_Q14)) 86 #elif defined(OPUS_ARM_PRESUME_NEON_INTR) 87 #define OVERRIDE_silk_NSQ_del_dec (1) 88 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ 89 LTPCoef_Q14, AR_Q13, HarmShapeGain_Q14, Tilt_Q14, \ 90 LF_shp_Q14, Gains_Q16, pitchL, Lambda_Q10, \ 91 LTP_scale_Q14, arch) \ 92 ((void)(arch), \ 93 silk_NSQ_del_dec_neon(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ 94 LTPCoef_Q14, AR_Q13, HarmShapeGain_Q14, Tilt_Q14, \ 95 LF_shp_Q14, Gains_Q16, pitchL, Lambda_Q10, \ 96 LTP_scale_Q14)) 97 #endif 98 #endif 99 100 #endif /* end SILK_NSQ_DEL_DEC_ARM_H */ 101