1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_string.h"
31 #include "util/u_math.h"
32
33 #include "os/os_process.h"
34
35 #include "svga_winsys.h"
36 #include "svga_public.h"
37 #include "svga_context.h"
38 #include "svga_format.h"
39 #include "svga_msg.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
45
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
48
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
51
52 #ifdef DEBUG
53 int SVGA_DEBUG = 0;
54
55 static const struct debug_named_value svga_debug_flags[] = {
56 { "dma", DEBUG_DMA, NULL },
57 { "tgsi", DEBUG_TGSI, NULL },
58 { "pipe", DEBUG_PIPE, NULL },
59 { "state", DEBUG_STATE, NULL },
60 { "screen", DEBUG_SCREEN, NULL },
61 { "tex", DEBUG_TEX, NULL },
62 { "swtnl", DEBUG_SWTNL, NULL },
63 { "const", DEBUG_CONSTS, NULL },
64 { "viewport", DEBUG_VIEWPORT, NULL },
65 { "views", DEBUG_VIEWS, NULL },
66 { "perf", DEBUG_PERF, NULL },
67 { "flush", DEBUG_FLUSH, NULL },
68 { "sync", DEBUG_SYNC, NULL },
69 { "cache", DEBUG_CACHE, NULL },
70 { "streamout", DEBUG_STREAMOUT, NULL },
71 { "query", DEBUG_QUERY, NULL },
72 { "samplers", DEBUG_SAMPLERS, NULL },
73 DEBUG_NAMED_VALUE_END
74 };
75 #endif
76
77 static const char *
svga_get_vendor(struct pipe_screen * pscreen)78 svga_get_vendor( struct pipe_screen *pscreen )
79 {
80 return "VMware, Inc.";
81 }
82
83
84 static const char *
svga_get_name(struct pipe_screen * pscreen)85 svga_get_name( struct pipe_screen *pscreen )
86 {
87 const char *build = "", *llvm = "", *mutex = "";
88 static char name[100];
89 #ifdef DEBUG
90 /* Only return internal details in the DEBUG version:
91 */
92 build = "build: DEBUG;";
93 mutex = "mutex: " PIPE_ATOMIC ";";
94 #elif defined(VMX86_STATS)
95 build = "build: OPT;";
96 #else
97 build = "build: RELEASE;";
98 #endif
99 #ifdef HAVE_LLVM
100 llvm = "LLVM;";
101 #endif
102
103 util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
104 return name;
105 }
106
107
108 /** Helper for querying float-valued device cap */
109 static float
get_float_cap(struct svga_winsys_screen * sws,SVGA3dDevCapIndex cap,float defaultVal)110 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
111 float defaultVal)
112 {
113 SVGA3dDevCapResult result;
114 if (sws->get_cap(sws, cap, &result))
115 return result.f;
116 else
117 return defaultVal;
118 }
119
120
121 /** Helper for querying uint-valued device cap */
122 static unsigned
get_uint_cap(struct svga_winsys_screen * sws,SVGA3dDevCapIndex cap,unsigned defaultVal)123 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
124 unsigned defaultVal)
125 {
126 SVGA3dDevCapResult result;
127 if (sws->get_cap(sws, cap, &result))
128 return result.u;
129 else
130 return defaultVal;
131 }
132
133
134 /** Helper for querying boolean-valued device cap */
135 static boolean
get_bool_cap(struct svga_winsys_screen * sws,SVGA3dDevCapIndex cap,boolean defaultVal)136 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
137 boolean defaultVal)
138 {
139 SVGA3dDevCapResult result;
140 if (sws->get_cap(sws, cap, &result))
141 return result.b;
142 else
143 return defaultVal;
144 }
145
146
147 static float
svga_get_paramf(struct pipe_screen * screen,enum pipe_capf param)148 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
149 {
150 struct svga_screen *svgascreen = svga_screen(screen);
151 struct svga_winsys_screen *sws = svgascreen->sws;
152
153 switch (param) {
154 case PIPE_CAPF_MAX_LINE_WIDTH:
155 return svgascreen->maxLineWidth;
156 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
157 return svgascreen->maxLineWidthAA;
158
159 case PIPE_CAPF_MAX_POINT_WIDTH:
160 /* fall-through */
161 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
162 return svgascreen->maxPointSize;
163
164 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
165 return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
166
167 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
168 return 15.0;
169
170 case PIPE_CAPF_GUARD_BAND_LEFT:
171 case PIPE_CAPF_GUARD_BAND_TOP:
172 case PIPE_CAPF_GUARD_BAND_RIGHT:
173 case PIPE_CAPF_GUARD_BAND_BOTTOM:
174 return 0.0;
175 }
176
177 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
178 return 0;
179 }
180
181
182 static int
svga_get_param(struct pipe_screen * screen,enum pipe_cap param)183 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
184 {
185 struct svga_screen *svgascreen = svga_screen(screen);
186 struct svga_winsys_screen *sws = svgascreen->sws;
187 SVGA3dDevCapResult result;
188
189 switch (param) {
190 case PIPE_CAP_NPOT_TEXTURES:
191 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
192 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
193 return 1;
194 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
195 /*
196 * "In virtually every OpenGL implementation and hardware,
197 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
198 * http://www.opengl.org/wiki/Blending
199 */
200 return sws->have_vgpu10 ? 1 : 0;
201 case PIPE_CAP_ANISOTROPIC_FILTER:
202 return 1;
203 case PIPE_CAP_POINT_SPRITE:
204 return 1;
205 case PIPE_CAP_TGSI_TEXCOORD:
206 return 0;
207 case PIPE_CAP_MAX_RENDER_TARGETS:
208 return svgascreen->max_color_buffers;
209 case PIPE_CAP_OCCLUSION_QUERY:
210 return 1;
211 case PIPE_CAP_QUERY_TIME_ELAPSED:
212 return 0;
213 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
214 return sws->have_vgpu10;
215 case PIPE_CAP_TEXTURE_SWIZZLE:
216 return 1;
217 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
218 return 0;
219 case PIPE_CAP_USER_VERTEX_BUFFERS:
220 return 0;
221 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
222 return 256;
223
224 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
225 {
226 unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
227 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
228 levels = MIN2(util_logbase2(result.u) + 1, levels);
229 else
230 levels = 12 /* 2048x2048 */;
231 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
232 levels = MIN2(util_logbase2(result.u) + 1, levels);
233 else
234 levels = 12 /* 2048x2048 */;
235 return levels;
236 }
237
238 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
239 if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
240 return 8; /* max 128x128x128 */
241 return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
242
243 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
244 /*
245 * No mechanism to query the host, and at least limited to 2048x2048 on
246 * certain hardware.
247 */
248 return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
249 12 /* 2048x2048 */);
250
251 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
252 return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
253
254 case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
255 return 1;
256
257 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
258 return 1;
259 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
260 return sws->have_vgpu10;
261 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
262 return 0;
263 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
264 return !sws->have_vgpu10;
265
266 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
267 return 1; /* The color outputs of vertex shaders are not clamped */
268 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
269 return 0; /* The driver can't clamp vertex colors */
270 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
271 return 0; /* The driver can't clamp fragment colors */
272
273 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
274 return 1; /* expected for GL_ARB_framebuffer_object */
275
276 case PIPE_CAP_GLSL_FEATURE_LEVEL:
277 return sws->have_vgpu10 ? 330 : 120;
278
279 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
280 return 0;
281
282 case PIPE_CAP_SM3:
283 return 1;
284
285 case PIPE_CAP_DEPTH_CLIP_DISABLE:
286 case PIPE_CAP_INDEP_BLEND_ENABLE:
287 case PIPE_CAP_CONDITIONAL_RENDER:
288 case PIPE_CAP_QUERY_TIMESTAMP:
289 case PIPE_CAP_TGSI_INSTANCEID:
290 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
291 case PIPE_CAP_SEAMLESS_CUBE_MAP:
292 case PIPE_CAP_FAKE_SW_MSAA:
293 return sws->have_vgpu10;
294
295 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
296 return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
297 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
298 return sws->have_vgpu10 ? 4 : 0;
299 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
300 return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
301 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
302 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
303 return 0;
304 case PIPE_CAP_TEXTURE_MULTISAMPLE:
305 return svgascreen->ms_samples ? 1 : 0;
306
307 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
308 /* convert bytes to texels for the case of the largest texel
309 * size: float[4].
310 */
311 return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
312
313 case PIPE_CAP_MIN_TEXEL_OFFSET:
314 return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
315 case PIPE_CAP_MAX_TEXEL_OFFSET:
316 return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
317
318 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
319 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
320 return 0;
321
322 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
323 return sws->have_vgpu10 ? 256 : 0;
324 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
325 return sws->have_vgpu10 ? 1024 : 0;
326
327 case PIPE_CAP_PRIMITIVE_RESTART:
328 return 1; /* may be a sw fallback, depending on restart index */
329
330 case PIPE_CAP_GENERATE_MIPMAP:
331 return sws->have_generate_mipmap_cmd;
332
333 case PIPE_CAP_NATIVE_FENCE_FD:
334 return sws->have_fence_fd;
335
336 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
337 return 1;
338
339 /* Unsupported features */
340 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
341 case PIPE_CAP_SHADER_STENCIL_EXPORT:
342 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
343 case PIPE_CAP_INDEP_BLEND_FUNC:
344 case PIPE_CAP_TEXTURE_BARRIER:
345 case PIPE_CAP_MAX_VERTEX_STREAMS:
346 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
347 case PIPE_CAP_COMPUTE:
348 case PIPE_CAP_START_INSTANCE:
349 case PIPE_CAP_CUBE_MAP_ARRAY:
350 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
351 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
352 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
353 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
354 case PIPE_CAP_TEXTURE_GATHER_SM5:
355 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
356 case PIPE_CAP_TEXTURE_QUERY_LOD:
357 case PIPE_CAP_SAMPLE_SHADING:
358 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
359 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
360 case PIPE_CAP_DRAW_INDIRECT:
361 case PIPE_CAP_MULTI_DRAW_INDIRECT:
362 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
363 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
364 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
365 case PIPE_CAP_SAMPLER_VIEW_TARGET:
366 case PIPE_CAP_CLIP_HALFZ:
367 case PIPE_CAP_VERTEXID_NOBASE:
368 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
369 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
370 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
371 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
372 case PIPE_CAP_INVALIDATE_BUFFER:
373 case PIPE_CAP_STRING_MARKER:
374 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
375 case PIPE_CAP_QUERY_MEMORY_INFO:
376 case PIPE_CAP_PCI_GROUP:
377 case PIPE_CAP_PCI_BUS:
378 case PIPE_CAP_PCI_DEVICE:
379 case PIPE_CAP_PCI_FUNCTION:
380 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
381 return 0;
382 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
383 return 64;
384 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
385 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
386 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
387 return 1; /* need 4-byte alignment for all offsets and strides */
388 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
389 return 2048;
390 case PIPE_CAP_MAX_VIEWPORTS:
391 return 1;
392 case PIPE_CAP_ENDIANNESS:
393 return PIPE_ENDIAN_LITTLE;
394
395 case PIPE_CAP_VENDOR_ID:
396 return 0x15ad; /* VMware Inc. */
397 case PIPE_CAP_DEVICE_ID:
398 return 0x0405; /* assume SVGA II */
399 case PIPE_CAP_ACCELERATED:
400 return 0; /* XXX: */
401 case PIPE_CAP_VIDEO_MEMORY:
402 /* XXX: Query the host ? */
403 return 1;
404 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
405 return sws->have_vgpu10;
406 case PIPE_CAP_CLEAR_TEXTURE:
407 return sws->have_vgpu10;
408 case PIPE_CAP_UMA:
409 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
410 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
411 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
412 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
413 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
414 case PIPE_CAP_DEPTH_BOUNDS_TEST:
415 case PIPE_CAP_TGSI_TXQS:
416 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
417 case PIPE_CAP_SHAREABLE_SHADERS:
418 case PIPE_CAP_DRAW_PARAMETERS:
419 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
420 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
421 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
422 case PIPE_CAP_QUERY_BUFFER_OBJECT:
423 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
424 case PIPE_CAP_CULL_DISTANCE:
425 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
426 case PIPE_CAP_TGSI_VOTE:
427 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
428 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
429 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
430 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
431 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
432 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
433 case PIPE_CAP_TGSI_FS_FBFETCH:
434 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
435 case PIPE_CAP_DOUBLES:
436 case PIPE_CAP_INT64:
437 case PIPE_CAP_INT64_DIVMOD:
438 case PIPE_CAP_TGSI_TEX_TXF_LZ:
439 case PIPE_CAP_TGSI_CLOCK:
440 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
441 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
442 case PIPE_CAP_TGSI_BALLOT:
443 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
444 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
445 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
446 case PIPE_CAP_POST_DEPTH_COVERAGE:
447 case PIPE_CAP_BINDLESS_TEXTURE:
448 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
449 case PIPE_CAP_QUERY_SO_OVERFLOW:
450 case PIPE_CAP_MEMOBJ:
451 case PIPE_CAP_LOAD_CONSTBUF:
452 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
453 case PIPE_CAP_TILE_RASTER_ORDER:
454 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
455 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
456 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
457 return 0;
458 }
459
460 debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
461 return 0;
462 }
463
464
465 static int
vgpu9_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)466 vgpu9_get_shader_param(struct pipe_screen *screen,
467 enum pipe_shader_type shader,
468 enum pipe_shader_cap param)
469 {
470 struct svga_screen *svgascreen = svga_screen(screen);
471 struct svga_winsys_screen *sws = svgascreen->sws;
472 unsigned val;
473
474 assert(!sws->have_vgpu10);
475
476 switch (shader)
477 {
478 case PIPE_SHADER_FRAGMENT:
479 switch (param)
480 {
481 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
482 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
483 return get_uint_cap(sws,
484 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
485 512);
486 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
487 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
488 return 512;
489 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
490 return SVGA3D_MAX_NESTING_LEVEL;
491 case PIPE_SHADER_CAP_MAX_INPUTS:
492 return 10;
493 case PIPE_SHADER_CAP_MAX_OUTPUTS:
494 return svgascreen->max_color_buffers;
495 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
496 return 224 * sizeof(float[4]);
497 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
498 return 1;
499 case PIPE_SHADER_CAP_MAX_TEMPS:
500 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
501 return MIN2(val, SVGA3D_TEMPREG_MAX);
502 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
503 /*
504 * Although PS 3.0 has some addressing abilities it can only represent
505 * loops that can be statically determined and unrolled. Given we can
506 * only handle a subset of the cases that the state tracker already
507 * does it is better to defer loop unrolling to the state tracker.
508 */
509 return 0;
510 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
511 return 0;
512 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
513 return 0;
514 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
515 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
516 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
517 return 0;
518 case PIPE_SHADER_CAP_SUBROUTINES:
519 return 0;
520 case PIPE_SHADER_CAP_INT64_ATOMICS:
521 case PIPE_SHADER_CAP_INTEGERS:
522 return 0;
523 case PIPE_SHADER_CAP_FP16:
524 return 0;
525 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
526 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
527 return 16;
528 case PIPE_SHADER_CAP_PREFERRED_IR:
529 return PIPE_SHADER_IR_TGSI;
530 case PIPE_SHADER_CAP_SUPPORTED_IRS:
531 return 0;
532 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
533 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
534 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
535 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
536 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
537 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
538 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
539 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
540 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
541 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
542 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
543 return 0;
544 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
545 return 32;
546 }
547 /* If we get here, we failed to handle a cap above */
548 debug_printf("Unexpected fragment shader query %u\n", param);
549 return 0;
550 case PIPE_SHADER_VERTEX:
551 switch (param)
552 {
553 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
554 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
555 return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
556 512);
557 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
558 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
559 /* XXX: until we have vertex texture support */
560 return 0;
561 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
562 return SVGA3D_MAX_NESTING_LEVEL;
563 case PIPE_SHADER_CAP_MAX_INPUTS:
564 return 16;
565 case PIPE_SHADER_CAP_MAX_OUTPUTS:
566 return 10;
567 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
568 return 256 * sizeof(float[4]);
569 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
570 return 1;
571 case PIPE_SHADER_CAP_MAX_TEMPS:
572 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
573 return MIN2(val, SVGA3D_TEMPREG_MAX);
574 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
575 return 0;
576 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
577 return 0;
578 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
579 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
580 return 1;
581 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
582 return 0;
583 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
584 return 1;
585 case PIPE_SHADER_CAP_SUBROUTINES:
586 return 0;
587 case PIPE_SHADER_CAP_INT64_ATOMICS:
588 case PIPE_SHADER_CAP_INTEGERS:
589 return 0;
590 case PIPE_SHADER_CAP_FP16:
591 return 0;
592 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
593 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
594 return 0;
595 case PIPE_SHADER_CAP_PREFERRED_IR:
596 return PIPE_SHADER_IR_TGSI;
597 case PIPE_SHADER_CAP_SUPPORTED_IRS:
598 return 0;
599 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
600 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
601 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
602 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
603 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
604 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
605 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
606 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
607 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
608 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
609 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
610 return 0;
611 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
612 return 32;
613 }
614 /* If we get here, we failed to handle a cap above */
615 debug_printf("Unexpected vertex shader query %u\n", param);
616 return 0;
617 case PIPE_SHADER_GEOMETRY:
618 case PIPE_SHADER_COMPUTE:
619 case PIPE_SHADER_TESS_CTRL:
620 case PIPE_SHADER_TESS_EVAL:
621 /* no support for geometry, tess or compute shaders at this time */
622 return 0;
623 default:
624 debug_printf("Unexpected shader type (%u) query\n", shader);
625 return 0;
626 }
627 return 0;
628 }
629
630
631 static int
vgpu10_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)632 vgpu10_get_shader_param(struct pipe_screen *screen,
633 enum pipe_shader_type shader,
634 enum pipe_shader_cap param)
635 {
636 struct svga_screen *svgascreen = svga_screen(screen);
637 struct svga_winsys_screen *sws = svgascreen->sws;
638
639 assert(sws->have_vgpu10);
640 (void) sws; /* silence unused var warnings in non-debug builds */
641
642 /* Only VS, GS, FS supported */
643 if (shader != PIPE_SHADER_VERTEX &&
644 shader != PIPE_SHADER_GEOMETRY &&
645 shader != PIPE_SHADER_FRAGMENT) {
646 return 0;
647 }
648
649 /* NOTE: we do not query the device for any caps/limits at this time */
650
651 /* Generally the same limits for vertex, geometry and fragment shaders */
652 switch (param) {
653 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
654 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
655 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
656 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
657 return 64 * 1024;
658 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
659 return 64;
660 case PIPE_SHADER_CAP_MAX_INPUTS:
661 if (shader == PIPE_SHADER_FRAGMENT)
662 return VGPU10_MAX_FS_INPUTS;
663 else if (shader == PIPE_SHADER_GEOMETRY)
664 return VGPU10_MAX_GS_INPUTS;
665 else
666 return VGPU10_MAX_VS_INPUTS;
667 case PIPE_SHADER_CAP_MAX_OUTPUTS:
668 if (shader == PIPE_SHADER_FRAGMENT)
669 return VGPU10_MAX_FS_OUTPUTS;
670 else if (shader == PIPE_SHADER_GEOMETRY)
671 return VGPU10_MAX_GS_OUTPUTS;
672 else
673 return VGPU10_MAX_VS_OUTPUTS;
674 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
675 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
676 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
677 return svgascreen->max_const_buffers;
678 case PIPE_SHADER_CAP_MAX_TEMPS:
679 return VGPU10_MAX_TEMPS;
680 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
681 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
682 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
683 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
684 return TRUE; /* XXX verify */
685 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
686 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
687 case PIPE_SHADER_CAP_SUBROUTINES:
688 case PIPE_SHADER_CAP_INTEGERS:
689 return TRUE;
690 case PIPE_SHADER_CAP_FP16:
691 return FALSE;
692 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
693 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
694 return SVGA3D_DX_MAX_SAMPLERS;
695 case PIPE_SHADER_CAP_PREFERRED_IR:
696 return PIPE_SHADER_IR_TGSI;
697 case PIPE_SHADER_CAP_SUPPORTED_IRS:
698 return 0;
699 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
700 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
701 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
702 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
703 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
704 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
705 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
706 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
707 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
708 case PIPE_SHADER_CAP_INT64_ATOMICS:
709 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
710 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
711 return 0;
712 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
713 return 32;
714 default:
715 debug_printf("Unexpected vgpu10 shader query %u\n", param);
716 return 0;
717 }
718 return 0;
719 }
720
721
722 static int
svga_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)723 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
724 enum pipe_shader_cap param)
725 {
726 struct svga_screen *svgascreen = svga_screen(screen);
727 struct svga_winsys_screen *sws = svgascreen->sws;
728 if (sws->have_vgpu10) {
729 return vgpu10_get_shader_param(screen, shader, param);
730 }
731 else {
732 return vgpu9_get_shader_param(screen, shader, param);
733 }
734 }
735
736
737 static void
svga_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)738 svga_fence_reference(struct pipe_screen *screen,
739 struct pipe_fence_handle **ptr,
740 struct pipe_fence_handle *fence)
741 {
742 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
743 sws->fence_reference(sws, ptr, fence);
744 }
745
746
747 static boolean
svga_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)748 svga_fence_finish(struct pipe_screen *screen,
749 struct pipe_context *ctx,
750 struct pipe_fence_handle *fence,
751 uint64_t timeout)
752 {
753 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
754 boolean retVal;
755
756 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
757
758 if (!timeout) {
759 retVal = sws->fence_signalled(sws, fence, 0) == 0;
760 }
761 else {
762 SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
763 __FUNCTION__, fence);
764
765 retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
766 }
767
768 SVGA_STATS_TIME_POP(sws);
769
770 return retVal;
771 }
772
773
774 static int
svga_fence_get_fd(struct pipe_screen * screen,struct pipe_fence_handle * fence)775 svga_fence_get_fd(struct pipe_screen *screen,
776 struct pipe_fence_handle *fence)
777 {
778 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
779
780 return sws->fence_get_fd(sws, fence, TRUE);
781 }
782
783
784 static int
svga_get_driver_query_info(struct pipe_screen * screen,unsigned index,struct pipe_driver_query_info * info)785 svga_get_driver_query_info(struct pipe_screen *screen,
786 unsigned index,
787 struct pipe_driver_query_info *info)
788 {
789 #define QUERY(NAME, ENUM, UNITS) \
790 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
791
792 static const struct pipe_driver_query_info queries[] = {
793 /* per-frame counters */
794 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
795 PIPE_DRIVER_QUERY_TYPE_UINT64),
796 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
797 PIPE_DRIVER_QUERY_TYPE_UINT64),
798 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
799 PIPE_DRIVER_QUERY_TYPE_UINT64),
800 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
801 PIPE_DRIVER_QUERY_TYPE_UINT64),
802 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
803 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
804 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
805 PIPE_DRIVER_QUERY_TYPE_UINT64),
806 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
807 PIPE_DRIVER_QUERY_TYPE_UINT64),
808 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
809 PIPE_DRIVER_QUERY_TYPE_BYTES),
810 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
811 PIPE_DRIVER_QUERY_TYPE_BYTES),
812 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
813 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
814 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
815 PIPE_DRIVER_QUERY_TYPE_UINT64),
816 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
817 PIPE_DRIVER_QUERY_TYPE_UINT64),
818 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
819 PIPE_DRIVER_QUERY_TYPE_UINT64),
820 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
821 PIPE_DRIVER_QUERY_TYPE_UINT64),
822 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
823 PIPE_DRIVER_QUERY_TYPE_UINT64),
824 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
825 PIPE_DRIVER_QUERY_TYPE_UINT64),
826
827 /* running total counters */
828 QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
829 PIPE_DRIVER_QUERY_TYPE_BYTES),
830 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
831 PIPE_DRIVER_QUERY_TYPE_UINT64),
832 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
833 PIPE_DRIVER_QUERY_TYPE_UINT64),
834 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
835 PIPE_DRIVER_QUERY_TYPE_UINT64),
836 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
837 PIPE_DRIVER_QUERY_TYPE_UINT64),
838 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
839 PIPE_DRIVER_QUERY_TYPE_UINT64),
840 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
841 PIPE_DRIVER_QUERY_TYPE_UINT64),
842 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
843 PIPE_DRIVER_QUERY_TYPE_FLOAT),
844 };
845 #undef QUERY
846
847 if (!info)
848 return ARRAY_SIZE(queries);
849
850 if (index >= ARRAY_SIZE(queries))
851 return 0;
852
853 *info = queries[index];
854 return 1;
855 }
856
857
858 static void
init_logging(struct pipe_screen * screen)859 init_logging(struct pipe_screen *screen)
860 {
861 static const char *log_prefix = "Mesa: ";
862 char host_log[1000];
863
864 /* Log Version to Host */
865 util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
866 "%s%s", log_prefix, svga_get_name(screen));
867 svga_host_log(host_log);
868
869 util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
870 "%s%s"
871 #ifdef MESA_GIT_SHA1
872 " (" MESA_GIT_SHA1 ")"
873 #endif
874 , log_prefix, PACKAGE_VERSION);
875 svga_host_log(host_log);
876
877 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
878 * line (program name and arguments).
879 */
880 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
881 char cmdline[1000];
882 if (os_get_command_line(cmdline, sizeof(cmdline))) {
883 util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
884 "%s%s", log_prefix, cmdline);
885 svga_host_log(host_log);
886 }
887 }
888 }
889
890
891 static void
svga_destroy_screen(struct pipe_screen * screen)892 svga_destroy_screen( struct pipe_screen *screen )
893 {
894 struct svga_screen *svgascreen = svga_screen(screen);
895
896 svga_screen_cache_cleanup(svgascreen);
897
898 mtx_destroy(&svgascreen->swc_mutex);
899 mtx_destroy(&svgascreen->tex_mutex);
900
901 svgascreen->sws->destroy(svgascreen->sws);
902
903 FREE(svgascreen);
904 }
905
906
907 /**
908 * Create a new svga_screen object
909 */
910 struct pipe_screen *
svga_screen_create(struct svga_winsys_screen * sws)911 svga_screen_create(struct svga_winsys_screen *sws)
912 {
913 struct svga_screen *svgascreen;
914 struct pipe_screen *screen;
915
916 #ifdef DEBUG
917 SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
918 #endif
919
920 svgascreen = CALLOC_STRUCT(svga_screen);
921 if (!svgascreen)
922 goto error1;
923
924 svgascreen->debug.force_level_surface_view =
925 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
926 svgascreen->debug.force_surface_view =
927 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
928 svgascreen->debug.force_sampler_view =
929 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
930 svgascreen->debug.no_surface_view =
931 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
932 svgascreen->debug.no_sampler_view =
933 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
934 svgascreen->debug.no_cache_index_buffers =
935 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
936
937 screen = &svgascreen->screen;
938
939 screen->destroy = svga_destroy_screen;
940 screen->get_name = svga_get_name;
941 screen->get_vendor = svga_get_vendor;
942 screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
943 screen->get_param = svga_get_param;
944 screen->get_shader_param = svga_get_shader_param;
945 screen->get_paramf = svga_get_paramf;
946 screen->get_timestamp = NULL;
947 screen->is_format_supported = svga_is_format_supported;
948 screen->context_create = svga_context_create;
949 screen->fence_reference = svga_fence_reference;
950 screen->fence_finish = svga_fence_finish;
951 screen->fence_get_fd = svga_fence_get_fd;
952
953 screen->get_driver_query_info = svga_get_driver_query_info;
954 svgascreen->sws = sws;
955
956 svga_init_screen_resource_functions(svgascreen);
957
958 if (sws->get_hw_version) {
959 svgascreen->hw_version = sws->get_hw_version(sws);
960 } else {
961 svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
962 }
963
964 if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
965 /* too old for 3D acceleration */
966 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
967 svgascreen->hw_version);
968 goto error2;
969 }
970
971 /*
972 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
973 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
974 * we prefer the later when available.
975 *
976 * This mimics hardware vendors extensions for D3D depth sampling. See also
977 * http://aras-p.info/texts/D3D9GPUHacks.html
978 */
979
980 {
981 boolean has_df16, has_df24, has_d24s8_int;
982 SVGA3dSurfaceFormatCaps caps;
983 SVGA3dSurfaceFormatCaps mask;
984 mask.value = 0;
985 mask.zStencil = 1;
986 mask.texture = 1;
987
988 svgascreen->depth.z16 = SVGA3D_Z_D16;
989 svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
990 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
991
992 svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
993 has_df16 = (caps.value & mask.value) == mask.value;
994
995 svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
996 has_df24 = (caps.value & mask.value) == mask.value;
997
998 svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
999 has_d24s8_int = (caps.value & mask.value) == mask.value;
1000
1001 /* XXX: We might want some other logic here.
1002 * Like if we only have d24s8_int we should
1003 * emulate the other formats with that.
1004 */
1005 if (has_df16) {
1006 svgascreen->depth.z16 = SVGA3D_Z_DF16;
1007 }
1008 if (has_df24) {
1009 svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1010 }
1011 if (has_d24s8_int) {
1012 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1013 }
1014 }
1015
1016 /* Query device caps
1017 */
1018 if (sws->have_vgpu10) {
1019 svgascreen->haveProvokingVertex
1020 = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1021 svgascreen->haveLineSmooth = TRUE;
1022 svgascreen->maxPointSize = 80.0F;
1023 svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1024
1025 /* Multisample samples per pixel */
1026 if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1027 svgascreen->ms_samples =
1028 get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1029 }
1030
1031 /* We only support 4x, 8x, 16x MSAA */
1032 svgascreen->ms_samples &= ((1 << (4-1)) |
1033 (1 << (8-1)) |
1034 (1 << (16-1)));
1035
1036 /* Maximum number of constant buffers */
1037 svgascreen->max_const_buffers =
1038 get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1039 assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1040 }
1041 else {
1042 /* VGPU9 */
1043 unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1044 SVGA3DVSVERSION_NONE);
1045 unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1046 SVGA3DPSVERSION_NONE);
1047
1048 /* we require Shader model 3.0 or later */
1049 if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1050 goto error2;
1051 }
1052
1053 svgascreen->haveProvokingVertex = FALSE;
1054
1055 svgascreen->haveLineSmooth =
1056 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1057
1058 svgascreen->maxPointSize =
1059 get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1060 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1061 svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1062
1063 /* The SVGA3D device always supports 4 targets at this time, regardless
1064 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1065 */
1066 svgascreen->max_color_buffers = 4;
1067
1068 /* Only support one constant buffer
1069 */
1070 svgascreen->max_const_buffers = 1;
1071
1072 /* No multisampling */
1073 svgascreen->ms_samples = 0;
1074 }
1075
1076 /* common VGPU9 / VGPU10 caps */
1077 svgascreen->haveLineStipple =
1078 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1079
1080 svgascreen->maxLineWidth =
1081 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1082
1083 svgascreen->maxLineWidthAA =
1084 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1085
1086 if (0) {
1087 debug_printf("svga: haveProvokingVertex %u\n",
1088 svgascreen->haveProvokingVertex);
1089 debug_printf("svga: haveLineStip %u "
1090 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1091 svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1092 svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1093 debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1094 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1095 }
1096
1097 (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1098 (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1099
1100 svga_screen_cache_init(svgascreen);
1101
1102 init_logging(screen);
1103
1104 return screen;
1105 error2:
1106 FREE(svgascreen);
1107 error1:
1108 return NULL;
1109 }
1110
1111
1112 struct svga_winsys_screen *
svga_winsys_screen(struct pipe_screen * screen)1113 svga_winsys_screen(struct pipe_screen *screen)
1114 {
1115 return svga_screen(screen)->sws;
1116 }
1117
1118
1119 #ifdef DEBUG
1120 struct svga_screen *
svga_screen(struct pipe_screen * screen)1121 svga_screen(struct pipe_screen *screen)
1122 {
1123 assert(screen);
1124 assert(screen->destroy == svga_destroy_screen);
1125 return (struct svga_screen *)screen;
1126 }
1127 #endif
1128