1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __T4020QDS_QIXIS_H__ 7 #define __T4020QDS_QIXIS_H__ 8 9 /* Definitions of QIXIS Registers for T4020QDS */ 10 11 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 12 #define BRDCFG4_EMISEL_MASK 0xE0 13 #define BRDCFG4_EMISEL_SHIFT 5 14 15 /* SYSCLK */ 16 #define QIXIS_SYSCLK_66 0x0 17 #define QIXIS_SYSCLK_83 0x1 18 #define QIXIS_SYSCLK_100 0x2 19 #define QIXIS_SYSCLK_125 0x3 20 #define QIXIS_SYSCLK_133 0x4 21 #define QIXIS_SYSCLK_150 0x5 22 #define QIXIS_SYSCLK_160 0x6 23 #define QIXIS_SYSCLK_166 0x7 24 25 /* DDRCLK */ 26 #define QIXIS_DDRCLK_66 0x0 27 #define QIXIS_DDRCLK_100 0x1 28 #define QIXIS_DDRCLK_125 0x2 29 #define QIXIS_DDRCLK_133 0x3 30 31 #define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ 32 33 #define BRDCFG12_SD3EN_MASK 0x20 34 #define BRDCFG12_SD3MX_MASK 0x08 35 #define BRDCFG12_SD3MX_SLOT5 0x08 36 #define BRDCFG12_SD3MX_SLOT6 0x00 37 #define BRDCFG12_SD4EN_MASK 0x04 38 #define BRDCFG12_SD4MX_MASK 0x03 39 #define BRDCFG12_SD4MX_SLOT7 0x02 40 #define BRDCFG12_SD4MX_SLOT8 0x01 41 #define BRDCFG12_SD4MX_AURO_SATA 0x00 42 #endif 43