1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28
29 #include "common/gen_device_info.h"
30 #include "isl/isl.h"
31 #include "isl/isl_priv.h"
32
33 #define BDW_GT2_DEVID 0x161a
34
35 // An asssert that works regardless of NDEBUG.
36 #define t_assert(cond) \
37 do { \
38 if (!(cond)) { \
39 fprintf(stderr, "%s:%d: assertion failed\n", __FILE__, __LINE__); \
40 abort(); \
41 } \
42 } while (0)
43
44 static void
t_assert_extent4d(const struct isl_extent4d * e,uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)45 t_assert_extent4d(const struct isl_extent4d *e, uint32_t width,
46 uint32_t height, uint32_t depth, uint32_t array_len)
47 {
48 t_assert(e->width == width);
49 t_assert(e->height == height);
50 t_assert(e->depth == depth);
51 t_assert(e->array_len == array_len);
52 }
53
54 static void
t_assert_image_alignment_el(const struct isl_surf * surf,uint32_t w,uint32_t h,uint32_t d)55 t_assert_image_alignment_el(const struct isl_surf *surf,
56 uint32_t w, uint32_t h, uint32_t d)
57 {
58 struct isl_extent3d align_el;
59
60 align_el = isl_surf_get_image_alignment_el(surf);
61 t_assert(align_el.w == w);
62 t_assert(align_el.h == h);
63 t_assert(align_el.d == d);
64
65 }
66
67 static void
t_assert_image_alignment_sa(const struct isl_surf * surf,uint32_t w,uint32_t h,uint32_t d)68 t_assert_image_alignment_sa(const struct isl_surf *surf,
69 uint32_t w, uint32_t h, uint32_t d)
70 {
71 struct isl_extent3d align_sa;
72
73 align_sa = isl_surf_get_image_alignment_sa(surf);
74 t_assert(align_sa.w == w);
75 t_assert(align_sa.h == h);
76 t_assert(align_sa.d == d);
77
78 }
79
80 static void
t_assert_offset_el(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint32_t expected_x_offset_el,uint32_t expected_y_offset_el)81 t_assert_offset_el(const struct isl_surf *surf,
82 uint32_t level,
83 uint32_t logical_array_layer,
84 uint32_t logical_z_offset_px,
85 uint32_t expected_x_offset_el,
86 uint32_t expected_y_offset_el)
87 {
88 uint32_t x, y;
89 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
90 logical_z_offset_px, &x, &y);
91
92 t_assert(x == expected_x_offset_el);
93 t_assert(y == expected_y_offset_el);
94 }
95
96 static void
t_assert_phys_level0_sa(const struct isl_surf * surf,uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)97 t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width,
98 uint32_t height, uint32_t depth, uint32_t array_len)
99 {
100 t_assert_extent4d(&surf->phys_level0_sa, width, height, depth, array_len);
101 }
102
103 static void
t_assert_gen4_3d_layer(const struct isl_surf * surf,uint32_t level,uint32_t aligned_width,uint32_t aligned_height,uint32_t depth,uint32_t horiz_layers,uint32_t vert_layers,uint32_t * base_y)104 t_assert_gen4_3d_layer(const struct isl_surf *surf,
105 uint32_t level,
106 uint32_t aligned_width,
107 uint32_t aligned_height,
108 uint32_t depth,
109 uint32_t horiz_layers,
110 uint32_t vert_layers,
111 uint32_t *base_y)
112 {
113 for (uint32_t z = 0; z < depth; ++z) {
114 t_assert_offset_el(surf, level, 0, z,
115 aligned_width * (z % horiz_layers),
116 *base_y + aligned_height * (z / horiz_layers));
117 }
118
119 *base_y += aligned_height * vert_layers;
120 }
121
122 static void
test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void)123 test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void)
124 {
125 bool ok;
126
127 struct gen_device_info devinfo;
128 t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo));
129
130 struct isl_device dev;
131 isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
132
133 struct isl_surf surf;
134 ok = isl_surf_init(&dev, &surf,
135 .dim = ISL_SURF_DIM_2D,
136 .format = ISL_FORMAT_R8G8B8A8_UNORM,
137 .width = 512,
138 .height = 512,
139 .depth = 1,
140 .levels = 10,
141 .array_len = 1,
142 .samples = 1,
143 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
144 ISL_SURF_USAGE_DISABLE_AUX_BIT,
145 .tiling_flags = ISL_TILING_Y0_BIT);
146 t_assert(ok);
147
148 t_assert_image_alignment_el(&surf, 4, 4, 1);
149 t_assert_image_alignment_sa(&surf, 4, 4, 1);
150 t_assert_phys_level0_sa(&surf, 512, 512, 1, 1);
151 t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 772);
152 t_assert(isl_surf_get_array_pitch_el_rows(&surf) ==
153 isl_surf_get_array_pitch_sa_rows(&surf));
154
155 /* Row pitch should be minimal possible */
156 t_assert(surf.row_pitch == 2048);
157
158 t_assert_offset_el(&surf, 0, 0, 0, 0, 0); // +0, +0
159 t_assert_offset_el(&surf, 1, 0, 0, 0, 512); // +0, +512
160 t_assert_offset_el(&surf, 2, 0, 0, 256, 512); // +256, +0
161 t_assert_offset_el(&surf, 3, 0, 0, 256, 640); // +0, +128
162 t_assert_offset_el(&surf, 4, 0, 0, 256, 704); // +0, +64
163 t_assert_offset_el(&surf, 5, 0, 0, 256, 736); // +0, +32
164 t_assert_offset_el(&surf, 6, 0, 0, 256, 752); // +0, +16
165 t_assert_offset_el(&surf, 7, 0, 0, 256, 760); // +0, +8
166 t_assert_offset_el(&surf, 8, 0, 0, 256, 764); // +0, +4
167 t_assert_offset_el(&surf, 9, 0, 0, 256, 768); // +0, +4
168 }
169
170 static void
test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void)171 test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void)
172 {
173 bool ok;
174
175 struct gen_device_info devinfo;
176 t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo));
177
178 struct isl_device dev;
179 isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
180
181 struct isl_surf surf;
182 ok = isl_surf_init(&dev, &surf,
183 .dim = ISL_SURF_DIM_2D,
184 .format = ISL_FORMAT_R8G8B8A8_UNORM,
185 .width = 1024,
186 .height = 1024,
187 .depth = 1,
188 .levels = 11,
189 .array_len = 6,
190 .samples = 1,
191 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
192 ISL_SURF_USAGE_DISABLE_AUX_BIT,
193 .tiling_flags = ISL_TILING_Y0_BIT);
194 t_assert(ok);
195
196 t_assert_image_alignment_el(&surf, 4, 4, 1);
197 t_assert_image_alignment_sa(&surf, 4, 4, 1);
198
199 t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 1540);
200 t_assert(isl_surf_get_array_pitch_el_rows(&surf) ==
201 isl_surf_get_array_pitch_sa_rows(&surf));
202
203 /* Row pitch should be minimal possible */
204 t_assert(surf.row_pitch == 4096);
205
206 for (uint32_t a = 0; a < 6; ++a) {
207 uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf);
208
209 t_assert_offset_el(&surf, 0, a, 0, 0, b + 0); // +0, +0
210 t_assert_offset_el(&surf, 1, a, 0, 0, b + 1024); // +0, +1024
211 t_assert_offset_el(&surf, 2, a, 0, 512, b + 1024); // +512, +0
212 t_assert_offset_el(&surf, 3, a, 0, 512, b + 1280); // +0, +256
213 t_assert_offset_el(&surf, 4, a, 0, 512, b + 1408); // +0, +128
214 t_assert_offset_el(&surf, 5, a, 0, 512, b + 1472); // +0, +64
215 t_assert_offset_el(&surf, 6, a, 0, 512, b + 1504); // +0, +32
216 t_assert_offset_el(&surf, 7, a, 0, 512, b + 1520); // +0, +16
217 t_assert_offset_el(&surf, 8, a, 0, 512, b + 1528); // +0, +8
218 t_assert_offset_el(&surf, 9, a, 0, 512, b + 1532); // +0, +4
219 t_assert_offset_el(&surf, 10, a, 0, 512, b + 1536); // +0, +4
220
221 }
222
223 /* The layout below assumes a specific array pitch. It will need updating
224 * if isl's array pitch calculations ever change.
225 */
226 t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 1540);
227
228 /* skip the remaining array layers */
229 }
230
231 static void
test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void)232 test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void)
233 {
234 bool ok;
235
236 struct gen_device_info devinfo;
237 t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo));
238
239 struct isl_device dev;
240 isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
241
242 struct isl_surf surf;
243 ok = isl_surf_init(&dev, &surf,
244 .dim = ISL_SURF_DIM_3D,
245 .format = ISL_FORMAT_R8G8B8A8_UNORM,
246 .width = 256,
247 .height = 256,
248 .depth = 256,
249 .levels = 9,
250 .array_len = 1,
251 .samples = 1,
252 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
253 ISL_SURF_USAGE_DISABLE_AUX_BIT,
254 .tiling_flags = ISL_TILING_Y0_BIT);
255 t_assert(ok);
256
257 t_assert_image_alignment_el(&surf, 4, 4, 1);
258 t_assert_image_alignment_sa(&surf, 4, 4, 1);
259 t_assert(isl_surf_get_array_pitch_sa_rows(&surf) ==
260 isl_surf_get_array_pitch_el_rows(&surf));
261
262 uint32_t base_y = 0;
263
264 t_assert_gen4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y);
265 t_assert_gen4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y);
266 t_assert_gen4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y);
267 t_assert_gen4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y);
268 t_assert_gen4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y);
269 t_assert_gen4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y);
270 t_assert_gen4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y);
271 t_assert_gen4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y);
272 t_assert_gen4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y);
273 }
274
main(void)275 int main(void)
276 {
277 /* FINISHME: Add tests for npot sizes */
278 /* FINISHME: Add tests for 1D surfaces */
279
280 test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0();
281 test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0();
282 test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0();
283 }
284