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1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
3 
4 #include <stdio.h>
5 #include <stdlib.h>
6 
7 #include <platform.h>
8 #include <capstone.h>
9 
10 struct platform {
11 	cs_arch arch;
12 	cs_mode mode;
13 	unsigned char *code;
14 	size_t size;
15 	char *comment;
16 	cs_opt_type opt_type;
17 	cs_opt_value opt_value;
18 };
19 
print_string_hex(unsigned char * str,size_t len)20 static void print_string_hex(unsigned char *str, size_t len)
21 {
22 	unsigned char *c;
23 
24 	printf("Code: ");
25 	for (c = str; c < str + len; c++) {
26 		printf("0x%02x ", *c & 0xff);
27 	}
28 	printf("\n");
29 }
30 
test()31 static void test()
32 {
33 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
34 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
35 //#define X86_CODE32 "\x0f\xa7\xc0"	// xstorerng
36 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
37 //#define ARM_CODE "\x04\xe0\x2d\xe5"
38 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
39 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
40 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
41 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
42 #define THUMB_MCLASS "\xef\xf3\x02\x80"
43 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
44 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
45 //#define MIPS_CODE "\x21\x38\x00\x01"
46 //#define MIPS_CODE "\x21\x30\xe6\x70"
47 //#define MIPS_CODE "\x1c\x00\x40\x14"
48 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
49 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
50 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
51 //#define ARM64_CODE "\xe1\x0b\x40\xb9"	// ldr		w1, [sp, #0x8]
52 //#define ARM64_CODE "\x00\x40\x21\x4b"	// 	sub		w0, w0, w1, uxtw
53 //#define ARM64_CODE "\x21\x7c\x02\x9b"	// mul	x1, x1, x2
54 //#define ARM64_CODE "\x20\x74\x0b\xd5"	// dc	zva, x0
55 //#define ARM64_CODE "\x20\xfc\x02\x9b"	// mneg	x0, x1, x2
56 //#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
57 //#define ARM64_CODE "\x21\x7c\x00\x53"
58 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
59 //#define THUMB_CODE "\x0a\xbf" // itet eq
60 //#define X86_CODE32 "\x77\x04"	// ja +6
61 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
62 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
63 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
64 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
65 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
66 
67 	struct platform platforms[] = {
68 		{
69 			CS_ARCH_X86,
70 			CS_MODE_16,
71 			(unsigned char *)X86_CODE16,
72 			sizeof(X86_CODE32) - 1,
73 			"X86 16bit (Intel syntax)"
74 		},
75 		{
76 			CS_ARCH_X86,
77 			CS_MODE_32,
78 			(unsigned char *)X86_CODE32,
79 			sizeof(X86_CODE32) - 1,
80 			"X86 32bit (ATT syntax)",
81 			CS_OPT_SYNTAX,
82 			CS_OPT_SYNTAX_ATT,
83 		},
84 		{
85 			CS_ARCH_X86,
86 			CS_MODE_32,
87 			(unsigned char *)X86_CODE32,
88 			sizeof(X86_CODE32) - 1,
89 			"X86 32 (Intel syntax)"
90 		},
91 		{
92 			CS_ARCH_X86,
93 			CS_MODE_64,
94 			(unsigned char *)X86_CODE64,
95 			sizeof(X86_CODE64) - 1,
96 			"X86 64 (Intel syntax)"
97 		},
98 		{
99 			CS_ARCH_ARM,
100 			CS_MODE_ARM,
101 			(unsigned char *)ARM_CODE,
102 			sizeof(ARM_CODE) - 1,
103 			"ARM"
104 		},
105 		{
106 			CS_ARCH_ARM,
107 			CS_MODE_THUMB,
108 			(unsigned char *)THUMB_CODE2,
109 			sizeof(THUMB_CODE2) - 1,
110 			"THUMB-2"
111 		},
112 		{
113 			CS_ARCH_ARM,
114 			CS_MODE_ARM,
115 			(unsigned char *)ARM_CODE2,
116 			sizeof(ARM_CODE2) - 1,
117 			"ARM: Cortex-A15 + NEON"
118 		},
119 		{
120 			CS_ARCH_ARM,
121 			CS_MODE_THUMB,
122 			(unsigned char *)THUMB_CODE,
123 			sizeof(THUMB_CODE) - 1,
124 			"THUMB"
125 		},
126 		{
127 			CS_ARCH_ARM,
128 			(cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
129 			(unsigned char*)THUMB_MCLASS,
130 			sizeof(THUMB_MCLASS) - 1,
131 			"Thumb-MClass"
132 		},
133 		{
134 			CS_ARCH_ARM,
135 			(cs_mode)(CS_MODE_ARM + CS_MODE_V8),
136 			(unsigned char*)ARMV8,
137 			sizeof(ARMV8) - 1,
138 			"Arm-V8"
139 		},
140 		{
141 			CS_ARCH_MIPS,
142 			(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
143 			(unsigned char *)MIPS_CODE,
144 			sizeof(MIPS_CODE) - 1,
145 			"MIPS-32 (Big-endian)"
146 		},
147 		{
148 			CS_ARCH_MIPS,
149 			(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
150 			(unsigned char *)MIPS_CODE2,
151 			sizeof(MIPS_CODE2) - 1,
152 			"MIPS-64-EL (Little-endian)"
153 		},
154 		{
155 			CS_ARCH_MIPS,
156 			(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
157 			(unsigned char*)MIPS_32R6M,
158 			sizeof(MIPS_32R6M) - 1,
159 			"MIPS-32R6 | Micro (Big-endian)"
160 		},
161 		{
162 			CS_ARCH_MIPS,
163 			(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
164 			(unsigned char*)MIPS_32R6,
165 			sizeof(MIPS_32R6) - 1,
166 			"MIPS-32R6 (Big-endian)"
167 		},
168 		{
169 			CS_ARCH_ARM64,
170 			CS_MODE_ARM,
171 			(unsigned char *)ARM64_CODE,
172 			sizeof(ARM64_CODE) - 1,
173 			"ARM-64"
174 		},
175 		{
176 			CS_ARCH_PPC,
177 			CS_MODE_BIG_ENDIAN,
178 			(unsigned char*)PPC_CODE,
179 			sizeof(PPC_CODE) - 1,
180 			"PPC-64"
181 		},
182 		{
183 			CS_ARCH_SPARC,
184 			CS_MODE_BIG_ENDIAN,
185 			(unsigned char*)SPARC_CODE,
186 			sizeof(SPARC_CODE) - 1,
187 			"Sparc"
188 		},
189 		{
190 			CS_ARCH_SPARC,
191 			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
192 			(unsigned char*)SPARCV9_CODE,
193 			sizeof(SPARCV9_CODE) - 1,
194 			"SparcV9"
195 		},
196 		{
197 			CS_ARCH_SYSZ,
198 			(cs_mode)0,
199 			(unsigned char*)SYSZ_CODE,
200 			sizeof(SYSZ_CODE) - 1,
201 			"SystemZ"
202 		},
203 		{
204 			CS_ARCH_XCORE,
205 			(cs_mode)0,
206 			(unsigned char*)XCORE_CODE,
207 			sizeof(XCORE_CODE) - 1,
208 			"XCore"
209 		},
210 	};
211 
212 	csh handle;
213 	uint64_t address = 0x1000;
214 	cs_insn *all_insn;
215 	cs_detail *detail;
216 	int i;
217 	size_t count;
218 	cs_err err;
219 
220 	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
221 		printf("****************\n");
222 		printf("Platform: %s\n", platforms[i].comment);
223 		err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
224 		if (err) {
225 			printf("Failed on cs_open() with error returned: %u\n", err);
226 			continue;
227 		}
228 
229 		if (platforms[i].opt_type)
230 			cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
231 
232 		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
233 
234 		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn);
235 		if (count) {
236 			size_t j;
237 			int n;
238 
239 			print_string_hex(platforms[i].code, platforms[i].size);
240 			printf("Disasm:\n");
241 
242 			for (j = 0; j < count; j++) {
243 				cs_insn *ins = &(all_insn[j]);
244 				printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
245 						ins->address, ins->mnemonic, ins->op_str,
246 						ins->id, cs_insn_name(handle, ins->id));
247 
248 				// print implicit registers used by this instruction
249 				detail = ins->detail;
250 
251 				if (detail->regs_read_count > 0) {
252 					printf("\tImplicit registers read: ");
253 					for (n = 0; n < detail->regs_read_count; n++) {
254 						printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
255 					}
256 					printf("\n");
257 				}
258 
259 				// print implicit registers modified by this instruction
260 				if (detail->regs_write_count > 0) {
261 					printf("\tImplicit registers modified: ");
262 					for (n = 0; n < detail->regs_write_count; n++) {
263 						printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
264 					}
265 					printf("\n");
266 				}
267 
268 				// print the groups this instruction belong to
269 				if (detail->groups_count > 0) {
270 					printf("\tThis instruction belongs to groups: ");
271 					for (n = 0; n < detail->groups_count; n++) {
272 						printf("%s ", cs_group_name(handle, detail->groups[n]));
273 					}
274 					printf("\n");
275 				}
276 			}
277 
278 			// print out the next offset, after the last insn
279 			printf("0x%" PRIx64 ":\n", all_insn[j-1].address + all_insn[j-1].size);
280 
281 			// free memory allocated by cs_disasm()
282 			cs_free(all_insn, count);
283 		} else {
284 			printf("****************\n");
285 			printf("Platform: %s\n", platforms[i].comment);
286 			print_string_hex(platforms[i].code, platforms[i].size);
287 			printf("ERROR: Failed to disasm given code!\n");
288 		}
289 
290 		printf("\n");
291 
292 		cs_close(&handle);
293 	}
294 }
295 
main()296 int main()
297 {
298 	test();
299 
300 	return 0;
301 }
302