1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
3
4 // This sample code demonstrates the APIs cs_malloc() & cs_disasm_iter().
5 #include <stdio.h>
6 #include <stdlib.h>
7
8 #include <platform.h>
9 #include <capstone.h>
10
11 struct platform {
12 cs_arch arch;
13 cs_mode mode;
14 unsigned char *code;
15 size_t size;
16 char *comment;
17 cs_opt_type opt_type;
18 cs_opt_value opt_value;
19 };
20
print_string_hex(unsigned char * str,size_t len)21 static void print_string_hex(unsigned char *str, size_t len)
22 {
23 unsigned char *c;
24
25 printf("Code: ");
26 for (c = str; c < str + len; c++) {
27 printf("0x%02x ", *c & 0xff);
28 }
29 printf("\n");
30 }
31
test()32 static void test()
33 {
34 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
35 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 //#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
37 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
38 //#define ARM_CODE "\x04\xe0\x2d\xe5"
39 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
40 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
41 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
42 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
43 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
44 //#define MIPS_CODE "\x21\x38\x00\x01"
45 //#define MIPS_CODE "\x21\x30\xe6\x70"
46 //#define MIPS_CODE "\x1c\x00\x40\x14"
47 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
48 //#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
49 //#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
50 //#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
51 //#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
52 //#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2
53 //#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
54 //#define ARM64_CODE "\x21\x7c\x00\x53"
55 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
56 //#define THUMB_CODE "\x0a\xbf" // itet eq
57 //#define X86_CODE32 "\x77\x04" // ja +6
58 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
59 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
60 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
61 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
62 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
63
64 struct platform platforms[] = {
65 {
66 CS_ARCH_X86,
67 CS_MODE_16,
68 (unsigned char *)X86_CODE16,
69 sizeof(X86_CODE32) - 1,
70 "X86 16bit (Intel syntax)"
71 },
72 {
73 CS_ARCH_X86,
74 CS_MODE_32,
75 (unsigned char *)X86_CODE32,
76 sizeof(X86_CODE32) - 1,
77 "X86 32bit (ATT syntax)",
78 CS_OPT_SYNTAX,
79 CS_OPT_SYNTAX_ATT,
80 },
81 {
82 CS_ARCH_X86,
83 CS_MODE_32,
84 (unsigned char *)X86_CODE32,
85 sizeof(X86_CODE32) - 1,
86 "X86 32 (Intel syntax)"
87 },
88 {
89 CS_ARCH_X86,
90 CS_MODE_64,
91 (unsigned char *)X86_CODE64,
92 sizeof(X86_CODE64) - 1,
93 "X86 64 (Intel syntax)"
94 },
95 {
96 CS_ARCH_ARM,
97 CS_MODE_ARM,
98 (unsigned char *)ARM_CODE,
99 sizeof(ARM_CODE) - 1,
100 "ARM"
101 },
102 {
103 CS_ARCH_ARM,
104 CS_MODE_THUMB,
105 (unsigned char *)THUMB_CODE2,
106 sizeof(THUMB_CODE2) - 1,
107 "THUMB-2"
108 },
109 {
110 CS_ARCH_ARM,
111 CS_MODE_ARM,
112 (unsigned char *)ARM_CODE2,
113 sizeof(ARM_CODE2) - 1,
114 "ARM: Cortex-A15 + NEON"
115 },
116 {
117 CS_ARCH_ARM,
118 CS_MODE_THUMB,
119 (unsigned char *)THUMB_CODE,
120 sizeof(THUMB_CODE) - 1,
121 "THUMB"
122 },
123 {
124 CS_ARCH_MIPS,
125 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
126 (unsigned char *)MIPS_CODE,
127 sizeof(MIPS_CODE) - 1,
128 "MIPS-32 (Big-endian)"
129 },
130 {
131 CS_ARCH_MIPS,
132 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
133 (unsigned char *)MIPS_CODE2,
134 sizeof(MIPS_CODE2) - 1,
135 "MIPS-64-EL (Little-endian)"
136 },
137 {
138 CS_ARCH_ARM64,
139 CS_MODE_ARM,
140 (unsigned char *)ARM64_CODE,
141 sizeof(ARM64_CODE) - 1,
142 "ARM-64"
143 },
144 {
145 CS_ARCH_PPC,
146 CS_MODE_BIG_ENDIAN,
147 (unsigned char*)PPC_CODE,
148 sizeof(PPC_CODE) - 1,
149 "PPC-64"
150 },
151 {
152 CS_ARCH_SPARC,
153 CS_MODE_BIG_ENDIAN,
154 (unsigned char*)SPARC_CODE,
155 sizeof(SPARC_CODE) - 1,
156 "Sparc"
157 },
158 {
159 CS_ARCH_SPARC,
160 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
161 (unsigned char*)SPARCV9_CODE,
162 sizeof(SPARCV9_CODE) - 1,
163 "SparcV9"
164 },
165 {
166 CS_ARCH_SYSZ,
167 (cs_mode)0,
168 (unsigned char*)SYSZ_CODE,
169 sizeof(SYSZ_CODE) - 1,
170 "SystemZ"
171 },
172 {
173 CS_ARCH_XCORE,
174 (cs_mode)0,
175 (unsigned char*)XCORE_CODE,
176 sizeof(XCORE_CODE) - 1,
177 "XCore"
178 },
179 };
180
181 csh handle;
182 uint64_t address;
183 cs_insn *insn;
184 cs_detail *detail;
185 int i;
186 cs_err err;
187 const uint8_t *code;
188 size_t size;
189
190 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
191 printf("****************\n");
192 printf("Platform: %s\n", platforms[i].comment);
193 err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
194 if (err) {
195 printf("Failed on cs_open() with error returned: %u\n", err);
196 continue;
197 }
198
199 if (platforms[i].opt_type)
200 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
201
202 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
203
204 // allocate memory for the cache to be used by cs_disasm_iter()
205 insn = cs_malloc(handle);
206
207 print_string_hex(platforms[i].code, platforms[i].size);
208 printf("Disasm:\n");
209
210 address = 0x1000;
211 code = platforms[i].code;
212 size = platforms[i].size;
213 while(cs_disasm_iter(handle, &code, &size, &address, insn)) {
214 int n;
215
216 printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
217 insn->address, insn->mnemonic, insn->op_str,
218 insn->id, cs_insn_name(handle, insn->id));
219
220 // print implicit registers used by this instruction
221 detail = insn->detail;
222
223 if (detail->regs_read_count > 0) {
224 printf("\tImplicit registers read: ");
225 for (n = 0; n < detail->regs_read_count; n++) {
226 printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
227 }
228 printf("\n");
229 }
230
231 // print implicit registers modified by this instruction
232 if (detail->regs_write_count > 0) {
233 printf("\tImplicit registers modified: ");
234 for (n = 0; n < detail->regs_write_count; n++) {
235 printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
236 }
237 printf("\n");
238 }
239
240 // print the groups this instruction belong to
241 if (detail->groups_count > 0) {
242 printf("\tThis instruction belongs to groups: ");
243 for (n = 0; n < detail->groups_count; n++) {
244 printf("%s ", cs_group_name(handle, detail->groups[n]));
245 }
246 printf("\n");
247 }
248 }
249
250 printf("\n");
251
252 // free memory allocated by cs_malloc()
253 cs_free(insn, 1);
254
255 cs_close(&handle);
256 }
257 }
258
main()259 int main()
260 {
261 test();
262
263 return 0;
264 }
265