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1#!/usr/bin/env python2.7
2
3# Copyright 2015, VIXL authors
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9#   * Redistributions of source code must retain the above copyright notice,
10#     this list of conditions and the following disclaimer.
11#   * Redistributions in binary form must reproduce the above copyright notice,
12#     this list of conditions and the following disclaimer in the documentation
13#     and/or other materials provided with the distribution.
14#   * Neither the name of ARM Limited nor the names of its contributors may be
15#     used to endorse or promote products derived from this software without
16#     specific prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
19# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
22# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29import os
30import sys
31import argparse
32import re
33import util
34
35copyright_header = """// Copyright 2015, VIXL authors
36// All rights reserved.
37//
38// Redistribution and use in source and binary forms, with or without
39// modification, are permitted provided that the following conditions are met:
40//
41//   * Redistributions of source code must retain the above copyright notice,
42//     this list of conditions and the following disclaimer.
43//   * Redistributions in binary form must reproduce the above copyright notice,
44//     this list of conditions and the following disclaimer in the documentation
45//     and/or other materials provided with the distribution.
46//   * Neither the name of ARM Limited nor the names of its contributors may be
47//     used to endorse or promote products derived from this software without
48//     specific prior written permission.
49//
50// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
51// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
52// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
53// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
54// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
55// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
56// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
57// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
58// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60
61"""
62
63master_trace_header = """
64// This file holds the expected results for the instructions tested by
65// test-simulator-aarch64.
66//
67// If you update input lists in test-simulator-inputs-aarch64.h, or add a new
68// test to test-simulator-aarch64.cc, please run
69// tools/generate_simulator_traces.py on a reference platform to regenerate
70// this file and trace files.
71//
72
73#ifndef VIXL_TEST_AARCH64_SIMULATOR_TRACES_AARCH64_H_
74#define VIXL_TEST_AARCH64_SIMULATOR_TRACES_AARCH64_H_
75
76extern "C" {
77#include <stdint.h>
78}
79
80// To add a new simulator test to test-simulator-aarch64.cc, add dummy array(s)
81// below to build test-simulator-aarch64 for reference platform. Then, run
82// tools/generate_simulator_traces.py on a reference platform to regenerate this
83// file and traces files.
84
85// ---------------------------------------------------------------------
86// ADD DUMMY ARRAYS FOR NEW SIMULATOR TEST HERE.
87// ---------------------------------------------------------------------
88const uint64_t kExpected_dummy_64[] = {0};
89const size_t kExpectedCount_dummy_64 = 0;
90
91const uint32_t kExpected_dummy_32[] = {0};
92const size_t kExpectedCount_dummy_32 = 0;
93
94// ---------------------------------------------------------------------
95// Simulator test trace output files.
96// ---------------------------------------------------------------------
97"""
98master_trace_footer = """
99#endif  // VIXL_TEST_AARCH64_SIMULATOR_TRACES_AARCH64_H_
100"""
101
102trace_header = """
103// ---------------------------------------------------------------------
104// This file is auto generated using tools/generate_simulator_traces.py.
105//
106// PLEASE DO NOT EDIT.
107// ---------------------------------------------------------------------
108"""
109
110def BuildOptions(root):
111  result = argparse.ArgumentParser(description = 'Simulator test generator.')
112  result.add_argument('--runner', action='store',
113                      default=os.path.join(root, 'obj/latest/test/test-runner'),
114                      help='The test executable to run.')
115  result.add_argument('--aarch32-only', action='store_true')
116  result.add_argument('--aarch64-only', action='store_true')
117  result.add_argument('--out', action='store',
118                      default='test/aarch64/test-simulator-traces-aarch64.h')
119  result.add_argument('--filter', action='store', help='Test regexp filter.')
120  return result.parse_args()
121
122def ShouldGenerateAArch32(args):
123  return (not args.aarch32_only and not args.aarch64_only) or args.aarch32_only
124
125def ShouldGenerateAArch64(args):
126  return (not args.aarch32_only and not args.aarch64_only) or args.aarch64_only
127
128def GetAArch32Filename(test):
129  return test.lower().replace('_', '-') + '.h'
130
131def GetAArch64Filename(test):
132  return test.lower().replace('_', '-') + '-trace-aarch64.h'
133
134if __name__ == '__main__':
135  # $ROOT/tools/generate_simulator_traces.py
136  root_dir = os.path.dirname(os.path.dirname(os.path.abspath(sys.argv[0])))
137  os.chdir(root_dir)
138
139  args = BuildOptions(root_dir)
140
141  # List all tests.
142  status, test_list = util.getstatusoutput(args.runner + ' --list')
143  if status != 0: util.abort('Failed to list all tests')
144
145  if ShouldGenerateAArch64(args):
146    # Run each simulator test (AARCH64_SIM_*) with the --generate_test_trace
147    # option, and use the output to create the traces header (from --out). In
148    # addition, the test-simulator-traces-aarch64.h file, the master trace file,
149    # which includes all other trace files is generated.
150
151    # Create master trace file.
152    master_trace_f = open(args.out, 'w')
153    master_trace_f.write(copyright_header)
154    master_trace_f.write(master_trace_header)
155    master_trace_f.write('\n\n')
156
157    # Find the AArch64 simulator tests.
158    tests = sorted(filter(lambda t: 'AARCH64_SIM_' in t, test_list.split()),
159                   key=lambda t: GetAArch64Filename(t))
160
161    for test in tests:
162      # Strip out 'AARCH64_' to get the name of the test.
163      test_name = test[len('AARCH64_'):]
164      trace_filename = GetAArch64Filename(test_name)
165      if not args.filter or re.compile(args.filter).search(test):
166        # Run each test.
167        print 'Generating trace for ' + test;
168        cmd = ' '.join([args.runner, '--generate_test_trace', test])
169        status, output = util.getstatusoutput(cmd)
170        if status != 0: util.abort('Failed to run ' + cmd + '.')
171
172        # Create a new trace header file.
173        trace_f =  open("test/aarch64/traces/" + trace_filename, 'w')
174        trace_f.write(copyright_header)
175        trace_f.write(trace_header)
176        trace_f.write('\n')
177        trace_f.write("#ifndef VIXL_" + test_name.upper() + "_TRACE_AARCH64_H_\n")
178        trace_f.write("#define VIXL_" + test_name.upper() + "_TRACE_AARCH64_H_\n")
179        trace_f.write('\n')
180        trace_f.write(output)
181        trace_f.write('\n')
182        trace_f.write('\n' + "#endif  // VIXL_"
183                      + test_name.upper() + "_TRACE_AARCH64_H_" + '\n')
184        trace_f.close()
185
186      # Update master trace file.
187      master_trace_f.write(
188          '#include \"aarch64/traces/' + trace_filename + '\"\n')
189
190    # Close master trace file.
191    master_trace_f.write(master_trace_footer)
192    master_trace_f.close()
193
194  if ShouldGenerateAArch32(args):
195    # Run each test (AARCH32_{SIMULATOR,ASSEMBLER}_*) with the
196    # --generate_test_trace option.
197
198    # Find the AArch32 tests.
199    tests = sorted(
200        filter(
201            lambda t: 'AARCH32_SIMULATOR_' in t or ('AARCH32_ASSEMBLER_' in t
202                and not 'AARCH32_ASSEMBLER_NEGATIVE_' in t),
203            test_list.split()),
204        key=lambda t: GetAArch32Filename(t))
205    if args.filter:
206      tests = filter(re.compile(args.filter).search, tests)
207
208    for test in tests:
209      # Run each test.
210      print 'Generating trace for ' + test;
211      # Strip out 'AARCH32_' to get the name of the test.
212      test_name = test[len('AARCH32_'):]
213
214      # An "and" instruction will be called "and_" since we cannot clash with
215      # the C++ operator. Rename "and_" to "and" to keep sane filenames.
216      test_name = test_name.replace('and_', 'and')
217
218      cmd = ' '.join([args.runner, '--generate_test_trace', test])
219      status, output = util.getstatusoutput(cmd)
220      if status != 0: util.abort('Failed to run ' + cmd + '.')
221
222      # Create a new trace header file.
223      trace_filename = GetAArch32Filename(test_name)
224      trace_f =  open("test/aarch32/traces/" + trace_filename, 'w')
225      trace_f.write(copyright_header)
226      trace_f.write(trace_header)
227      trace_f.write('\n')
228      trace_f.write("#ifndef VIXL_" + test_name.upper() + "_H_\n")
229      trace_f.write("#define VIXL_" + test_name.upper() + "_H_\n")
230      trace_f.write('\n')
231      trace_f.write(output)
232      trace_f.write('\n')
233      trace_f.write(
234          '\n' + "#endif  // VIXL_" + test_name.upper() + "_H_" + '\n')
235      trace_f.close()
236
237  print 'Trace generation COMPLETE'
238