1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "os/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_cpu_detect.h"
31 #include "util/u_debug.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_hash_table.h"
35 #include "util/ralloc.h"
36
37 #include <xf86drm.h>
38 #include "drm_fourcc.h"
39 #include "vc4_drm.h"
40 #include "vc4_screen.h"
41 #include "vc4_context.h"
42 #include "vc4_resource.h"
43
44 static const struct debug_named_value debug_options[] = {
45 { "cl", VC4_DEBUG_CL,
46 "Dump command list during creation" },
47 { "surf", VC4_DEBUG_SURFACE,
48 "Dump surface layouts" },
49 { "qpu", VC4_DEBUG_QPU,
50 "Dump generated QPU instructions" },
51 { "qir", VC4_DEBUG_QIR,
52 "Dump QPU IR during program compile" },
53 { "nir", VC4_DEBUG_NIR,
54 "Dump NIR during program compile" },
55 { "tgsi", VC4_DEBUG_TGSI,
56 "Dump TGSI during program compile" },
57 { "shaderdb", VC4_DEBUG_SHADERDB,
58 "Dump program compile information for shader-db analysis" },
59 { "perf", VC4_DEBUG_PERF,
60 "Print during performance-related events" },
61 { "norast", VC4_DEBUG_NORAST,
62 "Skip actual hardware execution of commands" },
63 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
64 "Flush after each draw call" },
65 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
66 "Wait for finish after each flush" },
67 #ifdef USE_VC4_SIMULATOR
68 { "dump", VC4_DEBUG_DUMP,
69 "Write a GPU command stream trace file" },
70 #endif
71 { NULL }
72 };
73
74 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
75 uint32_t vc4_debug;
76
77 static const char *
vc4_screen_get_name(struct pipe_screen * pscreen)78 vc4_screen_get_name(struct pipe_screen *pscreen)
79 {
80 struct vc4_screen *screen = vc4_screen(pscreen);
81
82 if (!screen->name) {
83 screen->name = ralloc_asprintf(screen,
84 "VC4 V3D %d.%d",
85 screen->v3d_ver / 10,
86 screen->v3d_ver % 10);
87 }
88
89 return screen->name;
90 }
91
92 static const char *
vc4_screen_get_vendor(struct pipe_screen * pscreen)93 vc4_screen_get_vendor(struct pipe_screen *pscreen)
94 {
95 return "Broadcom";
96 }
97
98 static void
vc4_screen_destroy(struct pipe_screen * pscreen)99 vc4_screen_destroy(struct pipe_screen *pscreen)
100 {
101 struct vc4_screen *screen = vc4_screen(pscreen);
102
103 util_hash_table_destroy(screen->bo_handles);
104 vc4_bufmgr_destroy(pscreen);
105 slab_destroy_parent(&screen->transfer_pool);
106 free(screen->ro);
107
108 #ifdef USE_VC4_SIMULATOR
109 vc4_simulator_destroy(screen);
110 #endif
111
112 close(screen->fd);
113 ralloc_free(pscreen);
114 }
115
116 static bool
vc4_has_feature(struct vc4_screen * screen,uint32_t feature)117 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
118 {
119 struct drm_vc4_get_param p = {
120 .param = feature,
121 };
122 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
123
124 if (ret != 0)
125 return false;
126
127 return p.value;
128 }
129
130 static int
vc4_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)131 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
132 {
133 struct vc4_screen *screen = vc4_screen(pscreen);
134
135 switch (param) {
136 /* Supported features (boolean caps). */
137 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
139 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
140 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
141 case PIPE_CAP_NPOT_TEXTURES:
142 case PIPE_CAP_SHAREABLE_SHADERS:
143 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
144 case PIPE_CAP_TEXTURE_MULTISAMPLE:
145 case PIPE_CAP_TEXTURE_SWIZZLE:
146 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
147 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
148 case PIPE_CAP_TEXTURE_BARRIER:
149 return 1;
150
151 case PIPE_CAP_TILE_RASTER_ORDER:
152 return vc4_has_feature(screen,
153 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
154
155 /* lying for GL 2.0 */
156 case PIPE_CAP_OCCLUSION_QUERY:
157 case PIPE_CAP_POINT_SPRITE:
158 return 1;
159
160 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
161 return 256;
162
163 case PIPE_CAP_GLSL_FEATURE_LEVEL:
164 return 120;
165
166 case PIPE_CAP_MAX_VIEWPORTS:
167 return 1;
168
169 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
170 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
171 return 1;
172
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
174 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
175 return 1;
176
177 /* Unsupported features. */
178 case PIPE_CAP_ANISOTROPIC_FILTER:
179 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
180 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
181 case PIPE_CAP_CUBE_MAP_ARRAY:
182 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
183 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
184 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
185 case PIPE_CAP_SEAMLESS_CUBE_MAP:
186 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
187 case PIPE_CAP_TGSI_INSTANCEID:
188 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
189 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
190 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
191 case PIPE_CAP_COMPUTE:
192 case PIPE_CAP_START_INSTANCE:
193 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
194 case PIPE_CAP_SHADER_STENCIL_EXPORT:
195 case PIPE_CAP_TGSI_TEXCOORD:
196 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
197 case PIPE_CAP_CONDITIONAL_RENDER:
198 case PIPE_CAP_PRIMITIVE_RESTART:
199 case PIPE_CAP_SM3:
200 case PIPE_CAP_INDEP_BLEND_ENABLE:
201 case PIPE_CAP_INDEP_BLEND_FUNC:
202 case PIPE_CAP_DEPTH_CLIP_DISABLE:
203 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
204 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
206 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
207 case PIPE_CAP_USER_VERTEX_BUFFERS:
208 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
209 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
210 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
211 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
212 case PIPE_CAP_TEXTURE_GATHER_SM5:
213 case PIPE_CAP_FAKE_SW_MSAA:
214 case PIPE_CAP_TEXTURE_QUERY_LOD:
215 case PIPE_CAP_SAMPLE_SHADING:
216 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
217 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
218 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
219 case PIPE_CAP_MAX_TEXEL_OFFSET:
220 case PIPE_CAP_MAX_VERTEX_STREAMS:
221 case PIPE_CAP_DRAW_INDIRECT:
222 case PIPE_CAP_MULTI_DRAW_INDIRECT:
223 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
224 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
225 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
226 case PIPE_CAP_SAMPLER_VIEW_TARGET:
227 case PIPE_CAP_CLIP_HALFZ:
228 case PIPE_CAP_VERTEXID_NOBASE:
229 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
230 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
231 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
232 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
233 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
234 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
235 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
236 case PIPE_CAP_DEPTH_BOUNDS_TEST:
237 case PIPE_CAP_TGSI_TXQS:
238 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
239 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
240 case PIPE_CAP_CLEAR_TEXTURE:
241 case PIPE_CAP_DRAW_PARAMETERS:
242 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
243 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
244 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
245 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
246 case PIPE_CAP_INVALIDATE_BUFFER:
247 case PIPE_CAP_GENERATE_MIPMAP:
248 case PIPE_CAP_STRING_MARKER:
249 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
250 case PIPE_CAP_QUERY_BUFFER_OBJECT:
251 case PIPE_CAP_QUERY_MEMORY_INFO:
252 case PIPE_CAP_PCI_GROUP:
253 case PIPE_CAP_PCI_BUS:
254 case PIPE_CAP_PCI_DEVICE:
255 case PIPE_CAP_PCI_FUNCTION:
256 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
257 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
258 case PIPE_CAP_CULL_DISTANCE:
259 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
260 case PIPE_CAP_TGSI_VOTE:
261 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
262 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
263 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
264 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
265 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
266 case PIPE_CAP_NATIVE_FENCE_FD:
267 case PIPE_CAP_TGSI_FS_FBFETCH:
268 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
269 case PIPE_CAP_DOUBLES:
270 case PIPE_CAP_INT64:
271 case PIPE_CAP_INT64_DIVMOD:
272 case PIPE_CAP_TGSI_TEX_TXF_LZ:
273 case PIPE_CAP_TGSI_CLOCK:
274 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
275 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
276 case PIPE_CAP_TGSI_BALLOT:
277 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
278 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
279 case PIPE_CAP_POST_DEPTH_COVERAGE:
280 case PIPE_CAP_BINDLESS_TEXTURE:
281 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
282 case PIPE_CAP_QUERY_SO_OVERFLOW:
283 case PIPE_CAP_MEMOBJ:
284 case PIPE_CAP_LOAD_CONSTBUF:
285 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
286 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
287 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
288 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
289 return 0;
290
291 /* Stream output. */
292 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
293 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
294 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
295 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
296 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
297 return 0;
298
299 /* Geometry shader output, unsupported. */
300 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
301 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
302 return 0;
303
304 /* Texturing. */
305 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
306 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
307 return VC4_MAX_MIP_LEVELS;
308 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
309 /* Note: Not supported in hardware, just faking it. */
310 return 5;
311 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
312 return 0;
313
314 /* Render targets. */
315 case PIPE_CAP_MAX_RENDER_TARGETS:
316 return 1;
317
318 /* Queries. */
319 case PIPE_CAP_QUERY_TIME_ELAPSED:
320 case PIPE_CAP_QUERY_TIMESTAMP:
321 return 0;
322
323 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
324 case PIPE_CAP_MIN_TEXEL_OFFSET:
325 return 0;
326
327 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
328 return 2048;
329
330 case PIPE_CAP_ENDIANNESS:
331 return PIPE_ENDIAN_LITTLE;
332
333 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
334 return 64;
335
336 case PIPE_CAP_VENDOR_ID:
337 return 0x14E4;
338 case PIPE_CAP_DEVICE_ID:
339 return 0xFFFFFFFF;
340 case PIPE_CAP_ACCELERATED:
341 return 1;
342 case PIPE_CAP_VIDEO_MEMORY: {
343 uint64_t system_memory;
344
345 if (!os_get_total_physical_memory(&system_memory))
346 return 0;
347
348 return (int)(system_memory >> 20);
349 }
350 case PIPE_CAP_UMA:
351 return 1;
352
353 default:
354 fprintf(stderr, "unknown param %d\n", param);
355 return 0;
356 }
357 }
358
359 static float
vc4_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)360 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
361 {
362 switch (param) {
363 case PIPE_CAPF_MAX_LINE_WIDTH:
364 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
365 return 32;
366
367 case PIPE_CAPF_MAX_POINT_WIDTH:
368 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
369 return 512.0f;
370
371 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
372 return 0.0f;
373 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
374 return 0.0f;
375 case PIPE_CAPF_GUARD_BAND_LEFT:
376 case PIPE_CAPF_GUARD_BAND_TOP:
377 case PIPE_CAPF_GUARD_BAND_RIGHT:
378 case PIPE_CAPF_GUARD_BAND_BOTTOM:
379 return 0.0f;
380 default:
381 fprintf(stderr, "unknown paramf %d\n", param);
382 return 0;
383 }
384 }
385
386 static int
vc4_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)387 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
388 enum pipe_shader_type shader,
389 enum pipe_shader_cap param)
390 {
391 if (shader != PIPE_SHADER_VERTEX &&
392 shader != PIPE_SHADER_FRAGMENT) {
393 return 0;
394 }
395
396 /* this is probably not totally correct.. but it's a start: */
397 switch (param) {
398 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
399 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
400 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
401 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
402 return 16384;
403
404 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
405 return vc4_screen(pscreen)->has_control_flow;
406
407 case PIPE_SHADER_CAP_MAX_INPUTS:
408 return 8;
409 case PIPE_SHADER_CAP_MAX_OUTPUTS:
410 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
411 case PIPE_SHADER_CAP_MAX_TEMPS:
412 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
413 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
414 return 16 * 1024 * sizeof(float);
415 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
416 return 1;
417 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
418 return 0;
419 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
420 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
421 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
422 return 0;
423 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
424 return 1;
425 case PIPE_SHADER_CAP_SUBROUTINES:
426 return 0;
427 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
428 return 0;
429 case PIPE_SHADER_CAP_INTEGERS:
430 return 1;
431 case PIPE_SHADER_CAP_INT64_ATOMICS:
432 case PIPE_SHADER_CAP_FP16:
433 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
434 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
435 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
436 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
437 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
438 return 0;
439 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
440 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
441 return VC4_MAX_TEXTURE_SAMPLERS;
442 case PIPE_SHADER_CAP_PREFERRED_IR:
443 return PIPE_SHADER_IR_NIR;
444 case PIPE_SHADER_CAP_SUPPORTED_IRS:
445 return 0;
446 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
447 return 32;
448 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
449 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
450 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
451 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
452 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
453 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
454 return 0;
455 default:
456 fprintf(stderr, "unknown shader param %d\n", param);
457 return 0;
458 }
459 return 0;
460 }
461
462 static boolean
vc4_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned usage)463 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
464 enum pipe_format format,
465 enum pipe_texture_target target,
466 unsigned sample_count,
467 unsigned usage)
468 {
469 struct vc4_screen *screen = vc4_screen(pscreen);
470 unsigned retval = 0;
471
472 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
473 return FALSE;
474
475 if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
476 !util_format_is_supported(format, usage)) {
477 return FALSE;
478 }
479
480 if (usage & PIPE_BIND_VERTEX_BUFFER) {
481 switch (format) {
482 case PIPE_FORMAT_R32G32B32A32_FLOAT:
483 case PIPE_FORMAT_R32G32B32_FLOAT:
484 case PIPE_FORMAT_R32G32_FLOAT:
485 case PIPE_FORMAT_R32_FLOAT:
486 case PIPE_FORMAT_R32G32B32A32_SNORM:
487 case PIPE_FORMAT_R32G32B32_SNORM:
488 case PIPE_FORMAT_R32G32_SNORM:
489 case PIPE_FORMAT_R32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_SSCALED:
491 case PIPE_FORMAT_R32G32B32_SSCALED:
492 case PIPE_FORMAT_R32G32_SSCALED:
493 case PIPE_FORMAT_R32_SSCALED:
494 case PIPE_FORMAT_R16G16B16A16_UNORM:
495 case PIPE_FORMAT_R16G16B16_UNORM:
496 case PIPE_FORMAT_R16G16_UNORM:
497 case PIPE_FORMAT_R16_UNORM:
498 case PIPE_FORMAT_R16G16B16A16_SNORM:
499 case PIPE_FORMAT_R16G16B16_SNORM:
500 case PIPE_FORMAT_R16G16_SNORM:
501 case PIPE_FORMAT_R16_SNORM:
502 case PIPE_FORMAT_R16G16B16A16_USCALED:
503 case PIPE_FORMAT_R16G16B16_USCALED:
504 case PIPE_FORMAT_R16G16_USCALED:
505 case PIPE_FORMAT_R16_USCALED:
506 case PIPE_FORMAT_R16G16B16A16_SSCALED:
507 case PIPE_FORMAT_R16G16B16_SSCALED:
508 case PIPE_FORMAT_R16G16_SSCALED:
509 case PIPE_FORMAT_R16_SSCALED:
510 case PIPE_FORMAT_R8G8B8A8_UNORM:
511 case PIPE_FORMAT_R8G8B8_UNORM:
512 case PIPE_FORMAT_R8G8_UNORM:
513 case PIPE_FORMAT_R8_UNORM:
514 case PIPE_FORMAT_R8G8B8A8_SNORM:
515 case PIPE_FORMAT_R8G8B8_SNORM:
516 case PIPE_FORMAT_R8G8_SNORM:
517 case PIPE_FORMAT_R8_SNORM:
518 case PIPE_FORMAT_R8G8B8A8_USCALED:
519 case PIPE_FORMAT_R8G8B8_USCALED:
520 case PIPE_FORMAT_R8G8_USCALED:
521 case PIPE_FORMAT_R8_USCALED:
522 case PIPE_FORMAT_R8G8B8A8_SSCALED:
523 case PIPE_FORMAT_R8G8B8_SSCALED:
524 case PIPE_FORMAT_R8G8_SSCALED:
525 case PIPE_FORMAT_R8_SSCALED:
526 retval |= PIPE_BIND_VERTEX_BUFFER;
527 break;
528 default:
529 break;
530 }
531 }
532
533 if ((usage & PIPE_BIND_RENDER_TARGET) &&
534 vc4_rt_format_supported(format)) {
535 retval |= PIPE_BIND_RENDER_TARGET;
536 }
537
538 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
539 vc4_tex_format_supported(format) &&
540 (format != PIPE_FORMAT_ETC1_RGB8 || screen->has_etc1)) {
541 retval |= PIPE_BIND_SAMPLER_VIEW;
542 }
543
544 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
545 (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
546 format == PIPE_FORMAT_X8Z24_UNORM)) {
547 retval |= PIPE_BIND_DEPTH_STENCIL;
548 }
549
550 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
551 (format == PIPE_FORMAT_I8_UINT ||
552 format == PIPE_FORMAT_I16_UINT)) {
553 retval |= PIPE_BIND_INDEX_BUFFER;
554 }
555
556 #if 0
557 if (retval != usage) {
558 fprintf(stderr,
559 "not supported: format=%s, target=%d, sample_count=%d, "
560 "usage=0x%x, retval=0x%x\n", util_format_name(format),
561 target, sample_count, usage, retval);
562 }
563 #endif
564
565 return retval == usage;
566 }
567
568 static void
vc4_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)569 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
570 enum pipe_format format, int max,
571 uint64_t *modifiers,
572 unsigned int *external_only,
573 int *count)
574 {
575 int m, i;
576 uint64_t available_modifiers[] = {
577 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
578 DRM_FORMAT_MOD_LINEAR,
579 };
580 struct vc4_screen *screen = vc4_screen(pscreen);
581 int num_modifiers = screen->has_tiling_ioctl ? 2 : 1;
582
583 if (!modifiers) {
584 *count = num_modifiers;
585 return;
586 }
587
588 *count = MIN2(max, num_modifiers);
589 m = screen->has_tiling_ioctl ? 0 : 1;
590 /* We support both modifiers (tiled and linear) for all sampler
591 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
592 * we shouldn't advertise the tiled formats.
593 */
594 for (i = 0; i < *count; i++) {
595 modifiers[i] = available_modifiers[m++];
596 if (external_only)
597 external_only[i] = false;
598 }
599 }
600
601 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
602
handle_hash(void * key)603 static unsigned handle_hash(void *key)
604 {
605 return PTR_TO_UINT(key);
606 }
607
handle_compare(void * key1,void * key2)608 static int handle_compare(void *key1, void *key2)
609 {
610 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
611 }
612
613 static bool
vc4_get_chip_info(struct vc4_screen * screen)614 vc4_get_chip_info(struct vc4_screen *screen)
615 {
616 struct drm_vc4_get_param ident0 = {
617 .param = DRM_VC4_PARAM_V3D_IDENT0,
618 };
619 struct drm_vc4_get_param ident1 = {
620 .param = DRM_VC4_PARAM_V3D_IDENT1,
621 };
622 int ret;
623
624 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
625 if (ret != 0) {
626 if (errno == EINVAL) {
627 /* Backwards compatibility with 2835 kernels which
628 * only do V3D 2.1.
629 */
630 screen->v3d_ver = 21;
631 return true;
632 } else {
633 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
634 strerror(errno));
635 return false;
636 }
637 }
638 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
639 if (ret != 0) {
640 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
641 strerror(errno));
642 return false;
643 }
644
645 uint32_t major = (ident0.value >> 24) & 0xff;
646 uint32_t minor = (ident1.value >> 0) & 0xf;
647 screen->v3d_ver = major * 10 + minor;
648
649 if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
650 fprintf(stderr,
651 "V3D %d.%d not supported by this version of Mesa.\n",
652 screen->v3d_ver / 10,
653 screen->v3d_ver % 10);
654 return false;
655 }
656
657 return true;
658 }
659
660 struct pipe_screen *
vc4_screen_create(int fd,struct renderonly * ro)661 vc4_screen_create(int fd, struct renderonly *ro)
662 {
663 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
664 struct pipe_screen *pscreen;
665
666 pscreen = &screen->base;
667
668 pscreen->destroy = vc4_screen_destroy;
669 pscreen->get_param = vc4_screen_get_param;
670 pscreen->get_paramf = vc4_screen_get_paramf;
671 pscreen->get_shader_param = vc4_screen_get_shader_param;
672 pscreen->context_create = vc4_context_create;
673 pscreen->is_format_supported = vc4_screen_is_format_supported;
674
675 screen->fd = fd;
676 if (ro) {
677 screen->ro = renderonly_dup(ro);
678 if (!screen->ro) {
679 fprintf(stderr, "Failed to dup renderonly object\n");
680 ralloc_free(screen);
681 return NULL;
682 }
683 }
684
685 list_inithead(&screen->bo_cache.time_list);
686 (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
687 screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
688
689 screen->has_control_flow =
690 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
691 screen->has_etc1 =
692 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
693 screen->has_threaded_fs =
694 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
695 screen->has_madvise =
696 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
697
698 if (!vc4_get_chip_info(screen))
699 goto fail;
700
701 util_cpu_detect();
702
703 slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
704
705 vc4_fence_init(screen);
706
707 vc4_debug = debug_get_option_vc4_debug();
708 if (vc4_debug & VC4_DEBUG_SHADERDB)
709 vc4_debug |= VC4_DEBUG_NORAST;
710
711 #ifdef USE_VC4_SIMULATOR
712 vc4_simulator_init(screen);
713 #endif
714
715 vc4_resource_screen_init(pscreen);
716
717 pscreen->get_name = vc4_screen_get_name;
718 pscreen->get_vendor = vc4_screen_get_vendor;
719 pscreen->get_device_vendor = vc4_screen_get_vendor;
720 pscreen->get_compiler_options = vc4_screen_get_compiler_options;
721 pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
722
723 return pscreen;
724
725 fail:
726 close(fd);
727 ralloc_free(pscreen);
728 return NULL;
729 }
730