1 /******************************************************************************* 2 * Copyright (C) 2018 Cadence Design Systems, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to use this Software with Cadence processor cores only and 7 * not with any other processors and platforms, subject to 8 * the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included 11 * in all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 16 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 17 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 18 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 19 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 21 ******************************************************************************/ 22 23 #ifndef XTENSA_DEFS_H 24 #define XTENSA_DEFS_H 25 26 #include <xtensa/specreg.h> 27 #include <xtensa/config/core-isa.h> 28 #include <xtensa/corebits.h> 29 30 #define _AREG0 256 31 32 #define STACK_SIZE 1024 33 #define DEBUG_PC (EPC + XCHAL_DEBUGLEVEL) 34 #define DEBUG_EXCSAVE (EXCSAVE + XCHAL_DEBUGLEVEL) 35 #define DEBUG_PS (EPS + XCHAL_DEBUGLEVEL) 36 37 #endif /* XTENSA_DEFS_H */ 38