| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 95 registers_.push_back(new mips::Register(mips::A0)); in SetUpHelpers()
128 secondary_register_names_.emplace(mips::Register(mips::A0), "a0"); in SetUpHelpers()
280 __ LoadQFromOffset(mips::F0, mips::A0, 0); in TEST_F()
281 __ LoadQFromOffset(mips::F0, mips::A0, 1); in TEST_F()
282 __ LoadQFromOffset(mips::F0, mips::A0, 2); in TEST_F()
283 __ LoadQFromOffset(mips::F0, mips::A0, 4); in TEST_F()
284 __ LoadQFromOffset(mips::F0, mips::A0, 8); in TEST_F()
285 __ LoadQFromOffset(mips::F0, mips::A0, 511); in TEST_F()
286 __ LoadQFromOffset(mips::F0, mips::A0, 512); in TEST_F()
287 __ LoadQFromOffset(mips::F0, mips::A0, 513); in TEST_F()
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| D | assembler_mips32r6_test.cc | 108 registers_.push_back(new mips::Register(mips::A0)); in SetUpHelpers()
141 secondary_register_names_.emplace(mips::Register(mips::A0), "a0"); in SetUpHelpers()
324 (Base::GetAssembler()->*f)(mips::A0, &label, is_bare); in BranchCondOneRegHelper()
358 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label, is_bare); in BranchCondTwoRegsHelper()
673 __ LoadDFromOffset(mips::F0, mips::A0, -0x8000); in TEST_F()
674 __ LoadDFromOffset(mips::F0, mips::A0, +0); in TEST_F()
675 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FF8); in TEST_F()
676 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFB); in TEST_F()
677 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFC); in TEST_F()
678 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFF); in TEST_F()
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| D | assembler_mips_test.cc | 76 registers_.push_back(new mips::Register(mips::A0)); in SetUpHelpers()
109 secondary_register_names_.emplace(mips::Register(mips::A0), "a0"); in SetUpHelpers()
253 (Base::GetAssembler()->*f)(mips::A0, &label, is_bare); in BranchCondOneRegHelper()
287 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label, is_bare); in BranchCondTwoRegsHelper()
1028 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x8000); in TEST_F()
1029 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0); in TEST_F()
1030 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FF8); in TEST_F()
1031 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFB); in TEST_F()
1032 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFC); in TEST_F()
1033 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFF); in TEST_F()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 106 registers_.push_back(new mips64::GpuRegister(mips64::A0)); in SetUpHelpers()
139 secondary_register_names_.emplace(mips64::GpuRegister(mips64::A0), "a0"); in SetUpHelpers()
316 (Base::GetAssembler()->*f)(mips64::A0, &label, is_bare); in BranchCondOneRegHelper()
349 (Base::GetAssembler()->*f)(mips64::A0, mips64::A1, &label, is_bare); in BranchCondTwoRegsHelper()
952 __ Beqc(mips64::A0, mips64::A1, &label); in TEST_F()
997 __ Beqzc(mips64::A0, &label); in TEST_F()
1548 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A0, 0); in TEST_F()
1549 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0); in TEST_F()
1550 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1); in TEST_F()
1551 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 256); in TEST_F()
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| D | managed_register_mips64_test.cc | 53 reg = Mips64ManagedRegister::FromGpuRegister(A0); in TEST()
58 EXPECT_EQ(A0, reg.AsGpuRegister()); in TEST()
222 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
283 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
301 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
319 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
337 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
355 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
373 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
391 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
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| D | assembler_mips64.cc | 4087 Move(A0, exception->scratch_.AsGpuRegister()); in EmitExceptionPoll()
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 146 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value()); in CreateTrampoline()
149 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value()); in CreateTrampoline()
178 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value()); in CreateTrampoline()
181 __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset(8).Int32Value()); in CreateTrampoline()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 39 static const Register kJniCoreArgumentRegisters[] = { A0, A1, A2, A3 };
47 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
115 return MipsManagedRegister::FromCoreRegister(A0); in MethodRegister()
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| /art/runtime/arch/mips64/ |
| D | context_mips64.cc | 33 gprs_[A0] = &arg0_; in Reset()
77 gprs_[A0] = nullptr; in SmashCallerSaves()
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| D | context_mips64.h | 83 SetGPR(A0, new_arg0_value); in SetArg0()
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| D | registers_mips64.h | 32 A0 = 4, // Arguments. enumerator
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| D | fault_handler_mips64.cc | 58 *out_method = reinterpret_cast<ArtMethod*>(sc->sc_regs[mips64::A0]); in GetMethodAndReturnPcAndSp()
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| D | callee_save_frame_mips64.h | 45 (1 << art::mips64::A0) | (1 << art::mips64::A1) | (1 << art::mips64::A2) |
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 32 A0, A1, A2, A3, A4, A5, A6, A7
100 return Mips64ManagedRegister::FromGpuRegister(A0); in MethodRegister()
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| /art/runtime/arch/mips/ |
| D | context_mips.h | 83 SetGPR(A0, new_arg0_value); in SetArg0()
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| D | registers_mips.h | 32 A0 = 4, // Arguments. enumerator
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| D | fault_handler_mips.cc | 57 *out_method = reinterpret_cast<ArtMethod*>(sc->sc_regs[mips::A0]); in GetMethodAndReturnPcAndSp()
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| D | context_mips.cc | 33 gprs_[A0] = &arg0_; in Reset()
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| D | callee_save_frame_mips.h | 59 (1 << art::mips::A0) | (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) |
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| D | quick_entrypoints_mips.S | 998 li $t6, 0 # t6 = gpr_index = 0 (corresponds to A2; A0 and A1 are skipped)
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| /art/compiler/optimizing/ |
| D | optimizing_cfi_test.cc | 236 __ Beqz(mips::A0, &target); in TEST_F()
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| D | code_generator_mips64.h | 44 { A0, A1, A2, A3, A4, A5, A6, A7 };
115 return Location::RegisterLocation(A0); in GetFieldIndexLocation()
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| D | code_generator_mips.h | 46 { A0, A1, A2, A3 };
117 return Location::RegisterLocation(A0); in GetFieldIndexLocation()
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| D | intrinsics_mips64.cc | 111 invoke_->AsInvokeStaticOrDirect(), Location::RegisterLocation(A0), this); in EmitNativeCode()
114 invoke_->AsInvokeVirtual(), Location::RegisterLocation(A0), this); in EmitNativeCode()
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| D | intrinsics_mips.cc | 122 invoke_->AsInvokeStaticOrDirect(), Location::RegisterLocation(A0), this); in EmitNativeCode()
125 invoke_->AsInvokeVirtual(), Location::RegisterLocation(A0), this); in EmitNativeCode()
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