Searched refs:LR (Results 1 – 12 of 12) sorted by relevance
41 LR = 30 enumerator51 } else if (reg.GetCode() == LR) { in AppendRegisterNameToOutput()
48 LR = 14, enumerator
32 (1 << art::arm::LR);
673 ldr lr, [sp, #56] @ Load LR from gprs_, 56 = 4 * 14.
68 LR = X30, enumerator
36 (1 << art::arm64::LR);
74 Arm64ManagedRegister::FromXRegister(LR),
98 uint32_t result = 1 << LR; in CalculateCoreCalleeSpillMask()
89 RegList core_spill_mask = 1 << LR; in BuildFrame()148 RegList core_spill_mask = 1 << LR; in RemoveFrame()
631 EXPECT_TRUE(vixl::aarch64::lr.Is(Arm64Assembler::reg_x(LR))); in TEST()
195 DCHECK_NE(tmp_.reg(), LR); in EmitNativeCode()
1876 AddAllocatedRegister(Location::RegisterLocation(LR)); in CodeGeneratorARMVIXL()2029 blocked_core_registers_[LR] = true; in SetupBlockedRegisters()