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Searched refs:Mul (Results 1 – 15 of 15) sorted by relevance

/art/test/411-optimizing-arith/src/
DMulTest.java83 expectEquals(15, $opt$Mul(5, 3)); in mulInt()
84 expectEquals(0, $opt$Mul(0, 0)); in mulInt()
85 expectEquals(0, $opt$Mul(0, 3)); in mulInt()
86 expectEquals(0, $opt$Mul(3, 0)); in mulInt()
87 expectEquals(-3, $opt$Mul(1, -3)); in mulInt()
88 expectEquals(36, $opt$Mul(-12, -3)); in mulInt()
89 expectEquals(33, $opt$Mul(1, 3) * 11); in mulInt()
90 expectEquals(671088645, $opt$Mul(134217729, 5)); // (2^27 + 1) * 5 in mulInt()
94 expectEquals(15L, $opt$Mul(5L, 3L)); in mulLong()
95 expectEquals(0L, $opt$Mul(0L, 0L)); in mulLong()
[all …]
/art/test/660-clinit/src/
DMain.java38 expectNotPreInit(Mul.class); in main()
175 static Class<?> klazz[] = new Class<?>[]{Add.class, Mul.class};
186 class Mul { class
/art/test/475-simplify-mul-zero/
Dinfo.txt2 Mul should expect zero constant as input.
/art/test/594-checker-irreducible-linorder/smali/
DIrreducibleLoop.smali23 ## CHECK-DAG: Mul loop:<<Loop:B\d+>>
28 ## CHECK-DAG: Mul liveness:<<LHeader:\d+>>
72 ## CHECK-DAG: Mul loop:<<Loop:B\d+>>
76 ## CHECK-DAG: Mul liveness:<<LPreEntry2:\d+>>
/art/compiler/utils/arm/
Dassembler_arm_vixl.h118 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul() function
119 MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm); in Mul()
121 using MacroAssembler::Mul;
/art/runtime/interpreter/
Dsafe_math_test.cc96 TEST(SafeMath, Mul) { in TEST() argument
/art/compiler/optimizing/
Dscheduler_arm.h77 M(Mul , unused) \
Dscheduler_arm64.h76 M(Mul , unused) \
Dcode_generator_vector_arm64.cc608 __ Mul(dst.V16B(), lhs.V16B(), rhs.V16B()); in VisitVecMul() local
613 __ Mul(dst.V8H(), lhs.V8H(), rhs.V8H()); in VisitVecMul() local
617 __ Mul(dst.V4S(), lhs.V4S(), rhs.V4S()); in VisitVecMul() local
Dnodes.h1419 M(Mul, BinaryOperation) \
5023 DECLARE_INSTRUCTION(Mul);
5026 DEFAULT_COPY_CONSTRUCTOR(Mul);
Dcode_generator_arm_vixl.cc3899 __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1)); in VisitMul() local
3925 __ Mul(temp, in1_lo, in2_hi); in VisitMul() local
Dcode_generator_arm64.cc4950 __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1)); in VisitMul() local
/art/test/596-checker-dead-phi/smali/
DIrreducibleLoop.smali30 ## CHECK-DAG: Mul liveness:<<LPreEntry2:\d+>>
/art/test/485-checker-dce-loop-update/smali/
DTestCase.smali142 ## CHECK-DAG: <<Mul9:i\d+>> Mul [<<PhiX>>,<<Cst11>>] loop:<<HeaderY>>
158 ## CHECK-DAG: <<Mul9:i\d+>> Mul [<<PhiX>>,<<Cst11>>] loop:none
174 ## CHECK-DAG: <<Mul9:i\d+>> Mul [<<PhiX>>,<<Cst11>>] loop:none
/art/test/510-checker-try-catch/smali/
DSsaBuilder.smali214 ## CHECK-NOT: Mul