| /art/runtime/interpreter/ |
| D | safe_math.h | 27 template <typename T1, typename T2>
29 typedef typename std::conditional<sizeof(T1) >= sizeof(T2), T1, T2>::type type;
33 template<template <typename OpT> class Op, typename T1, typename T2>
34 static inline typename select_bigger<T1, T2>::type SafeMath(T1 a, T2 b) { in SafeMath()
35 typedef typename select_bigger<T1, T2>::type biggest_T; in SafeMath()
37 static_assert(std::is_signed<T1>::value, "Expected T1 to be signed"); in SafeMath()
45 template<typename T1, typename T2>
46 static inline typename select_bigger<T1, T2>::type SafeAdd(T1 a, T2 b) { in SafeAdd()
51 template<typename T1, typename T2>
52 static inline typename select_bigger<T1, T2>::type SafeSub(T1 a, T2 b) { in SafeSub()
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| /art/test/1962-multi-thread-events/src/art/ |
| D | Test1962.java | 55 Thread T1 = new Thread(threadRun, "T1 Thread"); in doTest() local
57 T1.start(); in doTest()
63 setupThread(T1, t1Events, target); in doTest()
68 T1.join(); in doTest()
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| /art/test/1962-multi-thread-events/ |
| D | expected.txt | 2 Hit event on T1 Thread
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 81 registers_.push_back(new mips::Register(mips::T1)); in SetUpHelpers()
114 secondary_register_names_.emplace(mips::Register(mips::T1), "t1"); in SetUpHelpers()
2313 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
2318 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
2321 __ Or(mips::T1, mips::T2, mips::T3); in TEST_F()
2322 __ Bne(mips::T2, mips::T1, &label1); // T1 dependency. in TEST_F()
2324 __ And(mips::T0, mips::T1, mips::T2); in TEST_F()
2325 __ Blt(mips::T1, mips::T0, &label1); // T0 dependency. in TEST_F()
2327 __ Xor(mips::AT, mips::T0, mips::T1); in TEST_F()
2328 __ Bge(mips::T1, mips::T0, &label1); // AT dependency. in TEST_F()
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| D | assembler_mips32r6_test.cc | 113 registers_.push_back(new mips::Register(mips::T1)); in SetUpHelpers()
146 secondary_register_names_.emplace(mips::Register(mips::T1), "t1"); in SetUpHelpers()
1509 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1514 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1519 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1524 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1604 __ Addiu(mips::T0, mips::T1, 0x5678, &patcher_label1); in TEST_F()
1615 __ Addiu(mips::T0, mips::T1, 0x5678, &patcher_label2); in TEST_F()
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| D | assembler_mips32r5_test.cc | 100 registers_.push_back(new mips::Register(mips::T1)); in SetUpHelpers()
133 secondary_register_names_.emplace(mips::Register(mips::T1), "t1"); in SetUpHelpers()
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| /art/runtime/verifier/ |
| D | verifier_deps.cc | 619 template<typename T1, typename T2>
620 static inline void EncodeTuple(std::vector<uint8_t>* out, const std::tuple<T1, T2>& t) { in EncodeTuple() argument
625 template<typename T1, typename T2>
626 static inline void DecodeTuple(const uint8_t** in, const uint8_t* end, std::tuple<T1, T2>* t) { in DecodeTuple() argument
627 T1 v1 = Decode<T1>(DecodeUint32WithOverflowCheck(in, end)); in DecodeTuple()
632 template<typename T1, typename T2, typename T3>
633 static inline void EncodeTuple(std::vector<uint8_t>* out, const std::tuple<T1, T2, T3>& t) { in EncodeTuple() argument
639 template<typename T1, typename T2, typename T3>
640 static inline void DecodeTuple(const uint8_t** in, const uint8_t* end, std::tuple<T1, T2, T3>* t) { in DecodeTuple() argument
641 T1 v1 = Decode<T1>(DecodeUint32WithOverflowCheck(in, end)); in DecodeTuple()
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 37 T1 = 9, enumerator
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| D | callee_save_frame_mips.h | 38 (1 << art::mips::T1);
60 (1 << art::mips::T0) | (1 << art::mips::T1) | (1 << art::mips::T2) | (1 << art::mips::T3) |
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| D | context_mips.cc | 89 gprs_[T1] = nullptr; in SmashCallerSaves()
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 41 T1 = 13, enumerator
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| D | callee_save_frame_mips64.h | 48 (1 << art::mips64::T1) | (1 << art::mips64::T2) | (1 << art::mips64::T3) |
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 47 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
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| /art/compiler/optimizing/ |
| D | code_generator_mips.h | 35 { A1, A2, A3, T0, T1 };
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 115 registers_.push_back(new mips64::GpuRegister(mips64::T1)); in SetUpHelpers()
148 secondary_register_names_.emplace(mips64::GpuRegister(mips64::T1), "t1"); in SetUpHelpers()
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