| /art/compiler/jni/quick/x86/ |
| D | calling_convention_x86.cc | 158 ManagedRegister in_reg = CurrentParamRegister(); in EntrySpills() local
160 if (!in_reg.IsNoRegister()) { in EntrySpills()
163 ManagedRegisterSpill spill(in_reg, size, spill_offset); in EntrySpills()
167 in_reg = CurrentParamHighLongRegister(); in EntrySpills()
168 DCHECK(!in_reg.IsNoRegister()); in EntrySpills()
170 ManagedRegisterSpill spill2(in_reg, size, spill_offset + 4); in EntrySpills()
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| /art/compiler/jni/quick/ |
| D | jni_compiler.cc | 62 ManagedRegister in_reg);
283 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
284 __ VerifyObject(in_reg, mr_conv->IsCurrentArgPossiblyNull()); in ArtJniCompileMethodInternal()
285 __ StoreRef(handle_scope_offset, in_reg); in ArtJniCompileMethodInternal()
692 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in CopyParameter() local
695 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, in_reg, null_allowed); in CopyParameter()
699 __ Move(out_reg, in_reg, mr_conv->CurrentParamSize()); in CopyParameter()
729 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in CopyParameter() local
742 __ Store(out_off, in_reg, param_size); in CopyParameter()
747 __ StoreSpanning(out_off, in_reg, in_off, mr_conv->InterproceduralScratchRegister()); in CopyParameter()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 479 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); in CreateHandleScopeEntry() local
480 if (in_reg.IsNoRegister()) { // TODO(64): && null_allowed in CreateHandleScopeEntry()
482 in_reg = out_reg; in CreateHandleScopeEntry()
484 __ movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); in CreateHandleScopeEntry()
486 CHECK(in_reg.IsCpuRegister()); in CreateHandleScopeEntry()
488 VerifyObject(in_reg, null_allowed); in CreateHandleScopeEntry()
491 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
494 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in CreateHandleScopeEntry()
526 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); in LoadReferenceFromHandleScope() local
528 CHECK(in_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_x86_64.h | 157 ManagedRegister in_reg,
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 428 X86ManagedRegister in_reg = min_reg.AsX86(); in CreateHandleScopeEntry() local
429 CHECK(in_reg.IsCpuRegister()); in CreateHandleScopeEntry()
431 VerifyObject(in_reg, null_allowed); in CreateHandleScopeEntry()
434 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
437 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in CreateHandleScopeEntry()
469 X86ManagedRegister in_reg = min_reg.AsX86(); in LoadReferenceFromHandleScope() local
471 CHECK(in_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
473 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
476 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in LoadReferenceFromHandleScope()
478 __ movl(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0)); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_x86.h | 134 ManagedRegister in_reg, bool null_allowed) override;
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 562 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); in CreateHandleScopeEntry() local
564 CHECK(in_reg.IsNoRegister() || in_reg.IsXRegister()) << in_reg; in CreateHandleScopeEntry()
570 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
573 in_reg = out_reg; in CreateHandleScopeEntry()
575 ___ Cmp(reg_w(in_reg.AsOverlappingWRegister()), 0); in CreateHandleScopeEntry()
576 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
609 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); in LoadReferenceFromHandleScope() local
611 CHECK(in_reg.IsXRegister()) << in_reg; in LoadReferenceFromHandleScope()
613 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
617 ___ Cbz(reg_x(in_reg.AsXRegister()), &exit); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_arm64.h | 147 ManagedRegister in_reg,
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| /art/compiler/jni/quick/x86_64/ |
| D | calling_convention_x86_64.cc | 163 ManagedRegister in_reg = CurrentParamRegister(); in EntrySpills() local
164 if (!in_reg.IsNoRegister()) { in EntrySpills()
167 ManagedRegisterSpill spill(in_reg, size, spill_offset); in EntrySpills()
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 487 vixl::aarch32::Register in_reg = in CreateHandleScopeEntry() local
495 if (!in_reg.IsValid()) { in CreateHandleScopeEntry()
497 in_reg = out_reg; in CreateHandleScopeEntry()
500 temps.Exclude(in_reg); in CreateHandleScopeEntry()
501 ___ Cmp(in_reg, 0); in CreateHandleScopeEntry()
504 if (!out_reg.Is(in_reg)) { in CreateHandleScopeEntry()
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| D | jni_macro_assembler_arm_vixl.h | 165 ManagedRegister in_reg,
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| /art/tools/dexanalyze/ |
| D | dexanalyze_bytecode.cc | 439 uint32_t in_reg = inst->VRegB_22c(); in ProcessCodeItem() local
445 ExtendPrefix(&in_reg, &local_type); in ProcessCodeItem()
446 CHECK(InstNibbles(new_opcode, {in_reg, out_reg, local_type})); in ProcessCodeItem()
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| /art/compiler/utils/ |
| D | jni_macro_assembler.h | 182 ManagedRegister in_reg,
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3957 Mips64ManagedRegister in_reg = min_reg.AsMips64(); in CreateHandleScopeEntry() local
3958 CHECK(in_reg.IsNoRegister() || in_reg.IsGpuRegister()) << in_reg; in CreateHandleScopeEntry()
3965 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
3968 in_reg = out_reg; in CreateHandleScopeEntry()
3970 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
3973 Beqzc(in_reg.AsGpuRegister(), &null_arg); in CreateHandleScopeEntry()
4007 Mips64ManagedRegister in_reg = min_reg.AsMips64(); in LoadReferenceFromHandleScope() local
4009 CHECK(in_reg.IsGpuRegister()) << in_reg; in LoadReferenceFromHandleScope()
4011 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
4014 Beqzc(in_reg.AsGpuRegister(), &null_arg); in LoadReferenceFromHandleScope()
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| D | assembler_mips64.h | 1412 ManagedRegister in_reg, bool null_allowed) override;
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 5122 MipsManagedRegister in_reg = min_reg.AsMips(); in CreateHandleScopeEntry() local
5123 CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg; in CreateHandleScopeEntry()
5130 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
5133 in_reg = out_reg; in CreateHandleScopeEntry()
5135 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
5138 Beqz(in_reg.AsCoreRegister(), &null_arg); in CreateHandleScopeEntry()
5171 MipsManagedRegister in_reg = min_reg.AsMips(); in LoadReferenceFromHandleScope() local
5173 CHECK(in_reg.IsCoreRegister()) << in_reg; in LoadReferenceFromHandleScope()
5175 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
5178 Beqz(in_reg.AsCoreRegister(), &null_arg); in LoadReferenceFromHandleScope()
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| D | assembler_mips.h | 1344 ManagedRegister in_reg,
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| /art/compiler/optimizing/ |
| D | intrinsics_arm_vixl.cc | 466 vixl32::SRegister in_reg = InputSRegisterAt(invoke, 0); in VisitMathRoundFloat() local
474 __ Vcvta(S32, F32, temp1, in_reg); in VisitMathRoundFloat()
484 __ Vrinta(F32, temp1, in_reg); in VisitMathRoundFloat()
486 __ Vsub(F32, temp1, in_reg, temp1); in VisitMathRoundFloat()
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| D | intrinsics_arm64.cc | 594 FPRegister in_reg = is_double ? DRegisterFrom(l->InAt(0)) : SRegisterFrom(l->InAt(0)); in GenMathRound() local
600 __ Fcvtas(out_reg, in_reg); in GenMathRound()
608 __ Frinta(tmp_fp, in_reg); in GenMathRound()
609 __ Fsub(tmp_fp, in_reg, tmp_fp); in GenMathRound()
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| D | code_generator_arm64.cc | 5313 Register in_reg = InputRegisterAt(abs, 0); in VisitAbs() local
5315 __ Cmp(in_reg, Operand(0)); in VisitAbs()
5316 __ Cneg(out_reg, in_reg, lt); in VisitAbs()
5321 FPRegister in_reg = InputFPRegisterAt(abs, 0); in VisitAbs() local
5323 __ Fabs(out_reg, in_reg); in VisitAbs()
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| D | code_generator_arm_vixl.cc | 4571 vixl32::Register in_reg = RegisterFrom(locations->InAt(0)); in VisitAbs() local
4574 __ Asr(mask, in_reg, 31); in VisitAbs()
4575 __ Add(out_reg, in_reg, mask); in VisitAbs()
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