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/art/runtime/interpreter/mterp/arm64/
Darithmetic.S1 %def binop(preinstr="", result="w0", chkzero="0", instr=""):
29 $instr // $result<- op, w0-w3 changed
35 %def binop2addr(preinstr="", result="w0", chkzero="0", instr=""):
60 $instr // $result<- op, w0-w3 changed
66 %def binopLit16(preinstr="", result="w0", chkzero="0", instr=""):
89 $instr // $result<- op, w0-w3 changed
95 %def binopLit8(extract="asr w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""):
124 $instr // $result<- op, w0-w3 changed
130 %def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"):
155 $instr // $result<- op, w0-w4 changed
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Dfloating_point.S1 %def fbinop(instr=""):
14 $instr // s0<- op
21 %def fbinopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2"):
33 $instr // $result<- op, w0-w4 changed
38 %def fbinop2addr(instr=""):
51 $instr // s2<- op
57 %def fbinopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1"):
67 $instr // result<- op
97 %def funopNarrow(srcreg="s0", tgtreg="d0", instr=""):
110 $instr // d0<- op
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/art/compiler/optimizing/
Dscheduler_arm64.cc26 void SchedulingLatencyVisitorARM64::VisitBinaryOperation(HBinaryOperation* instr) { in VisitBinaryOperation() argument
27 last_visited_latency_ = DataType::IsFloatingPointType(instr->GetResultType()) in VisitBinaryOperation()
50 HIntermediateAddressIndex* instr ATTRIBUTE_UNUSED) { in VisitIntermediateAddressIndex()
82 void SchedulingLatencyVisitorARM64::VisitDiv(HDiv* instr) { in VisitDiv() argument
83 DataType::Type type = instr->GetResultType(); in VisitDiv()
93 if (instr->GetRight()->IsConstant()) { in VisitDiv()
94 int64_t imm = Int64FromConstant(instr->GetRight()->AsConstant()); in VisitDiv()
135 void SchedulingLatencyVisitorARM64::VisitMul(HMul* instr) { in VisitMul() argument
136 last_visited_latency_ = DataType::IsFloatingPointType(instr->GetResultType()) in VisitMul()
196 void SchedulingLatencyVisitorARM64::VisitTypeConversion(HTypeConversion* instr) { in VisitTypeConversion() argument
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Dreference_type_propagation.cc102 void VisitLoadMethodHandle(HLoadMethodHandle* instr) override;
103 void VisitLoadMethodType(HLoadMethodType* instr) override;
104 void VisitLoadString(HLoadString* instr) override;
105 void VisitLoadException(HLoadException* instr) override;
106 void VisitNewArray(HNewArray* instr) override;
107 void VisitParameterValue(HParameterValue* instr) override;
108 void VisitInstanceFieldGet(HInstanceFieldGet* instr) override;
109 void VisitStaticFieldGet(HStaticFieldGet* instr) override;
110 void VisitUnresolvedInstanceFieldGet(HUnresolvedInstanceFieldGet* instr) override;
111 void VisitUnresolvedStaticFieldGet(HUnresolvedStaticFieldGet* instr) override;
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Dcommon_arm.h96 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) { in OutputSRegister() argument
97 DataType::Type type = instr->GetType(); in OutputSRegister()
99 return SRegisterFrom(instr->GetLocations()->Out()); in OutputSRegister()
102 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) { in OutputDRegister() argument
103 DataType::Type type = instr->GetType(); in OutputDRegister()
105 return DRegisterFrom(instr->GetLocations()->Out()); in OutputDRegister()
108 inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) { in OutputVRegister() argument
109 DataType::Type type = instr->GetType(); in OutputVRegister()
111 return OutputSRegister(instr); in OutputVRegister()
113 return OutputDRegister(instr); in OutputVRegister()
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Dcommon_arm64.h81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister() argument
82 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt() argument
86 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
87 instr->InputAt(input_index)->GetType()); in InputRegisterAt()
115 inline vixl::aarch64::FPRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister() argument
116 return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputFPRegister()
119 inline vixl::aarch64::FPRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt() argument
120 return FPRegisterFrom(instr->GetLocations()->InAt(input_index), in InputFPRegisterAt()
121 instr->InputAt(input_index)->GetType()); in InputFPRegisterAt()
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Dinstruction_simplifier_shared.h41 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { in HasShifterOperand() argument
44 bool res = instr->IsAdd() || instr->IsAnd() || in HasShifterOperand()
45 (isa == InstructionSet::kArm64 && instr->IsNeg()) || in HasShifterOperand()
46 instr->IsOr() || instr->IsSub() || instr->IsXor(); in HasShifterOperand()
Dselect_generator_test.cc29 void ConstructBasicGraphForSelect(HInstruction* instr) { in ConstructBasicGraphForSelect() argument
54 then_block->AddInstruction(instr); in ConstructBasicGraphForSelect()
61 phi->AddInput(instr); in ConstructBasicGraphForSelect()
78 HDivZeroCheck* instr = new (GetAllocator()) HDivZeroCheck(parameter_, 0); in TEST_F() local
79 ConstructBasicGraphForSelect(instr); in TEST_F()
83 ManuallyBuildEnvFor(instr, &current_locals); in TEST_F()
91 HAdd* instr = new (GetAllocator()) HAdd(DataType::Type::kInt32, parameter_, parameter_, 0); in TEST_F() local
92 ConstructBasicGraphForSelect(instr); in TEST_F()
Dscheduler_arm.cc32 void SchedulingLatencyVisitorARM::HandleBinaryOperationLantencies(HBinaryOperation* instr) { in HandleBinaryOperationLantencies() argument
33 switch (instr->GetResultType()) { in HandleBinaryOperationLantencies()
51 void SchedulingLatencyVisitorARM::VisitAdd(HAdd* instr) { in VisitAdd() argument
52 HandleBinaryOperationLantencies(instr); in VisitAdd()
55 void SchedulingLatencyVisitorARM::VisitSub(HSub* instr) { in VisitSub() argument
56 HandleBinaryOperationLantencies(instr); in VisitSub()
59 void SchedulingLatencyVisitorARM::VisitMul(HMul* instr) { in VisitMul() argument
60 switch (instr->GetResultType()) { in VisitMul()
75 void SchedulingLatencyVisitorARM::HandleBitwiseOperationLantencies(HBinaryOperation* instr) { in HandleBitwiseOperationLantencies() argument
76 switch (instr->GetResultType()) { in HandleBitwiseOperationLantencies()
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Dscheduler_arm64.h131 void HandleSimpleArithmeticSIMD(HVecOperation *instr);
163 bool IsSchedulingBarrier(const HInstruction* instr) const override { in IsSchedulingBarrier() argument
164 return HScheduler::IsSchedulingBarrier(instr) || in IsSchedulingBarrier()
165 instr->IsVecReduce() || in IsSchedulingBarrier()
166 instr->IsVecExtractScalar() || in IsSchedulingBarrier()
167 instr->IsVecSetScalars() || in IsSchedulingBarrier()
168 instr->IsVecReplicateScalar(); in IsSchedulingBarrier()
/art/runtime/interpreter/mterp/mips64/
Darithmetic.S1 %def binop(preinstr="", result="a0", chkzero="0", instr=""):
27 $instr # $result <- op, a0-a3 changed
32 %def binop2addr(preinstr="", result="a0", chkzero="0", instr=""):
58 $instr # $result <- op, a0-a3 changed
63 %def binopLit16(preinstr="", result="a0", chkzero="0", instr=""):
86 $instr # $result <- op, a0-a3 changed
92 %def binopLit8(preinstr="", result="a0", chkzero="0", instr=""):
116 $instr # $result <- op, a0-a3 changed
122 %def binopWide(preinstr="", result="a0", chkzero="0", instr=""):
148 $instr # $result <- op, a0-a3 changed
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Dfloating_point.S1 %def fbinop(instr=""):
14 $instr # f0 <- f0 op f1
20 %def fbinop2addr(instr=""):
32 $instr # f0 <- f0 op f1
38 %def fbinopWide(instr=""):
51 $instr # f0 <- f0 op f1
57 %def fbinopWide2addr(instr=""):
69 $instr # f0 <- f0 op f1
179 % fbinopWide(instr="add.d f0, f0, f1")
182 % fbinopWide2addr(instr="add.d f0, f0, f1")
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/art/runtime/interpreter/mterp/x86_64/
Darithmetic.S126 %def binop(result="%eax", instr=""):
140 $instr VREG_ADDRESS(%rcx),%eax
144 %def binop1(wide="0", instr=""):
155 $instr # ex: addl %ecx,%eax
159 $instr # ex: addl %ecx,%eax
164 %def binop2addr(result="%eax", instr=""):
180 $instr %eax, VREG_ADDRESS(%rcx)
184 %def binopLit16(result="%eax", instr=""):
200 $instr # for example: addl %ecx, %eax
204 %def binopLit8(result="%eax", instr=""):
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Dfloating_point.S55 %def sseBinop(instr="", suff=""):
59 ${instr}${suff} VREG_ADDRESS(%rax), %xmm0
65 %def sseBinop2Addr(instr="", suff=""):
70 ${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0
77 % sseBinop(instr="adds", suff="d")
80 % sseBinop2Addr(instr="adds", suff="d")
83 % sseBinop(instr="adds", suff="s")
86 % sseBinop2Addr(instr="adds", suff="s")
101 % sseBinop(instr="divs", suff="d")
104 % sseBinop2Addr(instr="divs", suff="d")
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/art/disassembler/
Ddisassembler_x86.cc164 RegFile dst_reg_file, const uint8_t** instr, in DumpAddress() argument
169 *address_bits = *reinterpret_cast<const uint32_t*>(*instr); in DumpAddress()
172 address << StringPrintf("[RIP + 0x%x]", *reinterpret_cast<const uint32_t*>(*instr)); in DumpAddress()
174 (*instr) += 4; in DumpAddress()
176 uint8_t sib = **instr; in DumpAddress()
177 (*instr)++; in DumpAddress()
209 address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr)); in DumpAddress()
212 *address_bits = *reinterpret_cast<const uint32_t*>(*instr); in DumpAddress()
215 (*instr) += 4; in DumpAddress()
218 address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr)); in DumpAddress()
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Ddisassembler_arm64.cc44 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, in AppendRegisterNameToOutput() argument
46 USE(instr); in AppendRegisterNameToOutput()
58 Disassembler::AppendRegisterNameToOutput(instr, reg); in AppendRegisterNameToOutput()
61 void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) { in VisitLoadLiteral() argument
62 Disassembler::VisitLoadLiteral(instr); in VisitLoadLiteral()
71 void* data_address = instr->GetLiteralAddress<void*>(); in VisitLoadLiteral()
78 Instr op = instr->Mask(LoadLiteralMask); in VisitLoadLiteral()
100 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) { in VisitLoadStoreUnsignedOffset() argument
101 Disassembler::VisitLoadStoreUnsignedOffset(instr); in VisitLoadStoreUnsignedOffset()
103 if (instr->GetRn() == TR) { in VisitLoadStoreUnsignedOffset()
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Ddisassembler_x86.h36 size_t DumpNops(std::ostream& os, const uint8_t* instr);
37 size_t DumpInstruction(std::ostream& os, const uint8_t* instr);
41 RegFile src_reg_file, RegFile dst_reg_file, const uint8_t** instr,
Ddisassembler_arm64.h47 void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
51 void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) override;
54 void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) override;
/art/runtime/interpreter/mterp/mips/
Darithmetic.S1 %def binop(preinstr="", result="a0", chkzero="0", instr=""):
30 $instr # $result <- op, a0-a3 changed
34 %def binop2addr(preinstr="", result="a0", chkzero="0", instr=""):
59 $instr # $result <- op, a0-a3 changed
63 %def binopLit16(preinstr="", result="a0", chkzero="0", instr=""):
88 $instr # $result <- op, a0-a3 changed
92 %def binopLit8(preinstr="", result="a0", chkzero="0", instr=""):
119 $instr # $result <- op, a0-a3 changed
123 …"", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""):
154 $instr # result <- op, a0-a3 changed
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Dfloating_point.S1 %def fbinop(instr=""):
17 $instr # f0 = result
21 %def fbinop2addr(instr=""):
37 $instr
41 %def fbinopWide(instr=""):
62 $instr
66 %def fbinopWide2addr(instr=""):
85 $instr
89 %def funop(instr=""):
102 $instr
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/art/runtime/
Dinstrumentation_test.cc193 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in CheckConfigureStubs() local
199 instr->ConfigureStubs(key, level); in CheckConfigureStubs()
220 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TestEvent() local
225 instr->AddListener(&listener, instrumentation_event); in TestEvent()
233 EXPECT_TRUE(HasEventListener(instr, instrumentation_event)); in TestEvent()
235 ReportEvent(instr, in TestEvent()
249 instr->RemoveListener(&listener, instrumentation_event); in TestEvent()
253 EXPECT_FALSE(HasEventListener(instr, instrumentation_event)); in TestEvent()
255 ReportEvent(instr, in TestEvent()
352 static bool HasEventListener(const instrumentation::Instrumentation* instr, uint32_t event_type) in HasEventListener() argument
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/art/runtime/interpreter/mterp/x86/
Dfloating_point.S37 %def fpcvt(instr="", load="", store="", wide="0"):
46 $instr
55 %def sseBinop(instr="", suff=""):
59 ${instr}${suff} VREG_ADDRESS(%eax), %xmm0
65 %def sseBinop2Addr(instr="", suff=""):
70 ${instr}${suff} VREG_ADDRESS(rINST), %xmm0
77 % sseBinop(instr="adds", suff="d")
80 % sseBinop2Addr(instr="adds", suff="d")
83 % sseBinop(instr="adds", suff="s")
86 % sseBinop2Addr(instr="adds", suff="s")
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Darithmetic.S142 %def binop(result="%eax", instr=""):
156 $instr VREG_ADDRESS(%ecx), %eax
160 %def binop1(result="%eax", tmp="%ecx", instr=""):
170 $instr # ex: addl %ecx,%eax
174 %def binop2addr(result="%eax", instr=""):
190 $instr %eax, VREG_ADDRESS(%ecx)
194 %def binopLit16(result="%eax", instr=""):
210 $instr # for example: addl %ecx, %eax
214 %def binopLit8(result="%eax", instr=""):
229 $instr # ex: addl %ecx,%eax
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/art/runtime/interpreter/mterp/arm/
Dfloating_point.S1 %def fbinop(instr=""):
20 $instr @ s2<- op
25 %def fbinop2addr(instr=""):
41 $instr @ s2<- op
458 % binopWide(instr="bl fmod")
462 % binopWide2addr(instr="bl fmod")
466 % binop(instr="bl fmodf")
470 % binop2addr(instr="bl fmodf")
473 % fbinopWide(instr="fsubd d2, d0, d1")
476 % fbinopWide2addr(instr="fsubd d2, d0, d1")
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Darithmetic.S1 %def binop(preinstr="", result="r0", chkzero="0", instr=""):
31 $instr @ $result<- op, r0-r3 changed
37 %def binop2addr(preinstr="", result="r0", chkzero="0", instr=""):
64 $instr @ $result<- op, r0-r3 changed
70 %def binopLit16(result="r0", chkzero="0", instr=""):
94 $instr @ $result<- op, r0-r3 changed
100 %def binopLit8(extract="asr r1, r3, #8", result="r0", chkzero="0", instr=""):
130 $instr @ $result<- op, r0-r3 changed
136 %def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""):
169 $instr @ result<- op, r0-r3 changed
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