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Searched refs:lr (Results 1 – 24 of 24) sorted by relevance

/art/runtime/arch/arm/
Dmemcmp16_arm.S39 bxeq lr
61 bxne lr
64 bx lr
68 0: push {r4, lr}
71 .cfi_rel_offset lr, 4
82 popne {r4, lr}
83 bxne lr
109 ldr lr, [r1, #4]!
113 eorseq r0, r0, lr
115 ldreq lr, [r1, #4]!
[all …]
Djni_entrypoints_arm.S24 push {r0, r1, r2, r3, lr} @ spill regs
30 .cfi_rel_offset lr, 16
38 pop {r0, r1, r2, r3, lr} @ restore regs
44 .cfi_restore lr
Dquick_entrypoints_arm.S31 push {r4-r11, lr} @ 9 words (36 bytes) of callee saves.
41 .cfi_rel_offset lr, 32
74 push {r5-r8, r10-r11, lr} @ 7 words of callee saves
82 .cfi_rel_offset lr, 24
103 pop {r5-r8, r10-r11, lr} @ 7 words of callee saves
110 .cfi_restore lr
122 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
133 .cfi_rel_offset lr, 36
167 pop {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves
177 .cfi_restore lr
[all …]
Dinstruction_set_features_assembly_tests.S41 bx lr
64 bx lr
/art/runtime/interpreter/mterp/arm/
Dcontrol_flow.S147 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
149 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
162 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
164 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
171 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
173 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
186 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
188 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
Dfloating_point.S22 SET_VREG_FLOAT s2, r9, lr @ vAA<- s2
352 bx lr @ return
392 bx lr @ return
Darithmetic.S166 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
201 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
269 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
292 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
547 umull r1, lr, r2, r0 @ r1/lr <- ZxX
550 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX))
551 CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs
575 umull r1, lr, r2, r0 @ r1/lr <- ZxX
579 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX))
785 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
[all …]
Dother.S116 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
129 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
280 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
294 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
306 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA]
310 SET_VREG_WIDE_BY_ADDR r0, r1, lr @ fp[AAAA]<- r0/r1
322 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
Dmain.S385 stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64)
396 .cfi_rel_offset lr, 36
Dobject.S161 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs
Darray.S86 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
/art/runtime/interpreter/mterp/arm64/
Dmain.S408 SAVE_TWO_REGS fp, lr, 64
607 ldr lr, [xSELF, #THREAD_FLAGS_OFFSET]
611 ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
749 RESTORE_TWO_REGS fp, lr, 64
767 RESTORE_TWO_REGS fp, lr, 64
/art/compiler/jni/
Djni_cfi_test_expected.inc20 // 0x00000000: push {r5,r6,r7,r8,r10,r11,lr}
79 // 0x00000020: pop {r5,r6,r7,r8,r10,r11,lr}
81 // 0x00000028: bx lr
127 // 0x00000018: stp x29, lr, [sp, #176]
167 // 0x0000005c: ldp x29, lr, [sp, #176]
/art/compiler/optimizing/
Doptimizing_cfi_test_expected.inc11 // 0x00000000: push {r5, r6, lr}
47 // 0x00000008: stp x22, lr, [sp, #48]
59 // 0x00000018: ldp x22, lr, [sp, #48]
241 // 0x00000000: push {r5, r6, lr}
Dcode_generator_arm64.cc909 AddAllocatedRegister(LocationFrom(lr)); in CodeGeneratorARM64()
1690 __ Ldr(lr, MemOperand(tr, GetThreadOffset<kArm64PointerSize>(entrypoint).Int32Value())); in InvokeRuntime()
1694 __ blr(lr); in InvokeRuntime()
1705 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in InvokeRuntimeWithoutRecordingPcInfo()
1706 __ Blr(lr); in InvokeRuntimeWithoutRecordingPcInfo()
4013 __ Ldr(lr, MemOperand(temp, entry_point.Int32Value())); in VisitInvokeInterface()
4020 __ blr(lr); in VisitInvokeInterface()
4137 __ Ldr(lr, MemOperand( in GenerateStaticOrDirectCall()
4146 __ blr(lr); in GenerateStaticOrDirectCall()
4188 __ Ldr(lr, MemOperand(temp, entry_point.SizeValue())); in GenerateVirtualCall()
[all …]
Dcode_generator_arm_vixl.cc2169 __ Bx(lr); in GenerateFrameExit()
2386 __ Ldr(lr, MemOperand(tr, GetThreadOffset<kArmPointerSize>(entrypoint).Int32Value())); in InvokeRuntime()
2392 __ blx(lr); in InvokeRuntime()
2402 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in InvokeRuntimeWithoutRecordingPcInfo()
2403 __ Blx(lr); in InvokeRuntimeWithoutRecordingPcInfo()
3252 GetAssembler()->LoadFromOffset(kLoadWord, lr, temp, entry_point); in VisitInvokeInterface()
3278 __ blx(lr); in VisitInvokeInterface()
8364 EmitAdrCode adr(GetVIXLAssembler(), lr, &return_address); in GenerateGcRootFieldLoad()
8410 EmitAdrCode adr(GetVIXLAssembler(), lr, &return_address); in GenerateUnsafeCasOldValueAddWithBakerReadBarrier()
8469 EmitAdrCode adr(GetVIXLAssembler(), lr, &return_address); in GenerateFieldLoadWithBakerReadBarrier()
[all …]
Dcode_generator_arm64.h93 vixl::aarch64::lr);
800 DCHECK(reg < vixl::aarch64::lr.GetCode() && in CheckValidReg()
Dcode_generator_arm_vixl.h93 vixl::aarch32::lr));
/art/compiler/utils/
Dassembler_thumb_test_expected.cc.inc2 " 0: e92d 4de0 stmdb sp!, {r5, r6, r7, r8, sl, fp, lr}\n",
152 " 218: e8bd 4de0 ldmia.w sp!, {r5, r6, r7, r8, sl, fp, lr}\n",
154 " 220: 4770 bx lr\n",
/art/runtime/arch/arm64/
Dquick_entrypoints_arm64.S520 .cfi_rel_offset lr, 0
525 mov x0, lr // pass the fault address stored in LR by the fault handler.
1066 str lr, [sp, x1]
2314 br lr
2676 br lr // Do not use RET as we do not enter the entrypoint with "BL".
2739 ldr x0, [lr, #\ldr_offset] // Load the instruction.
2815 ldr wIP1, [lr, #BAKER_MARK_INTROSPECTION_FIELD_LDR_OFFSET] // Load the instruction.
/art/runtime/
Dinstrumentation.cc1341 uintptr_t lr, bool interpreter_entry) { in PushInstrumentationStackFrame() argument
1346 << reinterpret_cast<void*>(lr); in PushInstrumentationStackFrame()
1365 instrumentation::InstrumentationStackFrame instrumentation_frame(h_this.Get(), method, lr, in PushInstrumentationStackFrame()
Dinstrumentation.h473 ArtMethod* method, uintptr_t lr,
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc208 ___ Bx(vixl32::lr); in RemoveFrame()
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc631 EXPECT_TRUE(vixl::aarch64::lr.Is(Arm64Assembler::reg_x(LR))); in TEST()