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Searched refs:method_reg (Results 1 – 14 of 14) sorted by relevance

/art/compiler/utils/x86/
Djni_macro_assembler_x86.h46 ManagedRegister method_reg,
Djni_macro_assembler_x86.cc45 ManagedRegister method_reg, in BuildFrame() argument
66 __ pushl(method_reg.AsX86().AsCpuRegister()); in BuildFrame()
/art/compiler/utils/x86_64/
Djni_macro_assembler_x86_64.h47 ManagedRegister method_reg,
Djni_macro_assembler_x86_64.cc39 ManagedRegister method_reg, in BuildFrame() argument
76 __ movq(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister()); in BuildFrame()
Dassembler_x86_64_test.cc2058 x86_64::X86_64ManagedRegister method_reg = ManagedFromCpu(x86_64::RDI); in buildframe_test_fn() local
2061 assembler->BuildFrame(frame_size, method_reg, spill_regs, entry_spills); in buildframe_test_fn()
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.h53 ManagedRegister method_reg,
Djni_macro_assembler_arm_vixl.cc82 ManagedRegister method_reg, in BuildFrame() argument
86 CHECK(r0.Is(AsVIXLRegister(method_reg.AsArm()))); in BuildFrame()
/art/compiler/utils/
Djni_macro_assembler.h65 ManagedRegister method_reg,
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.h56 ManagedRegister method_reg,
Djni_macro_assembler_arm64.cc687 ManagedRegister method_reg, in BuildFrame() argument
717 DCHECK(X0 == method_reg.AsArm64().AsXRegister()); in BuildFrame()
/art/compiler/utils/mips64/
Dassembler_mips64.cc3611 ManagedRegister method_reg, in BuildFrame() argument
3632 StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0); in BuildFrame()
Dassembler_mips64.h1323 ManagedRegister method_reg,
/art/compiler/utils/mips/
Dassembler_mips.h1233 ManagedRegister method_reg,
Dassembler_mips.cc4779 ManagedRegister method_reg, in BuildFrame() argument
4800 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0); in BuildFrame()